Vellore
VIT
of Technology
Institute
SchoolofElectronies
Engineering
Fall
Semester 2023 -24
ContinuousAssessment Test - II
Programme Name & Branch:M.Tech- VLSIDesign Duration:90 Min
Course Code: MVLD503L Design with FPGA
CourseName: Digital
Maximum Marks:50 Marks Slot:C2 Class Number: VL2023240107492
Answer all
the Questions (5 X 10 = 50 Marks)
S.No C B Mark
Question
L
Write a verilogcode
structural to generate the following
sequence 1,3, 7, 6, 4, 0, 1 ....
Verify the code with an
. 3 L3 10
testbench.
appropriate
program to count number of
Write a verilog 1'sand 0's of a
32-bitinput data using task and functionsand display the
3 L3 10
message.
8. Develop a VerilogHDL usingbehavioural
modelling
to get the
followingwaveform as shown below. (Hint: f is the control
signal)
Deta in 2a
2 01 3 L6 10
rst
ck ELLLLLL
s9out 002 2b 2 2d 2
4. Sketch the output waveform forthe following
code as per the
shown below.
input condition
module example (w,x,y,z, a, b);
output w,X.y,z;
input a, b;
reg w,x,y,z;
always @ (a orb)
begin
#2 w = #3 a & b;
#3 x = #2 w & b; 3 L6 10
end
always @ (aor b)
#2 y <=#3 a & b;
always @ (a orb)
#3 z <= #2 a& b
endmodule
4 ps ps 12 ps 16 ps 20 ps 24 ps
8
ps
||0
5. Sketch the output and the hardware inferredforthe code given
below.
module ctr _a(output [9:0]count,input clk );
last count;
reg [9:0]
assigncount = last count + 1:
always @( posedge clk)
last count < count;
10
3 L6
endmodule
module ctr b(outputreg [9:0]count,input clk );
wire(9:0];
assignnext count = count + 1:
always @( posedge clk)
count <= next count;
endmodule
REG.NO.:
(Deemed
VIT
VelloreInstitute
of Technology
o he Uversity undersetion of UGC Ad, 198o)
J
SCHOOL OF ELECTRONICS ENGINECRING
CONTINUOUS ASSESSMENT TEST - H SLOT: E1
FALL SEMESTER 2024-2025
Programme Name & Branch :M.Tech VLSIDesign
Course Code and CourseName :MVLD503L-Digital Designwith FPGA
Faculty Name(s) :
Prof.SivasankaranK,Prof.JagannadhaNaiduK
ClassNumber(s) :VL2024250106594, VL2024250106596
Date ofExamination :17-10-2024
Exam Duration :90minutes Maximum Marks: 50
Generalinstruction(s):
Answer Questions
All
M- Max mark; C0 -CourseOutcome; BL - Blooms Taxonomy Level(1-Remember, 2
3 -Apply, 4
Understand, - Analyse,5 - Evaluate,
6 - Create)
CourseOutcomes
CO3: Design and implement sequentialdigital usingBehavioral
circuits Modeling
C04: Understand and develop data-pathand controller
design
Question M COBL
No
1. Draw the logicdiagram inferred
by the followingVerilog
code.
module fir
(input CLK,
input reset, 1/initialize
registers
input [7:0] Din, // Data input for load
output reg [7:0] Dout) :
reg [7:0] DO, D1, D2, D3;
localparam C0 = 4, Cl = 3, C2 = 2, C3 = 1;
always (posedge CLK) begin
@
10
if begin
(reset)
DO <= 0: D1 <= 0; D2 <= 0; D3 <= 0: 3 3
end elsebegin
D3 <= Din; D2 <= D3; D1 <= D2; DO <= D1;
Dout <= C0 * D0 + C1 * D1 + C2 * D2 + C3 * D3:
end
end
endmodule // fir
2. Draw the statediagram for a statemachine whose output goes
high when
the input is high forfouror more clock cycles.As shown inthe timing
diagram, the output shouldgo high duringthe fourth clock cycle and
remain high so long as the input does. Input and statetransitions 10
occur
shortly
afterthe clock rising
edge. Writesynthesizable
Verilog
code by 4 6
adopting FSM coding guidelines.
Page 1of 3
REG.NO.:
VelloreInstitute
(Decmod te be
VIT
ofTechnology
Universityundersection orUGC Act, 1956)
A
SCHOOL OF ELECTRONICS ENGINEERING
CONTINUOUS ASSESSMENT TEST - II SLOT:E1
FALL SEMESTER 2024-2025
Cock
IN
OUT
3. a)Ifthe following
code isnot legal,not synthesizable,
ordoes not follow
good codingpractices,
explainwhy.
always @ (posedge clk ora) always @(weekend or
begin go_to beach)
if(rst) begin
y= a + b; 5
if(weekend) 3 3
else action<=go to beach
y<=1'b0; elseif(weekday)
end action<= go_to work;
end
b) Writethe Verilogcode fora functionwhich takes 3
integerinputsand
returnsthe product of them. 5
4. A synchronous4-bitUP/DOWN binarycounter has a synchronousclear
signalCLR and a synchronousloadsignal LD. CLR has higherpriority than
LD. BothCLR and LD are activehigh.D isa 4-bit inputto the
counter,and
Q isthe 4-bit output from the
counter.UP is a signalthatcontrolsthe
direction
ofcounting.IfCLR and LD are not activeand UP is 1,the counter
increments.IfCLR and LD are not activead UP is 0, the counter
decrements.All changes occuron the falling
edge of theclock.
(a)Writea Behavioral Verilogdescriptionof the counter. 3 3
10
(b)Use the foregoing UP/DOWN
counterto implement a synchronous
modulo 6 counterthatcounts from 1to 6. Thismodulo 6 counter has an
external makes thecount to 1.
reset,which,ifapplied, A count enablesignal
CNT makes itcountinthe sequence 1, 2, 3, 4, 5, 6, 1,
2, incrementing ..,
once foreach clock pulse.You shoulduse any necessarylogicto make the
countergo to count =1aftercount=6.The modulo 6 countercountsonly in
the UP sequence.Writea Behavioral
Verilog
description
forthe modulo-6
counterinpart (b).
5. For the circuit
given below,Writethe synthesizable
Behavioral
Verilog
code. At the beginning isat 0 leveland y1=0,y2=0. Fill
the clocksignal the
10
restof the tablebelow fory1,y2 (whichcan be 0 or 1)and Z output (which 3 3
can be oneofthegiven 8 letters).
Page 2 of 3
REG.NO.:
VIT
(Dbemed te be
VIT
VelloreInstitute
ofTechnology
Univeityundersection 1 ofUGC At, 1056)
SCHOOL OF ELECTRONICS ENGINEERING
SLOT: E1
CONTINUOUS ASSESSMENT TEST - II
FALL SEMESTER 2024-2025
1 yl |J2 y2
1
KI K2
clock
MSB d
f
LSE
3 h
1 2x1
MUX
0
At the beginning
Afterthe 1stpulse
Afterthe 2nd pulse
Afterthe 3rd pulse
Afterthe 4th pulse
Page 3 of3
