Ahmed Abouellail

Faculty of Engineering
Sphinx University

MICROPROCESSORS
Introduction
A Historical Background & Basic Concepts
The Mechanical Age The Analytical Engine required more than 50,000
machined parts, which could not be made with enough
The idea of a computing system is not new—it has been precision to allow his engine to function reliably.
around long before modem electrical and electronic
devices were developed. The idea of calculating The Electrical Age
with a machine dates to 500 BC when
the Babylonians, the ancestors of the The 1800s saw the advent of the electric motor
present-day Iraqis, invented the abacus, (conceived by Michael Faraday). These
the first mechanical calculator. electrically driven mechanical
calculators were common pieces of
The abacus was not improved until 1642, when office equipment.
mathematician Blaise Pascal invented a calculator that
was constructed of gears and wheels. In 1889, Herman Hollerith developed a mechanical
The PASCAL programming language machine—driven by one of the new electric motors—that
is named in honor of Blaise Pascal for counted, sorted information. Mechanical
his pioneering work with the machines driven by electric motors
mechanical calculator. The arrival of continued to dominate the information
the first practical geared mechanical machines used to processing world until the construction of
automatically compute information dates to the early the first electronic calculating machine
1800s. in 1941.

Charles Babbage was commissioned in A German inventor named Konrad Zuse invented the first
1823 by the Royal Astronomical Society modern electromechanical computer.
of Great Britain to produce a
calculating machine.
His Z3 calculating computer was probably invented for The first general-purpose, programmable electronic
use in aircraft and missile design during World War II for computer system was developed in 1946 at the University
the German war effort. The Z3 was a of Pennsylvania. This first modem computer was called
relay logic machine that was the ENIAC (Electronic Numerical Integrator and
clocked at 5.33 Hz (far slower than Calculator). The ENIAC was a huge machine, containing
the latest multiple GHz over 17,000 vacuum tubes and over 500 miles of wires.
microprocessors). This massive machine weighed over 30 tons, yet
performed only about 100,000 operations per second.
The ENIAC was programmed by
Later in 1939, Zuse constructed his first electromechanical rewiring its circuits—a process
computer system, called the Z2. that took many workers several
days to accomplish. The
workers changed the electrical
connections on plug-boards
that looked like early telephone
switchboards.
This first electronic computing system, which used
vacuum tubes, was invented by Alan Turing. Turing called Breakthroughs that followed were the development of
his machine Colossus, probably because of its size. the transistor on December 23,
Colossus was not programmable— 1947 at Bell Labs by John
it was a fixed-program computer Bardeen, William Shockley,
system, which today is often called and Walter Brattain.
a special purpose computer.
This was followed by the 1958 invention of the integrated One such early video game, a shuffleboard game, was
circuit by Jack Kilby of Texas Instruments. produced by Bailey. The main problems with this early
microprocessor were its speed, word width, and memory
size.

The evolution of the 4-bit microprocessor ended when

Intel released the 4040, an updated version of the earlier
4004. The 4040 operated at a higher speed, although it
In 1971, the integrated circuit led Intel engineers Federico lacked improvements in word width and memory size.
Faggin, Ted Hoff, and Stan Mazor to develop the 4004 The 4-bit microprocessor still survives in low-end
microprocessor—the device that applications such as microwave ovens and small control
started the microprocessor systems and is still available from some microprocessor
revolution that continues today manufacturers. Most calculators are still based on 4-bit
at an ever-accelerating pace. microprocessors that process 4-bit BCD (binary-coded
decimal) codes.

The Microprocessor Age Later in 1971, realizing that the microprocessor was a
commercially viable product, Intel Corporation released
The world’s first microprocessor, the Intel 4004, was a 4-bit the 8008—an extended 8-bit version of the 4004
microprocessor–programmable controller on a chip. It microprocessor which could address a 16KB memory.
addressed a mere 4096 bytes (4 KB), 4-bit-wide memory Intel recognized some limitations, so they introduced the
locations. The 4004 instruction set contained only 45 8080 microprocessor in 1973—the first of the modem 8-bit
instructions. The 4-bit microprocessor debuted in early microprocessors.
video game systems and small microprocessor-based
control systems.
In 1977, Intel Corporation introduced an updated version Improvements to the instruction set included multiply and
of the 8080—the 8085. The 8085 was to be the last 8-bit, divide instructions, which were missing on earlier
general-purpose microprocessor developed by Intel. microprocessors.
Although only slightly more advanced than an 8080
microprocessor, the 8085 executed software at an even
higher speed. The main advantages of the 8085 were its In addition, the number of instructions increased from 45
internal clock generator, internal system controller, and on the 4004, to 246 on the 8085, to well over 20,000
higher clock frequency. This higher level of component variations on the 8086 and 8088 microprocessors. Note
integration reduced the 8085’s cost and increased its that these microprocessors are called CISC (complex
usefulness. instruction set computers) because of the number and
complexity of instructions.
The Modern Microprocessor
The 16-bit microprocessor evolved mainly because of the
In 1978, Intel released the 8086 microprocessor; a year or need for larger memory systems. The popularity of the
so later, it released the 8088. Both devices are 16-bit Intel family was ensured in 1981, when IBM Corporation
microprocessors, which executed instructions in as little as decided to use the 8088 microprocessor in its personal
400 ns (2.5 MIPs, or 2.5 millions of instructions per second).
computer. Applications such as spreadsheets, word
This represented a major improvement over the
execution speed of the 8085. In addition, the 8086 and processors, spelling checkers, and computer-based
8088 addressed 1M byte of memory, which was 16 times thesauruses were memory-intensive and required more
more memory than the 8085 (A 1M-byte memory than the 64K bytes of memory found in 8-bit
contains 1024KB sized memory locations or 1,048,576 microprocessors to execute efficiently. The 16-bit 8086
bytes) and a 4-byte instruction cache. The featured and 8088 provided 1M byte of memory for these
instruction cache sped the operation of many sequences applications. Soon, even the 1M-byte memory system
of instructions and proved to be the basis for the much proved limiting for large databases and other
larger instruction caches found in modem applications. This led Intel to introduce the 80286
microprocessors.
microprocessor, an updated 8086, in 1983.
The 80286 microprocessor was almost identical to the The Pentium contained a 16K-byte cache, which contains an
8086 and 8088, except it addressed a 16M-byte memory 8K-byte instruction cache and an 8K-byte data cache.
system instead of a 1M-byte system. The instruction set of
the 80286 was almost identical to the 8086 and 8088, A 1995-entry from Intel is the Pentium Pro processor, formerly
except for a few additional instructions. named the P6 microprocessor. In addition to the internal 16K
level-one (L1) cache (8K for data and 8K for instructions) the
Pentium Pro processor also contains a 256K level-two (L2)
Applications began to demand faster microprocessor
cache. One other significant change is that the Pentium Pro
speeds, more memory, and wider data paths. This led to
processor uses three execution engines, so it can execute up
the arrival of the 80386 in 1986 by Intel Corporation. The to three instructions at a time. This represents a change from
80386 represented a major overhaul of the 16-bit 8086 the Pentium, which executes two instructions simultaneously.
architecture. The 80386 was Intel’s first practical 32-bit
microprocessor that contained a 32-bit data bus and a The Pentium II microprocessor (released in 1997) represents a
32-bit memory address. new direction for Intel. The microprocessor on the Pentium II
module is, actually, Pentium Pro with MMX extensions.
In 1989, Intel released the 80486 microprocessor, which
incorporated an 80386-like microprocessor. Although the The Pentium III (released in 1999) microprocessor uses a faster
80486 microprocessor was not radically different from the core than the Pentium II.
80386, it did include one substantial change — 8K byte
cache memory. The internal structure of the 80486 was The Pentium 4 microprocessor was first made available in late
modified from the 80386 to support instruction pipelining. 2000 and had enhancements for multimedia and graphics.

The most recent version of the Pentium is called the Core2 by

The Pentium, introduced in 1993, was similar to the 80386
Intel, where the biggest advancement is the inclusion of
and 80486 microprocessors. The memory system
multiple cores. Each core executes a separate task in a
contained up to 4G bytes. This microprocessor was program, which increases the speed of execution if a
originally labeled the P5 or 80586. program is written to take advantage of the multiple cores.
The superscaler technology uses many microprocessors,
but they all share the same register set. This new
technology contains many microprocessors, each
containing its own register set that is linked with the other
microprocessors’ registers. This technology offers true
parallel processing without writing any special program.

The success of the Intel family is continuing with a new

technology jointly by Intel and Hewlett-Packard called
hyper-threading technology. The hyper-threading
technology provides even more parallel processors (more
than the present number of processor cores). The basic
premise behind this technology is that many
microprocessors communicate directly with each other,
allowing parallel processing without any change to the
instruction set or program.

The following figures show the internal structure of

microprocessors: the CPU, coprocessor, and cache
memory. This illustration shows the complexity and level of
integration in each version of the microprocessor
The Programming Model
The programming model of the 8086 through the Core2 is
considered to be program visible because its registers
are used during application programming and are
specified by the instructions.

Other registers, are considered to be program invisible

because they are not addressable directly during
applications programming, but may be used indirectly
during system programming. Only the 80286 and above
contain the program-invisible registers used to control
and operate the protected memory system and other
features of the microprocessor.

The shaded areas in this illustration represent registers that

are found in early versions of the 8086, 8088, or 80286
microprocessors and are provided on the 8086 through
the Core2 microprocessor including the 64-bit extensions
for compatibility to the early versions.

The earlier 8086, 8088, and 80286 contain 16-bit internal

architectures, as indicated in the shaded area. The
80386 through the Core2 microprocessors contain full 32-
bit internal architectures. Core2 microprocessor including
the 64-bit extensions contain 64-bit internal architecture.
Multipurpose Registers RBP (base pointer)
RBP points to a memory location in all versions of the
RAX (accumulator) microprocessor for memory data transfers.
The accumulator is used for instructions such as
multiplication, division, and some of the adjustment RDI (destination index)
instructions. RDI often addresses string destination data for the string
instructions.
RBX (base index)
The BX register sometimes holds the offset address of a RSI (source index)
location in the memory system in all versions of the The source index register often addresses source string
microprocessor. data for the string instructions.

RCX (count) R8 through R15

RCX is a general-purpose register that also holds the These general-purpose registers are only found in the
count for various instructions. Pentium 4 and Core2 if 64-bit extensions are enabled.
Instructions that use a count are the repeated string Data in these registers are addressed as 64-, 32-, 16-, or 8-
instructions (REP/REPE/REPNE); and shift, rotate, and bit sizes.
LOOP/LOOPD instructions.
Special-purpose Registers
RDX (data)
RDX is a general-purpose register that holds a part of the RIP (instruction pointer)
result from a multiplication or part of the dividend before RIP addresses the next instruction in a section of memory
a division. defined as a code segment.
RSP (stack pointer) Segment Registers
RSP addresses an area of memory called the stack.
The stack memory stores data through this pointer. Additional registers, called segment registers, generate
memory addresses when combined with other registers in
the microprocessor.
RFLAGS
RFLAGS indicate the condition of the microprocessor and CS (code)
control its operation. The code segment is a section of memory that holds the
The figure below shows the flag registers of all versions of code (programs and procedures) used by the
the microprocessor. microprocessor. The code segment register defines the
Note the flags are upward-compatible from the starting address of the section of memory holding code.
8086/8088 through the Core2 microprocessors.
The flags never change for any data transfer or program DS (data)
control operation. The data segment is a section of memory that contains
most data used by a program.
Some of the flags are also used to control features found Data are accessed in the data segment by an offset
in the microprocessor. address or the contents of other registers that hold the
The rightmost five flags and the overflow flag are offset address.
changed by most arithmetic and logic operations,
although data transfers do not affect them. ES (extra)
The extra segment is an additional data segment that is
used by some of the string instructions to hold destination
data.

SS (stack)
The stack segment defines the area of memory used for
the stack. The stack entry point is determined by the
stack segment and stack pointer registers.
Lecture 1
The 80x86 Microprocessor and Its Architecture

14
Inside The 8086 Intel implemented the concept of pipelining in the
8088/86 by splitting the internal structure of the
There are two ways to make the CPU process information microprocessor into two sections: the execution unit (EU)
faster. and the bus interface unit (BIU). These two sections work
simultaneously.
The first option is to increase the working frequency,
where the designer must use the required technology
and materials in making ICs (integrated circuits)
determine the working frequency, power consumption,
and the number of transistors packed into a single-chip
microprocessor. A detailed discussion of IC technology is
beyond the scope of this course.

The second option has to do with changing the internal

architecture of the CPU.

In the 8085 microprocessor, for example, the CPU could

either fetch or execute at a given time.

The idea of pipelining in its simplest form is to allow the

CPU to fetch and execute at the same time.
The BIU accesses memory and peripherals while the EU Assembly Language Programming
executes instructions previously fetched.

This works only if the BIU keeps ahead of the EU; thus, the While the CPU can work only in binary, it can do so at
BIU of the 8086 has a buffer, or queue. very high speeds. However, it is quite tedious and slow for
humans to deal with 0s and 1 s in order to program the
The buffer is 6 bytes in the 8086. If any instruction takes computer. A program that consists of 0s and 1 s is called
too long to execute, the queue is filled to its maximum machine language, and in the early days of the
capacity and the buses will sit idle. computer, programmers actually coded programs in
machine language.
The BIU fetches a new instruction whenever the queue
has room for 2 bytes in the 6-byte 8086 queue.
Although the hexadecimal system was used as a more
In some circumstances, the microprocessor must flush out efficient way to represent binary numbers, the process of
the queue. For example, when a jump instruction is working in machine code was still cumbersome for
executed, the BIU starts to fetch information from the new humans, so, eventually, Assembly languages were
location in memory and information in the queue that developed.
was fetched previously is discarded. In this situation the
EU must wait until the BIU fetches the new instruction. This Assembly language programs must be translated into
is referred to in computer science terminology as a machine code by a program called an assembler.
branch penalty. In a pipelined CPU, this means that too
much jumping around reduces the efficiency of a
Assembly language is referred to as a low-level language
program.
because it deals directly with the internals of the CPU.
Pipelining in the 8086 has two stages: fetch and execute,
but in more powerful computers pipelining can have To program in Assembly language, the programmer must
many stages. know the number of registers and their size, as well as
other details of the CPU.
Today, one can use many different programming For example, the instruction "MOV DX,CX" copies the
languages, such as C, Python and numerous others. contents of register CX to register DX.
These languages are called high-level languages
because the programmer does not have to be After this instruction is executed, register DX will have the
concerned with the internal details of the CPU. same value as register CX.

High-level languages are translated into machine code The MOV instruction does not affect the source operand.
by a program called a compiler. For instance, to write a
program in C, one must use a C compiler to translate the The following program first loads CL with value 55H, then
program into machine language. moves this value around to various registers inside the
CPU.
There are numerous assemblers available for translating
80x86 Assembly language programs into machine code.
One of the most commonly used assemblers is MASM by
Microsoft.

MOV Instruction

Simply stated, the MOV instruction copies data from one The use of l6-bit registers is demonstrated below.
location to another. It has the following format:

This instruction tells the CPU to move (copy) the source

operand to the destination operand.
Rules of MOV instruction 3. If a value less than FFH is moved into a 16-bit register,
the rest of the bits are assumed to be all zeros. For
1. In the 8086 CPU, data can be moved among all the example, in "MOV BX,5" the result will be BX = 0005; that is,
registers (except the flag register) as long as the source BH = 00 and BL = 05.
and destination registers match in size.
4. Moving a value that is too large into a register will
2. Data can not be moved directly into segment registers cause an error.
(CS, DS, ES, or SS), using the MOV instruction. For example,
look at the following instructions to see which are legal
and which are illegal.

ADD instruction

The ADD instruction has the following format:

The ADD instruction tells the CPU to add the source and
To load a value into a segment register, first load it to a the destination operands and put the result in the
nonsegment register and then move it to the segment destination.
register, as shown next.
To add two numbers such as 25H and 34H, each can be
moved to a register and then added together:
Executing the program results in AL = 59H (25H + 34H = 2. The largest number that an 8-bit register can hold is
59H) and BL = 34H. Notice that the contents of BL do not FFH. To use numbers larger than FFH (255 decimal), 16-bit
change. registers such as AX, BX, CX, or DX must be used. For
example, to add two numbers such as 34EH and 6A5H,
The program can be written in many ways, depending on the following program can be used:
the registers used. Another way might be:

Running the previous program gives DX = 9F3H (34E + 6A5

The program above results in DH = 59H and CL = 34H. = 9F3) and AX = 34E.
There are always many ways to write the same program.

Rules of ADD instruction 3. Again, any 16-bit nonsegment registers could have
been used to perform the action above:
1. It is not necessary to move both data items into
registers before adding them together. The source
operand can be either a register or immediate operand.
Look at the following variation of the same program: The general-purpose registers are typically used in
arithmetic operations. Register AX is sometimes referred
to as the accumulator.
Program Segments Logical Address and Physical Address

A segment is an area of memory that includes up to 64K In Intel literature concerning the 8086, there are three
bytes and begins on an address evenly divisible by 16 (such
types of addresses mentioned frequently: the physical
an address ends in 0H). A typical Assembly language
program consists of at least three segments: a code address, the offset address, and the logical address.
segment, a data segment, and a stack segment.
The physical address is the 20-bit address that is actually
The code segment contains the Assembly language put on the address pins of the 8086 microprocessor. This
instructions that perform the tasks that the program was address can have a range of 00000H to FFFFFH for the
designed to accomplish.
8086. This is an actual physical location in RAM or ROM
The data segment is used to store information (data) that within the 1-megabyte memory range.
needs to be processed by the instructions in the code
segment. The offset address is a location within a 64K-byte segment
range. Therefore, an offset address can range from 0000H
The stack segment is used to store information temporarily.
to FFFFH.
The extra segment is a segment register used as an extra
data segment. Although in many normal programs this The logical address consists of a segment value and an
segment is not used, its use is absolutely essential for string offset address.
operations.
The differences among these addresses and the process
In the 80x86 there can be up to 64KB of memory assigned to of converting from one to another is best understood in
each category. The 8086 can only handle a maximum of the context of some examples, as shown next.
64KB of code and 64KB of data and 64KB of stack at any
given time, although it has a range of 1MB of memory.
Code Segment

To execute a program, the 8086 fetches the instructions

(opcodes and operands) from the code segment.

The logical address of an instruction always consists of a

CS (code segment) and an IP (instruction pointer), shown
in CS:IP format.

The physical address for the location of the instruction is Since IP can have a minimum value of 0000H and a
generated by shifting the CS left one hex digit and then maximum of FFFFH, the logical address range in this example
is 2500:0000 to 2500:FFFF. This means that the lowest memory
adding it to the IP, which contains the offset address.
location of the code segment will be 25000H (25000 + 0000)
and the highest memory location will be 34FFFH (25000 +
The resulting 20-bit address is called the physical address FFFF).
since it is put on the external physical address bus pins to
be decoded by the memory decoding circuitry. Example 1-1

If CS = 24F6H and IP = 634AH, show:

(a) The logical address (b) The offset address
To clarify this important concept, assume values in CS and calculate:
and IP as shown below. (c) The physical address (d) The lower range
(e) The upper range of the code segment

Solution:
(a) 24F6:634A (b) 634A
(c) 2B2AA (24F60 + 634A) (d) 24F60 (24F60 + 0000)
(e) 34F5F (24F60 + FFFF)
Logical & physical addresses in the code segment The physical address is an actual location within RAM (or
even ROM).
In the code segment, CS and IP hold the logical address
of the instructions to be executed. The following are the physical addresses and the
The following Assembly language instructions have been contents of each location for the program above.
assembled (translated into machine code) and stored in Remember that it is the physical address that is put on the
memory. address bus by the 8086 CPU to be decoded by the
memory circuitry:

The program above shows that the byte at address

1132:0100 contains B0, which is the opcode for moving a
value into register AL, and address 1132:0101 contains the
operand (in this case 57) to be moved to AL.

Similarly, the machine code B686 is located in memory

locations 1132:0102 and 1132:0103 and represents the
opcode and the operand for the instruction "MOV
DH,86".
Data Segment Assume that the offset for the data segment begins at
200H. The data is placed in memory locations:
Assume that a program is being written to add 5 bytes of
data, such as 25H, 12H, 15H, 1FH, and 2BH, where each
byte represents a person's daily overtime pay. One way
to add them is as follows:

and the program can be rewritten as follows:

In the program above, the data and code are mixed

together in the instructions. The problem with writing the Notice that the offset address is enclosed in brackets. The
program this way is that if the data changes, the code brackets indicate that the operand represents the
must be searched for every place the data is included, address of the data and not the data itself.
and the data retyped. For this reason, the idea arose to
set aside an area of memory strictly for data. If the brackets were not included, as in "MOV AL,0200",
the CPU would attempt to move 200 into AL instead of
the contents of offset address 200.
In 80x86 microprocessors, the area of memory set aside
for data is called the data segment. Just as the code This program will run with any set of data. Changing the
segment is associated with CS and IP as its segment data has no effect on the code.
register and offset, the data segment uses register DS and
an offset value.
Although this program is an improvement over the The "INC" instruction adds 1 to (increments) its operand.
preceding one, it can be improved even further. "INC BX" achieves the same result as "ADD BX,1".

If the data had to be stored at a different offset address, For the program, if the offset address where data is
say 450H, the program would have to be rewritten. located is changed, only one instruction will need to be
modified, and the rest of the program will be unaffected.
One way to solve this problem would be to use a register
to hold the offset address, and before each ADD, to Examining the program above shows that there is a
increment the register to access the next byte. Next a pattern of two instructions being repeated. This leads to
decision must be made as to which register to use. the idea of using a loop to repeat certain instructions.

While CS uses only the IP register as an offset, DS uses only

BX, DI, and SI to hold the offset address of the data. Logical & physical addresses in the data segment

The term pointer is often used for a register holding an The physical address for data is calculated using the
offset address. In the following example, BX is used as a same rules as for the code segment.
pointer:
The physical address of data is calculated by shifting DS
left one hex digit and adding the offset value, as shown
in following examples.
Example 1-2 Example 1-3

Assume that DS is 5000 and the offset is 1950. Calculate If DS = 7FA2H and the offset is 438EH,
the physical address of the byte. (a) Calculate the physical address.
(b) Calculate the lower range.
(c) Calculate the upper range of the data segment.
(d) Show the logical address.

Solution:
Solution: (a) 830AE (7FA20 + 438E) (b) 7FA20 (7FA20 + 0000)
(c) 8FA1F (7FA20 + FFFF) (d) 7FA2:438E
The physical address will be 50000 + 1950 = 51950.

Example 1-4

Assume that the DS register is 578C. To access a given

byte of data at physical memory location 67F66, does the
data segment cover the range where the data is
located? If not, what changes need to be made?

Solution:
No, since the range is 578C0 to 678BF, location 67F66 is
not included in this range. To access that byte, DS must
be changed so that its range will include that byte.
Little Endian Convention Example 1-5

Previous examples used 8-bit or 1-byte data. In this case Assume memory locations with the following contents:
the bytes are stored one after another in memory. What DS:6826 = 48 and DS:6827 = 22.
happens when 16-bit data is used? For example: Show the contents of register BX in the instruction "MOV
BX,[6826]".

Solution:
In cases like this, the low byte goes to the low memory According to the little-endian convention used in all
location and the high byte goes to the high memory 80x86 microprocessors, register BL should contain the
address. value from the low offset address 6826 and register BH the
value from offset address 6827, giving BL = 48H and BH =
22H.
In the example above, memory location DS: 1500
contains F3H and memory location DS: 1501 contains 35H. DS:6826 = 48
DS:6827 = 22
In the big-endian method, the high byte goes to the low
address, whereas in the little-endian method, the high
byte goes to the high address and the low byte to the
low address.
Memory map of the IBM PC Memory Stack
For a program to be executed on the PC, DOS must first
load it into RAM. Where in RAM will it be loaded? The stack is a section of read/write memory (RAM) used
by the CPU to store information temporarily.
The 20-bit address of the 8088/86 allows a total of 1
megabyte (1024K bytes) of memory space with the The CPU needs this storage area since there are only a
address range 00000 - FFFFF. limited number of registers. There must be some place for
the CPU to store information safely and temporarily.
During the design phase of the first IBM PC, engineers had
to decide on the allocation of the 1-megabyte memory Now one might ask why not design a CPU with more
space to various sections. This memory allocation is called
registers? The reason is that in the design of the CPU,
a memory map.
every transistor is precious and not enough of them are
available to build hundreds of registers. In addition, how
Of this 1 megabyte, 640K
bytes from addresses 00000 many registers should a CPU have to satisfy every possible
to 9FFFFH were set aside for program and application?
RAM.
The main disadvantage of the stack is its access time.
The 128K bytes from A0000H Since the stack is in RAM, it takes much longer to access
to BFFFFH were allocated compared to the access time of registers. After all, the
for video memory. registers are inside the CPU and RAM is outside.
The remaining 256K bytes
Some very powerful (and consequently, expensive)
from C0000H to FFFFFH were
set aside for ROM. computers do not have a stack; the CPU has a large
number of registers to work with.
How stacks are accessed As data is popped off the stack into the CPU, the TOS
location is incremented.
There must be registers inside the CPU to point to the
stack section of RAM. The two main registers used to When an instruction pushes or pops a general-purpose
access the stack are the SS (stack segment) register and register, it must be the entire 16-bit register. In other
the SP (stack pointer) register. These registers must be words, one must code "PUSH AX"; there are no instructions
loaded before any instructions accessing the stack are such as "PUSH AL" or "PUSH AH".
used.
The reason that the SP is decremented after the push is to
Every register inside the 80x86 (except segment registers make sure, that the stack is growing downward from
and SP) can be stored in the stack and brought back into upper addresses to lower addresses.
the CPU from the stack memory.
This is the opposite of the IP (instruction pointer). As was
The storing of a CPU register in the stack is called a push seen in the preceding section, the IP points to the next
while loading the contents of the stack into the CPU instruction to be executed and is incremented as each
register is called a pop. In other words, a register is instruction is executed.
pushed onto the stack to store it and popped of the
stack to retrieve it. To ensure that the code section and stack section of the
program never write over each other, they are located
The stack pointer register (SP) points at the current at opposite ends of the RAM memory set aside for the
memory location used for the top of the stack (TOS). program, and they grow toward each other but must not
meet. If they meet, the program will crash.
As data is pushed onto the stack, the TOS location is
decremented. The following examples show how the stack grows.
Pushing onto the stack Solution

As each PUSH is executed, the contents of the register

are saved on the stack, and SP is decremented by 2.

For every byte of data saved on the stack, SP is

decremented once, and since push is saving the
contents of a 16-bit register, it is decremented twice.

Notice also how the data is stored on the stack. In the

80x86, the lower byte is always stored in the memory
location with the lower address. That is the reason that
B6H (the content of AL), in the following example, is
saved in memory location with address 1234.

Example 1-6
Popping the stack
Assuming that SP = 1236, AX = 24B6, DI = 85C2, and DX =
5F93, show the contents of the stack as each of the With every pop, the top 2 bytes of the stack are copied
following instructions is executed: to the register specified by the instruction and the stack
pointer is incremented twice.

Although the data actually remains in memory, it is not

accessible since the stack pointer is beyond that point.
Example 1-7 Logical & physical addresses for the stack
Assuming that the stack is as shown below, and SP =
18FA, show the contents of the stack and registers as Now one might ask, what is the exact physical location of
each of the following instructions is executed: the stack? That depends on the value of the stack
segment (SS) register and, the stack pointer (SP).

To compute physical addresses for the stack, the same

principle is applied as was used for the code and data
Solution segments. The method is to shift left SS and then add
offset SP, the stack pointer register.

Example 1-8

If SS = 3500H and the SP is FFFEH,

(a) Calculate the physical address of the stack.
(b) Calculate the lower range.
(c) Calculate the upper range of the stack segment
(d) Show the logical address of the stack.

Solution:
(a) 44FFE (35000 + FFFE) (b) 35000 (35000 + 0000)
(c) 44FFF (35000 + FFFF) (d) 3500:FFFE
More About Segments in The 80x86 Example 1-9

Can a single physical address belong to many different What is the range of physical addresses if CS = FF59?
logical addresses? Yes, look at the case of a physical
address value of 15020H. There are many possible logical Solution:
addresses that represent this single physical address:
The low range is FF590 (FF590 + 0000).

The range goes to FFFFF and wraps around, from 00000 to

0F58F (FF590 + FFFF = 0F58F), which is illustrated below.

This shows the dynamic behavior of the segment and

offset concept in the 8086 CPU.

One last point that must be clarified is the case when

adding the offset to the shifted segment register results in
an address beyond the maximum allowed range of
FFFFFH. In that situation, wrap-around will occur.
Overlapping Flag Register

In calculating the physical address, it is possible that two The flag register is a 16-bit register sometimes referred to
segments can overlap as shown below, which is desirable as the status register.
in some circumstances. For example, overlapping is used
in COM files. Only some of the bits are used. The rest are either
undefined or reserved by Intel.

Six of the flags are called conditional flags, meaning that

they indicate some condition that resulted after an
instruction was executed. These six are CF, PF, AF, ZF, SF,
and OF.

The three remaining flags are sometimes called control

flags since they are used to control the operation of
instructions before they are executed.
Bits of the flag register Flag register and ADD instruction

CF, the Carry Flag. This flag is set whenever there is a carry The flag bits affected by the ADD instruction are CF (carry
out, either from d7 after an 8-bit operation, or from d15 after flag), PF (parity flag), AF (auxiliary carry flag), ZF (zero
a 16-bit data operation. flag), SF (sign flag), and OF (overflow flag).
PF, the Parity Flag. After certain operations, the parity of the
Example 1-10
result's low-order byte is checked. If the byte has an even
number of 1s, the parity flag is set to 1; otherwise, it is cleared.
Show how the flag register is affected by the addition of
AF, Auxiliary Carry Flag. If there is a carry from d3 to d4 of an 38H and 2FH.
operation, this bit is set; otherwise, it is cleared (set equal to
zero). This flag is used by the instructions that perform BCD Solution:
(binary coded decimal) arithmetic.

ZF, the Zero Flag. The zero flag is set to 1 if the result of an
arithmetic or logical operation is zero; otherwise, it is cleared.

SF, the Sign Flag. Binary representation of signed numbers

uses the most significant bit as the sign bit. After arithmetic or
logic operations, the status of this sign bit is copied into the SF, CF = 0 since there is no carry beyond d7
thereby indicating the sign of the result. PF = 0 since there is an odd number of 1s in the result
AF = 1 since there is a carry from d3 to d4
OF, the Overflow Flag. This flag is set whenever the result of a
ZF = 0 since the result is not zero
signed number operation is too large. It will be discussed later
in detail.
SF = 0 since d7 of the result is zero
Example 1-11 Example 1-12
Show how the flag register is affected by
Show how the flag register is affected by

Solution:

Solution:
CF = 0 since there is no carry beyond d15
PF = 0 since there is an odd number of 1s in the lower byte
AF = 1 since there is a carry from d3 to d4
ZF = 0 since the result is not zero
CF=1 since there is a carry beyond d7 SF = 1 since d15 of the result is one
PF =1 since there is an even number of 1s in the result
AF=1 since there is a carry from d3 to d4 Example 1-13
ZF =1 since the result is zero
SF =0 since d7 of the result is zero Show how the flag register is affected by

It is important to notice the differences between 8-bit and

16-bit operations in terms of their impact on the flag bits. Solution:

The parity bit only counts the lower 8-bits of the result and
is set accordingly. Also notice the CF bit.
CF = 1 since there is a carry beyond d15
PF = 1 since there is an even number of 1s in the lower byte
The carry flag is set if there is a carry beyond bit d15 AF = 1 since there is a carry from d3 to d4
instead of bit d7. ZF = 1 since the result is zero
SF = 0 since d15 of the result is zero
Notice the zero flag (ZF) status after the execution of the Use of the zero flag for looping
ADD instruction.
Since the result of the entire 16-bit operation is zero One of the most widely used applications of the flag
(meaning the contents of BX), ZF is set to high. register is the use of the zero flag to implement program
Do all instructions affect the flag bits? The answer is no; loops. The term loop refers to a set of instructions that is
some instructions such as data transfers (MOV) affect no repeated a number of times.
flags.
For example, to add 5 bytes of data, a counter can be
Example 1-14 used to keep track of how many times the loop needs to
be repeated. Each time the addition is performed the
Show how the flag register is affected by counter is decremented and the zero flag is checked.

The following shows the implementation of the looping

concept in the program, which adds 5 bytes of data.

Solution: JNZ stands for "Jump Not Zero" meaning that if ZF = 0,

jump to a new address. If ZF = 1, the jump is not
performed and the instruction below the jump will be
executed.
After the ADD operation, the following are the flag bits:
CF = 0 since there is no carry beyond d15
PF = 1 since there is an even number of 1s in the lower
byte
AF = 1 since there is a carry from d3 to d4
ZF = 0 since the result is not zero
SF = 1 since d15 of the result is 1
80x86 Addressing Modes Examples:

The CPU can access operands (data) in various ways,

called addressing modes. The 80x86 provides a total of
seven distinct addressing modes: To move information to the segment registers, the data
must first be moved to a general-purpose register and
1. Register addressing mode then to the segment register. Example:

The register addressing mode involves the use of registers

to hold the data to be manipulated. Memory is not
accessed when this addressing mode is executed; In other words, the following would produce an error:
therefore, it is relatively fast. Examples follow:

3. Direct addressing mode

2. Immediate addressing mode In the direct addressing mode, the data is in some
memory location(s) and the address of the data in
In the immediate addressing mode, the source operand memory comes immediately after the instruction. This
is a constant. For this reason, this addressing mode address is the offset address, and one can calculate the
executes quickly. However, in programming it has limited physical address by shifting left the DS register and
use. Immediate addressing mode can be used to load adding it to the offset as follows:
information into any of the registers except the segment
registers and flag registers.
In this case the physical address is calculated by 4. Register indirect addressing mode
combining the contents of offset location 2400 with DS,
the data segment register. In the register indirect addressing mode, the address of
the memory location where the operand resides is held
In the absence of the bracket around the address, it will by a register. The registers used for this purpose are SI, DI,
give an error since it is interpreted to move the value 2400 and BX. If these three registers are used as pointers, that
(l6-bit data) into register DL, an 8-bit register. is, if they hold the offset of the memory location, they
must be combined with DS in order to generate the 20-bit
Example 1-15 physical address. For example:

Find the physical address of the memory location and its

contents after the execution of the following, assuming
that DS = 1512H. In the absence of brackets, it is interpreted as an
instruction moving the contents of register BX to AL (which
gives an error because source and destination do not
match) instead of the contents of the memory location
Solution: whose offset address is in BX.

First AL is initialized to 99H, then in line two, the contents of The physical address is calculated by shifting DS left one
AL are moved to logical address DS:3518 which is hex position and adding BX to it. The same rules apply
1512:3518. Shifting DS left and adding it to the offset gives when using register SI or DI.
the physical address of 18638H (15120H + 3518H =
18638H). That means after the execution of the second
instruction, the memory location with address 18638H will
contain the value 99H.
Example 1-16 6. Indexed relative addressing mode

Assume that DS = 1120, SI = 2498, and AX = 17FE. Show the The indexed relative addressing mode works the same as
contents of memory locations after the execution of the based relative addressing mode, except that registers
DI and SI hold the offset address. Examples:
Solution:

The contents of AX are moved into memory locations

with logical address DS:SI and DS:SI+1; therefore, the Example 1-17
physical address starts at DS (shifted left) + SI = 13698.
According to the little endian convention, low address Assume that DS = 4500, SS = 2000, BX = 2100, SI = 1486, DI =
13698H contains FE, the low byte, and high address 8500, BP = 7814, and AX = 2512. Show the exact physical
13699H will contain 17, the high byte. memory location where AX is stored in each of the
5. Based relative addressing mode following. All values are in hex.

In the based relative addressing mode, base registers BX

and BP, as well as a displacement value, are used to
calculate the effective address. The default segments Solution:
are DS for BX and SS for BP. For example:
In each case PA = segment register (shifted left) + offset
register + displacement.
(a) DS:BX+20 location 47120 = (12) and 47121 = (25)
(b) DS:SI+10 location 46496 = (12) and 46497 = (25)
Alternative ways of coding are "MOV CX,[BX+10]" or (c) DS:DI+4 location 4D504 = (12) and 4D505 = (25)
"MOV CX,10[BX]" and "MOV AL,[BP+5]" or "MOV AL,5[BP]". (d) SS:BP+12 location 27826 = (12) and 27827 = (25)
7. Based indexed addressing mode ☼ In many of the previous examples, the MOV
instruction was used for the sake of clarity, even
By combining based and indexed addressing modes, a though one can use any instruction as long as that
new addressing mode is derived called the based instruction supports the addressing mode.
indexed addressing mode. In this mode, one base
register and one index register are used. Examples: For example, the instruction "ADD DL,[BX]" would
add the contents of the memory location pointed
at by DS:BX to the contents of register DL.

Segment Overrides
The coding of the instructions above can vary; for
example, the last example could have been written The table below provides a summary of the offset
registers that can be used with the four segment registers
of the 80x86.
or

Note that "MOV AX,[SI][DI]+displacement" is illegal. The 80x86 CPU allows the program to override the default
segment and use any segment register. To do that,
specify the segment in the code.
For example, in "MOV AL,[BX]", the physical address of the The last table below summarizes all addressing modes.
operand to be moved into AL is DS:BX, as was shown
earlier since DS is the default segment for pointer BX.

To override that default, specify the desired segment in

the instruction as "MOV AL,ES:[BX]". Now the address of
the operand being moved to AL is ES:BX instead of DS:BX.

The following table shows more examples of segment

overrides shown next to the default address in the
absence of the override.

disp → Displacement value

Lecture 2
Assembly Language Programming

41
Directives and A Sample Program Directives give directions to the assembler about how it
should translate the Assembly language instructions into
machine code.
The given Assembly language program below is a series
of statements, or lines, which are either Assembly An Assembly language instruction consists of four fields:
language instructions such as ADD and MOV, or
statements called directives or pseudo-instructions.

Brackets indicate that the field is optional. Do not type in

the brackets!

The label field allows the program to refer to a line of

code by name.

The Assembly language mnemonic (instruction) and

operand(s) fields together perform the real work of the
program and accomplish the tasks for which the program
was written. In Assembly language statements such as

Directives do not generate any machine code and are

used only by the assembler as opposed to instructions,
which are translated into machine code for the CPU to
execute. Commands, DB, END, and ENDP, are examples
of directives.
The assembler ignores comments. The comment field Segments of A Program
begins with a ";“ and they are optional but are highly
recommended to make it easier for someone to read Assembly language statements are grouped into
and understand the program. segments. Normally, The simplified segment definition
format uses at least three simple directives: ".CODE",
".DATA", and ".STACK", which correspond to the CS, DS,
Model Definition and SS registers, respectively.

The first statement in the code after the comments is the

MODEL directive. This directive selects the size of the > Stack Segments
memory model.
The following directive reserves 64 bytes of memory for
the stack:

SMALL is one of the most widely used memory models for

Assembly language programs and is sufficient for most
programs. The small model uses a maximum of 64K bytes > Data Segment
of memory for code and another 64K bytes for data. The
other models are defined as follows: The data segment in the program defines three data
items: DATA1, DATA2, and SUM. They will be accessed in
the code segment by their labels.

DATA I and DATA2 are given initial values in the data

section. SUM is not given an initial value, but storage is set
aside for it. Each is defined as DB (define byte).

Memory can be allocated in other sizes than in byte-sized

Notice that MEDIUM and COMPACT are opposites. chunks, such as the DW (define word) directive.
> Code Segment The purpose of the two last instructions in the shell is to
return control to the operating system.
The first line of the segment after the .CODE directive is
the PROC directive. A procedure is a group of instructions The last two lines end the procedure and the entire
designed to accomplish a specific function. It helps make program, respectively.
the program more structured. Mostly a code segment
consist of only one procedure. Every procedure must The following is a sample shell of an Assembly language
have a name stated in the label field and must be closed program. You simply fill it in with the instructions and data
by the ENDP directive, which must have the same label. for your program.
The PROC and ENDP statements must have the same
label.

The PROC directive may have the option FAR or NEAR. It

is required that FAR must be used at the program entry
point (first procedure).

It is the job of the operating system to assign exact values

for only the CS and SS segment registers. The DS value
(and ES, if used) must be initialized by the program. This is
done as follows:

We cannot code "MOV DS,@DATA" in one line, because

we know no segment register can be loaded directly.
Assemble, Link, and Run A Program list of all symbols and labels used in the program as well
as the program line numbers in which they are
referenced.
Now that the basic form of an Assembly language
program has been given, the next question is: How is it
Before feeding the ".obj" file into the linker program, all
created and assembled?
syntax errors produced by the assembler must be
corrected, so that LINK can create the executable
program.

The LINK program,

thereby, produces the
executable program
that ends in ".exe“,
The MASM and LINK programs are the assembler and
which can be
linker programs for Microsoft's MASM assembler.
executed by the
The editor is used in creating and editing the program microprocessor.
and it must be able to produce a source file that ends in
".asm". This ".asm“ source file is assembled by an The .map file, which is
assembler, such as Microsoft’s MASM. optional, shows the
name of each segment
The assembler will convert the .asm file into a machine and its size in bytes. This
language in an object (.obj) file, plus lists of all the is especially helpful
opcodes and offset addresses in a list file (.lst), along with when there are many
cross-reference file (.crf), which provides an alphabetical segments for code or
data.
More Sample Programs In the method used below, a name is assigned to each
data item that will be accessed in the program.
Program-1
Variations of the program are shown below to clarify the
Write a program that adds 5 bytes of following hex use of addressing modes in the context of a real program
numbers (25, 12, 15, IF, and 2B) and saves the result. and also to show that the 80x86 can use any general-
purpose register to do arithmetic and logic operations.

From the data segment:

From the code segment:

There is quite a difference between these two methods

of writing the Same program. While in the first one the
There are many ways in which any program may be register indirect addressing mode was used to access the
written. The method shown above defined one field of data, in the second method the direct addressing mode
data and used pointer [BX] to access data elements. was used.
Program-2 For example, "234D" as defined in the data segment is stored
in a way that the lower address, 0000, has the least significant
Write a program that adds four words of data and saves byte, 4D, and the higher address, 0001, has the most
the result. The values will be 234DH, 1DE6H, 3BC7H, and significant byte, 23.
566AH. Use DEBUG to verify the sum is 0364.
Second, note that the address pointer is incremented twice,
since the operand being accessed is a word (two bytes). The
program could have used "ADD DI,2" instead of using "INC DI"
twice.

When storing the result of word addition, "MOV SI,OFFSET SUM"

was used to load the pointer (in this case 0010, as defined by
ORG 0010H) for the memory allocated for the label SUM, and
then "MOV [SI],BX" was used to move the contents of register
BX to memory locations with offsets 0010 and 0011.

Again, as was done previously, it could have been coded

simply as "MOV SUM,BX", using the direct addressing mode.

Program-2 uses the ORG directive. In previous programs

where ORG was not used, the assembler would start at offset
0000 and use memory for each data item.

The ORG directive can be used to set the offset addresses for
data items. Although the programmer cannot assign exact
First, notice that the 16-bit data (a word) is stored with the physical addresses, one is allowed to assign offset addresses.
low-order byte first.
Program-3 Notice that C4 was coded in the data
segments as 0C4. This is required by the
Write and run a program that transfers 6 bytes of data from assembler to indicate that C is a hex number
memory locations with offset of 0010H to memory locations with and not a letter. This is required if the first digit is
offset of 0028H. a hex digit A through F.

This program uses two registers, SI and DI, as

pointers to the data items being manipulated.

The first is used as a pointer to the data item to

be copied and the second as a pointer to the
location the data item is to be copied to.

With each iteration of the loop, both data

pointers are incremented to point to the next
byte.
Control Transfer Instructions Conditional Jumps

In the sequence of instructions to be executed, it is often In the conditional jump, control is transferred to a new
necessary to transfer program control to a different location if a certain condition is met.
location. There are many instructions in the 80x86 to
achieve this. The flag register is the one that indicates the current
condition.
FAR and NEAR

The CS:IP registers always point to the address of the next

instruction to be executed. In a NEAR jump, the IP is
updated, and CS remains the same, since control is still
inside the current code segment. In a FAR jump, because
control is passing outside the current code segment, both
CS and IP have to be updated to the new values. In
other words, in any control transfer instruction such as
jump or call, the IP must be changed, but only in the FAR
case is the CS changed, too.

The operating system assigns values for the segment

registers. It must do this because it knows how much
memory is installed in the computer, how much of it is
used by the system, and how much is available.

The OS first finds out how many kilobytes of RAM memory

are installed, allocates some for its own use, and then
allows the user program to use the portions that it needs.
For example, with "JNZ label", the processor looks at the
zero flag to see if it is raised. If not, the CPU starts to fetch
and execute instructions from the address of the label. If
ZF = 1, it will not jump but will execute the next instruction
below the JNZ.

Short jumps

All conditional jumps are short jumps. In a short jump, the

address of the target must be within -128 to +127 bytes of
the IP. In other words, the conditional jump is a two-byte
instruction: one byte is the opcode of the J condition,
and the second byte is a value between 00 and FF. An
offset range of 00 to FF gives 256 possible addresses;
these are split between backward jumps (to -128) and
forward jumps (to +127).
Assembled Code:
In a jump backward, the second byte is the 2's
complement of the displacement value. To calculate the
target address, the second byte is added to the IP of the
instruction after the jump.

To understand this, look at the unassembled and

assembled code versions of Program-1 for the instruction
JNZ AGAIN.
Similarly, the target address for a forward jump is The unconditional jump can take the following forms:
calculated by adding the IP of the following instruction to
the operand. In this case, the displacement value is 1. Short Jump, which is specified by the format
positive, as shown next. "JMP SHORT label". This is a jump in which the address
of the target location is within -128 to +127 bytes of
memory relative to the address of the current IP.

In this case, the opcode is EB and the operand is 1

byte in the range 00 to FF. The operand byte is added
to the current IP to calculate the target address.

If the jump is backward, the operand is in 2's

In the program, "JB NEXT" has the opcode 72 and the complement. Coding the directive "short" makes the
target address 06 and is located at IP = 000A and 000B. jump more efficient in that it will be assembled into a
The jump will be 6 bytes from the next instruction, which is 2-byte instruction instead of a 3-byte instruction.
IP = 000C. Adding gives us 000CH + 0006H = 0012H, which
is the exact address of the NEXT label. 2. Near jump, which is the default, has the format
"JMP label". This is a near jump (within the current
Look also at "JA NEXT", which has 77 and 02 for the code segment) and has the opcode E9. The target
opcode and displacement, respectively. The IP of the address can be any of the addressing modes of
following instruction, 0010, is added to 02 to get 0012, the direct, register, register indirect, or memory indirect:
address of the target location.
a) Direct JUMP is exactly like the short jump explained
Unconditional jumps earlier, except that the target address can be
anywhere in the segment within the range +32767
"JMP label" is an unconditional jump in which control is to -32768 of the current IP.
transferred unconditionally to the target location label.
 b) Register indirect JUMP; the target address is in a To make sure that, after execution of the called
register. For example, in "JMP BX", IP takes the subroutine, the microprocessor knows where to come
value BX. back, the microprocessor automatically saves the
address of the instruction following the call on the stack.
c) Memory indirect JMP; the target address is the In the NEAR call only, the IP is saved on the stack, and in
contents of two memory locations pointed at by a FAR call both CS and IP are saved.
the register. Example: "JMP [DI]" will replace the IP
with the contents of memory locations pointed at When a subroutine is called, control is transferred to that
by DI and DI+1. subroutine and the processor saves the IP (and CS in the
case of a FAR call) and begins to fetch instructions from
3. Far jump, which has the format "JMP FAR PTR label". the new location.
This is a jump out of the current code segment,
meaning that not only the IP but also the CS is After finishing execution of the subroutine, for control to
replaced with new values. be transferred back to the caller, the last instruction in the
called subroutine must be RET (return).
CALL statements
For NEAR calls, the IP is restored; for FAR calls, both CS
Another control transfer instruction is the CALL instruction, and IP are restored. This will ensure that control is given
which is used to call a procedure. back to the caller.

CALLs to procedures are used to perform tasks that need As an example, assume that SP = FFFEH and the following
to be performed frequently. This makes a program more code is a portion of the unassembled program:
structured. The target address could be in the current
segment.
Since the CALL instruction is a NEAR call, meaning that it is The main program is the entry point from DOS and is FAR,
in the same code segment (same CS, different IP), only IP as explained earlier, but the subroutines called within the
is saved on the stack. main program can be FAR or NEAR. If there is no specific
In this case, the IP address of mention of FAR after the directive PROC, it defaults to
the instruction after the call is NEAR, as shown below.
saved on the stack as
indicated.

That IP will be 0206, which

belongs to the "MOV AX,142F"
instruction.

The last instruction of the called subroutine must be a RET

instruction, which directs the CPU to POP the top 2 bytes
of the stack into the IP and resume executing at offset
address 0206.

Subroutines

In Assembly language programming it is common to

have one main program and many subroutines to be
called from the main program.
Rules for Names in Assembly Language The programmer should break down data larger than 16
bits (0000 to FFFFH or 0 to 65535 in decimal) to be
By choosing label names that are meaningful, a processed by the CPU.
programmer can make a program much easier to read
and maintain. There are rules that names must follow: If a number is less than 8 bits wide, it still must be coded
⌐ Each label name must be unique. as an 8-bit register with the higher digits as zero. Similarly,
⌐ The names used for labels may consist of alphabetic if the number is less than 16 bits wide it must use all 16 bits,
letters in both upper and lower case, the digits 0-9, with the rest being 0s.
and the special characters (?), (.), (@), and ($).
⌐ The first character of the name must be an For example, the number 5 is only 3 bits wide (10 I) in
alphabetic character or special character. binary, but the 8088/86 will accept it as 05H or "0000 0101"
⌐ It cannot be a digit. in binary. The decimal number 514 is “10 0000 0010" in
⌐ Names may be up to 31 characters long. binary, but the 8088/86 will accept it as 202H or "0000
⌐ There is a certain list of reserved words (e.g., 0010 0000 0010" in binary.
Instructions, register names, assembler operators and
directives), that cannot be used as user-defined
labels or variable names. Assembler data directives

All the assemblers designed for the 80x86 (8088, 8086,

80188, 80186, 80286, 80386, 80386SX, 80486, and Pentium)
80x86 Data Types microprocessors have standardized the directives for
data representation.
The 8088/86 microprocessor supports many data types
(8-bit or 16-bit), but none are longer than 16 bits wide
The following are some of the data directives used by the
since the size of the registers is 16 bits.
80x86 microprocessor.
ORG (origin) DW (define word)

ORG is used to indicate the beginning of the offset DW is used to allocate memory 2 bytes (one word) at a
address. The number that comes after ORG can be either time. The following are some examples of DW:
in hex or in decimal. If the number is not followed by H, it
is decimal and the assembler will convert it to hex.

DB (define byte)

DB can be used to define numbers in decimal, binary,

hex, and ASCII. Regardless of which one is used, the
assembler will convert them into hex. DD (define doubleword)

For decimal, the D after the number is optional, but using The DD directive is used to allocate memory locations
B (binary) and H (hexadecimal) for the others is required. that are 4 bytes (two words) in size. Again, the data can
To indicate ASCII, simply place the string in single or be in decimal, binary, or hex. In any case the data is
double quotations ("like this"). DB is the only directive that converted to hex and placed in memory locations
should be used for all ASCII data definitions. For example: according to the rule of low byte to low address and high
byte to high address. DD examples are:
DQ (define quadword) EQU (equate)
DQ is used to allocate memory 8 bytes (four words) in
This is used to define a constant without occupying a
size. This can be used to represent any variable up to 64 memory location. EQU does not set aside storage for a data
bits wide: item but associates a constant value with a data label so
that when the label appears in the program, its constant
value will be substituted for the label.

Using EQU for the counter constant in the immediate

addressing mode:

DUP (duplicate) When executing the instructions "MOV CX,COUNT", the

register CX will be loaded with the value 25. This is in contrast
to using DB:
DUP is used to duplicate a given number of characters.
This can avoid a lot of typing. For example, contrast the
following two methods of filling six memory locations with
FFH: When executing the same instruction "MOV CX,COUNT", it will
be in the direct addressing mode.

Assume that there is a constant (a fixed value) used in many

different places in the data and code segments. By the use
of EQU, one can change it once and the assembler will
change all of them, rather than correcting every location.