Comprehensive Interview Question Bank

(FPGA | Verilog | Digital Design | FIFO | CDC)

Section A – FPGA Basics

1. What is an FPGA? How does it differ from a microcontroller?
2. Compare FPGA, CPLD, and ASIC.
3. What are LUTs (Look-Up Tables)? Why are they important in FPGA design?
4. What is a flip-flop? How is it different from a latch?
5. Why do FPGAs have both combinational and sequential resources?
6. What is the function of Block RAM in an FPGA?
7. Name some common FPGA vendors and families (Xilinx, Intel/Altera, Lattice,
Microchip).

Section B – Design Flow & Tools

8. What is RTL? Why is it used in FPGA design?
9. Explain the FPGA design flow: HDL coding → synthesis → implementation →
bitstream → download.
10. What are common FPGA design tools (Vivado, Quartus, ISE, ModelSim, Icarus
Verilog)?
11. What is a constraint file (XDC/SDC)? Why is it required?
12. What is bitstream generation?
13. Explain functional vs. timing simulation.
14. What is timing closure, and why is it difficult?

Section C – Verilog/VHDL Coding (Freshers Level)

1. Verilog Fundamentals
15. What is Verilog? How is it different from VHDL?
16. Explain behavioral, dataflow, and structural modeling with examples.
17. What are wire, reg, and integer data types?
18. What is the difference between net types and register types?
19. Explain initial vs. always blocks.
20. What is the difference between blocking (=) and non-blocking (<=) assignments?
21. What is the difference between module instantiation and hierarchical references?
 22. What are compiler directives in Verilog (timescale, define, include)?

2. Data Types, Operators & Parameters

23. Difference between parameter and localparam.
24. What are defparam statements? Why should we avoid them?
25. Explain bitwise, logical, arithmetic, relational, and reduction operators.
26. What is the difference between concatenation and replication?
27. How do you declare multidimensional arrays? Are they synthesizable?
28. What is the difference between signed and unsigned operations in Verilog?
29. Explain $clog2 and $bits system functions.

3. Procedural Statements
30. What are the different procedural blocks (always, initial, task, function)?
31. What is the difference between tasks and functions in Verilog?
32. Difference between case, casex, and casez. Which is synthesizable?
33. What happens if you miss an else in an if-else block?
34. What happens if you miss a default in a case statement?

4. Combinational & Sequential Circuits

35. Write Verilog code for a 2:1 multiplexer.
36. Write Verilog code for a 4:1 multiplexer.
37. Write Verilog code for a 3:8 decoder.
38. Write Verilog code for an 8:3 priority encoder.
39. Write Verilog code for a parity generator.
40. Write RTL for a D Flip-Flop with reset and enable.
41. Write RTL for a T Flip-Flop.
42. Write RTL for a 4-bit counter with synchronous reset.
43. Write RTL for a 4-bit counter with asynchronous reset.
44. Write RTL for a shift register.
45. Explain FSM design (Moore vs Mealy) with examples.
46. What happens if you use blocking assignment inside sequential always blocks?
47. How do you implement a parameterized FSM?
5. Synthesis vs. Simulation
48. Which Verilog constructs are non-synthesizable? (e.g., delays, force/release,
fork/join).
49. What is the role of a synthesis tool?
50. Why can simulation work but FPGA hardware fail?
51. What is a race condition in Verilog simulation? How to avoid it?
52. Difference between RTL simulation, gate-level simulation, and timing simulation.
53. What are intra-assignment vs. inter-assignment delays?

6. Memory & FIFOs

54. How do you infer ROM in Verilog?
55. How do you infer single-port RAM in Verilog?
56. How do you infer dual-port RAM in Verilog?
57. What is the difference between blocking writes and non-blocking reads in memories?
58. Explain the FIFO structure (wr_ptr, rd_ptr, full, empty).
59. How do you design a synchronous FIFO?
60. How do you design an asynchronous FIFO? Why use Gray code pointers?
61. How do you test FIFO overflow/underflow conditions?

7. Clocking & Timing

62. What is a sensitivity list?
63. What is the difference between @(posedge clk) and @(negedge clk)?
64. Explain setup time, hold time, and clock-to-Q delay.
65. What is metastability?
66. How do you synchronize signals across clock domains (CDC)?
67. What is the difference between 2-flop synchronizer, pulse synchronizer, and FIFO
synchronizer?
68. Why are gated clocks discouraged in FPGA design?

8. Testbenches & Verification

69. What is a testbench? Why is it non-synthesizable?
70. Explain directed testing vs random testing.
71. What is a self-checking testbench?
72. Difference between $display, $monitor, $strobe.
73. How do you create a clock generator in Verilog?
 74. How do you apply reset stimulus in a testbench?
75. Write a testbench for a 4-bit counter.
76. What is functional coverage vs code coverage?

9. System Tasks & Debugging

77. Explain $finish, $stop, $time, $random, $fopen, $fdisplay.
78. What is the difference between $dumpfile and $dumpvars?
79. How do you dump waveforms for GTKWave/ModelSim?
80. What is an X-propagation issue in simulation?
81. How do you debug mismatches between DUT and testbench?
82. If FPGA hardware fails but simulation passes, what do you check first?

10. Advanced & Tricky Questions

83. Explain generate statements. How are they used for parameterization?
84. What is the difference between blocking vs non-blocking assignments in FSMs?
85. How do you avoid latch inference in Verilog?
86. Why should sensitivity lists use @(*) in Verilog-2001?
87. What is the difference between initial block and reset logic?
88. Why is reset synchronization required in FPGA?
89. What is the difference between RTL coding style for ASIC vs FPGA?
90. What are false paths and multi-cycle paths? How do you constrain them?

11. Project/Scenario-Based
91. Explain the largest Verilog project you worked on. What was your role?
92. How did you implement and test a UART in Verilog?
93. How did you implement and test an I²C module in Verilog?
94. How did you implement and test an SPI module in Verilog?
95. How did you design and test a sequence detector in Verilog?
96. How would you implement an image processing filter (e.g., Sobel edge detection) in
Verilog?
97. How do you optimize Verilog code for timing closure?
98. If your design is too large for FPGA LUTs/BRAM, what would you do?
Section D – Digital Design Concepts
99. What is synchronous reset vs asynchronous reset? Which is preferred in FPGA and
why?
100. Explain setup time and hold time.
101. What is metastability? How do you avoid it?
102. Why are synchronizers required in FPGA design?
103. Difference between combinational and sequential circuits.
104. Explain clock gating. Why is clock enable preferred in FPGA?
105. How do you implement a state machine (Moore vs. Mealy) in FPGA?

Section E – FPGA Resources & Practical Usage

106. What are DSP slices in FPGA? Where are they used?
107. Difference between Distributed RAM and Block RAM.
108. How would you implement multiplication in FPGA (DSP slices vs LUTs)?
109. Explain clock management resources (PLL, MMCM).
110. What is I/O standard selection (LVDS, LVCMOS, SSTL)?
111. How do you interface an FPGA with external devices like DDR?
112. How do you interface an FPGA with UART, SPI, or I²C?

Section F – FPGA Debug & Verification

113. What is functional simulation? Which tools are used?
114. What is an ILA (Integrated Logic Analyzer) / SignalTap?
115. How do you check whether your FPGA design works correctly after synthesis?
116. What is hardware co-simulation or hardware-in-the-loop testing?
117. How do you write a self-checking testbench in Verilog?
118. Explain code coverage and functional coverage.

Section G – Mini Projects (Freshers Level)

119. Implement a traffic light controller in Verilog and explain how you’d test it on
FPGA.
120. Design a UART TX/RX module and explain its FSM.
121. Implement a PWM generator using FPGA.
122. How do you create an LED blinking project with a divided clock?
 123. Implement a sequence detector (e.g., detect 1011).
124. Explain how you would connect FPGA to a 7-segment display.
125. Implement an FIR filter using FPGA DSP slices.

Section H – General & Career-Oriented

126. Why do companies use FPGAs instead of ASICs?
127. What are typical FPGA applications in industry (networking, automotive, AI,
prototyping)?
128. What challenges did you face in your FPGA project and how did you solve them?
129. How would you debug if your FPGA project works in simulation but fails on
hardware?
130. What excites you most about FPGA-based design?
131. Where do you see yourself in 3 years (FPGA, ASIC, verification, embedded)?

FIFO (First-In, First-Out) Questions

Basics
132. What is a FIFO? Where is it used in FPGA designs?
133. Explain the difference between synchronous FIFO and asynchronous FIFO.
134. What are the key signals in a FIFO design (wr_en, rd_en, full, empty, wr_ptr,
rd_ptr)?
135. What happens if you try to read from an empty FIFO?
136. What happens if you try to write to a full FIFO?
137. Why do we need FIFOs in communication protocols?

Intermediate
138. Write Verilog code for a simple synchronous FIFO with depth = 8 and width = 8.
139. How do you detect FIFO full and empty conditions?
140. What is the significance of the Gray code pointer technique in asynchronous FIFOs?
141. How do you handle overflow and underflow conditions in a FIFO?
142. What is the difference between circular buffer implementation and memory-based
FIFO?
143. Explain the concept of “almost full” and “almost empty” signals. Why are they
useful?
Advanced
144. How do you design a parameterized FIFO in Verilog (with configurable width and
depth)?
145. Explain how dual-port RAM is used inside a FIFO.
146. How would you verify a FIFO design in simulation? Write a self-checking testbench
strategy.
147. How do synthesis tools map FIFO logic (BRAM-based vs distributed LUT-based
FIFO)?
148. How do you ensure timing closure for a FIFO running between two different clock
domains?

CDC (Clock Domain Crossing) Questions

Basics
149. What is Clock Domain Crossing (CDC)? Why is it a problem in FPGA design?
150. What is metastability? How does it occur?
151. How do you reduce the probability of metastability in FPGA design?
152. What is a 2-flop synchronizer? Why do we use it?
153. Give examples of situations where CDC occurs in FPGA projects.

Intermediate
154. How do you synchronize a multi-bit bus across clock domains?
155. What are the challenges in synchronizing control signals vs. data signals?
156. Explain the difference between handshake-based CDC and FIFO-based CDC.
157. Why are Gray codes used in asynchronous FIFO CDC logic?
158. How do you handle CDC in high-speed designs (e.g., DDR, PCIe, Ethernet)?

Advanced
159. Draw and explain the architecture of an asynchronous FIFO used for CDC.
160. How do you verify CDC correctness? (simulation vs. formal checks vs. STA
constraints).
161. What are false paths in CDC, and how do you constrain them in XDC/SDC files?
162. Explain the difference between pulse synchronizers, toggle synchronizers, and
handshake synchronizers.
163. How do CDC issues appear in real hardware but not in simulation?
Project-Oriented
164. In your project, how did you implement a FIFO? What were the challenges?
165. Did you use synchronous FIFO or asynchronous FIFO in your project? Why?
166. How did you verify your FIFO design? (functional tests, corner cases, coverage).
167. Have you worked on a CDC verification tool (like Questa CDC)?
168. How would you explain CDC and FIFO design to a non-FPGA engineer?