CS353

Computer Architecture

Processor Datapath

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Instruction Datapath

4
 Instructions will be held
in the instruction
Add
memory
 The instruction to fetch
PC Read address is at the location
Instruction
Instruction
specified by the PC
Memory  Instr. = M[PC]
• After we fetch one
instruction, the PC must be
Note: Regular instruction width incremented to the next
(32 for MIPS) makes this easy instruction
• All instructions are 4 bytes
• PC = PC + 4
2
R-type Instruction Datapath
Read reg. num AA
reg num
Read reg data A
Instruction Read reg num B
Zero
Registers Result
Write reg num
Read reg data B ALU
Write reg data

 R-type Instructions have three registers

 Two read (Rs, Rt) to provide data to the ALU
 One write (Rd) to receive data from the ALU

• We’ll need to specify the operation to the ALU (later...)

• We might be interested if the result of the ALU is zero (later...)

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Memory Operations
Read reg. num AA
reg num Read address
Read reg data A
Instruction Read reg num B Data Memory
Zero Read data
Registers
Result Write address
Write reg num
Read reg data B
Write data
Write reg data

16 sign 32
extend

 Memory operations first need to compute the effective

address
 LW $t1, 450($s3) # E.A. = 450 + $s3
 Add together one register and 16 bits of immediate data
 Immediate data needs to be converted from 16-bit to 32-bit
 Memory then performs load or store using destination
register
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  Branches conditionally
Branches change the next
PC + 4 instruction
Result  BEQ $2, $1, 42
Sh. Add
Instruction Left
2
 The offset is specified as
the number of words to be
To control
Read reg. num AA
reg num
Read reg data A logic added to the next
Read reg num B
Registers
Zero instruction (PC+4)
Result
Write reg num
Read reg data B • Take offset, multiply by 4
– Shift left two
Write reg data

offset 16 sign 32
• Add this to PC+4 (from
extend
PC logic)
• Control logic has to
decide if the branch is
taken
– Uses ‘zero’ output of
ALU 9
 Integrating the R-types and Memory

Read reg. num AA

reg num Read address
Read reg data A
Instruction Read reg num B Data Memory
Zero Read data 1
Registers
Result Write address
Write reg num 0
Read reg data B 0
Write data
Write reg data
Memory 1

Datapath
16 sign 32
extend

 R-types and Load/Stores are similar in many respects

 Differences:
 2nd ALU source: R-types use register, I-types use Immediate
 Write Data: R-types use ALU result, I-types use memory
 Multiplex the conflicting datapaths together

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 Adding the instruction memory
4 Simply add the instruction memory
Result and PC to the beginning of the datapath.
Add

Read reg. num AA

reg num Read address
Read reg data A
Read address Read reg num B Data Memory
PC Zero Read data
Registers 1
Instruction [31-0] Result Write address
Write reg num
Instruction Read reg data B 0 0
Write data
Memory Write reg data 1

16 sign 32
extend

Separate Instruction and Data memories are needed in order to allow

the entire datapath to complete its job in a single clock cycle.

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 Adding the Branch Datapath
0
4
Result 1
Result
Sh. Add
Add Left
2

Read reg. num AA

reg num Read address
Read reg data A
Read address Read reg num B Data Memory
PC Zero Read data
Registers 1
Instruction [31-0] Result Write address
Write reg num
Instruction Read reg data B 0 0
Write data
Memory Write reg data 1

16 sign 32
extend

Now we have the datapath for R-type, I-type, and branch instructions.
On to the control logic!

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 When does everything
happen? 0

4 Result 1
Result clk Sh. Add
Left
Add 2 Single-Cycle Design
Read reg. num AA
reg num Read address
Read reg data A
Read address
Read reg num B Data Memory
PC Zero Read data
Registers 1
Instruction [31-0] Result Write address
Write reg num
Instruction Read reg data B 0 0
Write data
Memory Write reg data 1
clk
16 sign
extend
32
clk
Combinational Logic:
Just does it! Outputs are
always just a function of its Registers: Written at the end of the clock cycle.
inputs (with some delay) (Rising edge triggered).

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 What do we need to control? Mux - are we
branching or not?

Registers- 0

4 Should we
Result 1
write data? Mux - Result from
Result Sh. Add
Add
Left ALU or Memory?
2

Read reg. num AA

reg num Read address
Read reg data A
Read address
Read reg num B Data Memory
PC Zero Read data
Registers 1
Instruction [31-0] Result Write address
Write reg num
Instruction Read reg data B 0 0
Write data
Memory Write reg data 1

16 sign 32
Mux - Where
extend Memory-
does 2nd ALU ALU - Read/Write/neither?
operand come What is the
from? Operation?

Almost all of the information we need is in the instruction!

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