Counter and Time Delays

• A loop counter is set up by loading a

register with a certain value.
• Then using the DCR (to decrement)
and INR (to increment) the contents
of the register are updated.
• A loop is set up with a conditional
jump instruction that loops back or
not depending on whether the count
has reached the termination count.
• The operation of a loop counter can
be described using the following
flowchart.

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 Counter and Time Delays

• Using DCR instruction

MVI C, 15H

LOOP DCR C

JNZ LOOP

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 TIME DELAY
Why Time delays?
In the real time applications, such as traffic light control, digital clock,
process control, serial communication, it is important to keep a track with time.
For example in traffic light control application, it is necessary to give time
delays between two transitions. These time delays are in few seconds and can
be generated with the help of executing group of instructions number of times.
These software timers are also called time delays or software delays.
As you know microprocessor system consists of two basic components,
Hardware and software. The software component controls and operates the
hardware to get the desired output with the help of instructions. To execute
these instructions, microprocessor takes fix time as per the instruction, since it
is driven by constant frequency clock. This makes it possible to introduce delay
for specific time between two events.

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 TIME DELAY

• The procedure used to design a specific delay is similar to that used to set up
a counter.
• A register is loaded with a number, depending on the time delay required,
and then the register is decremented until it reaches zero by setting up a loop
with conditional jump instruction. The loop causes a delay, depending upon
the clock period of the system.
We can design time delay using following three techniques:
 Time delay using one register
 Time delay using register pair
 Time delay using a loop within a loop

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 Time delay using one register

• A count is loaded in a register and the loop is executed until the count
reaches to zero. The flowchart has been shown below:

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 Time delay Formulas

Total delay TD = Time to execute instructions outside loop (TO) + Time to

execute loop instructions (TL)
Time required to execute an instruction= number of T-states* clock period
Clock frequency of the system f
Clock period T= 1/f
Time Delay in Loop TL= T*Loop T states * N10
N10 = Equivalent decimal number of hexadecimal count loaded in the delay
register

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Example:
Label opcode operand Description T-state

Clock frequency of the system f = 2 MHz

Clock period= 1/f= 1/2 = 0.5 μs
Time to execute MVI = T-state for MVI*clock period
TO =7 T states * 0.5
= 3.5 μs

Time Delay in Loop TL= T*Loop T states * N10

= 0.5 * 14* 255
= 1785 μs
= 1.8 ms
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Note: 255 is equivalent decimal number of hexadecimal count FF loaded in the register C.
Note: T-states for JNZ instruction are shown as 10/7. The 8085 microprocessor requires 10
T-states to execute a conditional jump when it jumps and seven T-states when in the last
iteration, JNZ will fail (C reaches to zero).
The adjusted loop delay TLA= Time to execute loop instructions =
TL – (3T states* clock period)
=1785- 3*.5
=1785-1.5
=1783.5 μs
Note: The difference between loop delay and adjusted loop delay is approax 2 μs Hence it
can be ignored in some cases.
Total delay TD = Time to execute instructions outside loop (TO) + Time to execute loop
instructions (TL)
= TO+TLA
= 3.5+1783.5 =1787 μs
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 TIME DELAY USING A REGISTER PAIR

The time delay can be increased by setting a loop and using a register pair with
a 16-bit number (maximum FFFF H). The 16-bit number is decremented using
DCX instruction. However the, instruction DCX does not set the zero flag. So,
additional techniques must be used to set the zero flag.
Example:

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 TIME DELAY USING A REGISTER PAIR
Example:

Clock frequency of the system f = 2 MHz Clock period=

1/f= 1/2 = 0.5 μs Decimal equivalent of 2384 H = 909210
Time to execute LXI = T-state for LXI*clock period
TO =10T states * 0.5
=5 μs
Time Delay in Loop TL= T*Loop T states * N10 =0.5*24*9092
=109104 μs
=109 ms
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 Time delay using a loop within a loop
Example: Time Delay using a LOOP within a LOOP

Delay in Loop TL1=1783.5 μs

56 is the decimal equivalent of 38 hexadecimal value.
Delay in Loop TL2= (0.5*21+TL1)*56
= 100.46ms
Timer Delay Using NOP Instruction:
NOP instruction does nothing but takes 4T states of processor time to execute. So by
executing NOP instruction in between two instructions we can get delay of 4 T-state
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12
Counter design with time delay

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 Hexadecimal Counter
Program Statement: Write a program to count continuously in hexadecimal from FFH
to 00H in a system with clock period 0.5 microseconds. Use register C to set up a delay
of 1ms between each count and display output at one of the output ports.
Problem Analysis: 1. The hexadecimal counter is set by loading a register with starting
number and decrementing it till zero is reached and then again decrementing it to will
produce -1, which is two’s complement of FFH. Hence, the register again reaches FFH.
2. The 1ms time delay is set up by the procedure shown in flowchart- The register is
loaded with appropriate number such that the execution of above loop produces a time
delay of 1ms.

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Hexadecimal Counter

Program Statement:
Address Label Mnemonics
2000H MVI B, FFH
2002H NEXT DCR B
2003H MVI C, COUNT
2005H DELAY DCR C
2006H JNZ DELAY
2009H MOV A, B
200AH OUTPORT#
200CH JMP NEXT

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 Hexadecimal Counter

The C register is the time delay register which is Delay outside the loop includes-
loaded by a value COUNT to produce a time delay DCR B : 4T

of 1ms. MVI C, COUNT : 7T

MOV A, B : 4T
To find the value of COUNT we do-
OUTPORT : 10T
TD = TL + TO
JMP : 10T
Where- TD = Time Delay, TL = Time delay inside
Total : 35T
loop, TO = Time delay outside loop TO = 35*Clock period => 17.5
The delay loop includes two instructions- microseconds
DCR C (4 T-states) and JNZ (10 T-states) So,

So, TL = 14*Clock period*COUNT 1ms= (17.5+ 7*COUNT)microsecond

Therefore, COUNT=(140)10
=> 14*(0.5*10-6)*COUNT
=> (7*10-6)*COUNT

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 Illustrative program: Zero-to-nine, (module ten)
Program Statement: Write a program to count from 0 to 9 with a one-second delay between each
count. At the count of 9, the counter should reset itself to 0 and repeat the sequence continuously.
Use register pair HL to set up the delay and display each count at one of the output ports. Assume
the clock frequency of the microcomputer is 1 MHz.
Instructions: Review the following Instructions:
• LXI: Load Register Pair Immediate
• DCX: Decrement Register Pair
• INX: Increment Register Pair
These instructions manipulate 16-bit data by using registers in pairs (BC. DE. and HL). However,
the instructions DCX and INX do not set flags to reflect the outcome of the operation. Therefore,
additional instructions must be used to set the flags.
Problem Analysis: 1.

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 Illustrative program: Zero-to-nine, (module ten)

Problem Analysis: The problem is similar to that in the Illustrative Program for a
hexadecimal counter except in two respects: the counter is an up-counter (counts up to
the digit 9), and the delay is too long to use just one register.
1. The counter is set up by loading a register with the appropriate number and in
crementing it until reaches the digit 9. When the counter register reaches the final
count, it is reset to zero.
2. The 1-second delay between each count is set up by using a register pair.

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Illustrative program: Zero-to-nine, (module ten)

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 Illustrative program: Zero-to-nine, (module ten)
Delay Calculations: The major delay between two counts is provided by the 16-bit number in the
delay register HL. (the inner loop in the flowchart). This delay is set up by using a register pair,
Loop Delay TL = 24 T-states x Tx Count
1 second = 24 x 1.0 x 10 x Count
Count = 1/ 24 × 108 = 41666 = A2C2H
The delay count A2C2H in register HL would provide approximately a 1-second delay between two
counts. To achieve higher accuracy in the delay, the instructions outside the loop starting from OUT
PORT# to JNZ DSPLAY must be accounted for in the delay calculations.
The instructions outside the loop are: OUT, LXI, INR, MOV, CPI, and INZ (DSPLAY). These
instructions require 47 T-states; therefore, the delay count is calculatedas follows:
Total Delay TD = To + TL
1 second = (47 x 1.0 × 10 ) + (24 x 1.0 x 106 x Count)
Count = 41664

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Illustrative program: Generating Pulse Waveform

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Illustrative program: Generating Pulse Waveform

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 Stack
• The stack is an area of memory identified by the programmer for temporary
storage of information.
• The stack is a LIFO structure- Last In First Out.
• The stack normally grows backwards into memory.
• In other words, the programmer defines the bottom of the stack, and the stack
grows up into reducing address range.
Memory

The Stack grows

backwards into
memory
Bottom
of the
Stack

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 Stack

• In the 8085, the stack is defined by setting the SP (Stack Pointer) register.
•LXI SP, FFFFH
•This sets the Stack Pointer to location FFFFH (end of memory for the 8085).
•The Size of the stack is limited only by the available memory
–Information is saved on the stack by PUSHing it on.
–It is retrieved from the stack by POPing it off.
• The 8085 provides two instructions: PUSH and POP for storing information
on the stack and retrieving it back.
• – Both PUSH and POP work with register pairs ONLY.

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 Stack
The PUSH Instruction
• PUSH B (1 Byte Instruction)
• Decrement SP
• Copy the contents of register B to the memory location pointed to by SP
• Decrement SP
• Copy the contents of register C to the memory location pointed to by SP

B C
12 F3

FFFB
FFFC
FFFD F3
FFFE 12
FFFF SP

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 Stack
• The POP Instruction
• POP D (1 Byte Instruction)
–Copy the contents of the memory location pointed to by the SP to register E
–Increment SP
–Copy the contents of the memory location pointed to by the SP to register D
–Increment SP

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 Stack
PUSH PSW Register Pair
–This register pair is made up of the Accumulator and the Flags registers. PUSH
PSW (1 Byte Instruction)
–Decrement SP
–Copy the contents of register A to the memory location pointed to by SP
–Decrement SP
–Copy the contents of Flag register to the memory location pointed to by SP

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 Stack
POP PSW (1 Byte Instruction)
– Copy the contents of the memory location pointed to by the SP to Flag
register
–Increment SP
–Copy the contents of the memory location pointed to by the SP to register A
–Increment SP

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 Code Conversion
• The ASCII (American Standard Code For Information Interchange) keyboard is a commonly
used input device for disk-based microcomputer systems.
• Alphanumeric characters (letters and numbers) are displayed on a CRT (cathode ray tube)
terminal using the ASCII code. However, inside the microprocessor data processing is usually
performed in binary.
• In some instances, arithmetic operations are performed in BCD numbers. Therefore, data must
be converted from one code to another code.
• The programming techniques used for code con version fall into four general categories:
1. Conversion based on the position of a digit in a number (BCD to binary and vice versa).
2. Conversion based on hardware consideration (binary to seven-segment code using table
look- up procedure).
3. Conversion based on sequential order of digits (binary to ASCII and vice versa).
4. Decimal adjustment in BCD arithmetic operations. (This is an adjustment rather than a
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code conversion.)
 BCD To Binary Conversion
• In most microprocessor-based products, data are and displayed in decimal numbers.
• The system-monitor program of instrument converts each key into an equivalent 4-bit number, stores two
numbers an Two BCD numbers in an 8-bit register memory location. These numbers called packed BCD.
• Even if data are entered in decimal digits, it is inefficient to process data in BCD numbers because, in each
4-bit combination, digits A through F go unused. Therefore, BCD numbers are converted into binary
numbers for data processing.
• The conversion of BCD number into its binary equivalent employs the principle positional weighting in a
given number.
• For example: 7210 = 7 × 10 + 2
• The digit 7 represents 70, based on its second position the right. Therefore, converting 72BCD into its binary
equivalent requires multiplying second digit 10, and adding digit.
• Converting 2-digit BCD number into binary equivalent the following steps:
– Separate an 8-bit packed BCD number into 4-bit unpacked digits: BCD1, and BCD₂.
– Convert each digit into its binary value according to its position.
– Add both binary numbers to obtain the binary equivalent of the BCD numbers.
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BCD To Binary Conversion

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BCD To Binary Conversion

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BCD To Binary Conversion

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 Binary to BCD Conversion
• Microprocessor-based products, numbers are displayed in decimal. However, if data processing inside the
microprocessor is performed in binary, it is necessary to convert the binary results into their equivalent BCD
numbers just before they are displayed.
• Results are quite often stored in R/W memory locations called the Output Buffer.
• The conversion of binary to BCD is performed by dividing the number by the powers of ten and the division
is performed by the subtraction method.
For example,
1111 11112 (FFH) = 25510
• To represent this number in BCD requires twelve bits or three BCD digits, labelled here as BCD3 (MSB),
BCD₂, and BCD1 (LSB),
= 0010 0101 0101
BCD3 BCD₂ BCD₁

The conversion can be performed as follows:

Step 1: If the number is less than 100, go to Step 2; otherwise, divide by 100 or subtract 100 repeatedly until the
remainder is less than 100. The quotient is the most significant BCD digit BCD₁.
Step 2: If the number is less than 10, go to Step 3, otherwise divide by 10 repeatedly until the remainder is less
than 10. The quotient is BCD₂.
Step 3: The remainder from step 2 is BCD₁.

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 Binary to BCD Conversion
• Microprocessor-based products, numbers are displayed in decimal. However, if data processing inside the
microprocessor is performed in binary, it is necessary to convert the binary results into their equivalent BCD
numbers just before they are displayed.
• Results are quite often stored in R/W memory locations called the Output Buffer.
• The conversion of binary to BCD is performed by dividing the number by the powers of ten and the division
is performed by the subtraction method.
For example
1111 11112 (FFH) = 25510
• To represent this number in BCD requires twelve bits or three BCD digits, labelled here as BCD3 (MSB),
BCD₂, and BCD1 (LSB),
= 0010 0101 0101
BCD3 BCD₂ BCD₁

The conversion can be performed as follows:

Step 1: If the number is less than 100, go to Step 2; otherwise, divide by 100 or subtract 100 repeatedly until the
remainder is less than 100. The quotient is the most significant BCD digit BCD₁.
Step 2: If the number is less than 10, go to Step 3, otherwise divide by 10 repeatedly until the remainder is less
than 10. The quotient is BCD₂.
Step 3: The remainder from step 2 is BCD₁.

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Binary to BCD Conversion

36
Binary to BCD Conversion

37
Binary to BCD Conversion

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 BCD to Seven Segment Conversion
• Many times 7-segment LED display is used to display the results or
parameters in the microprocessor system.
• In such cases we have to convert the result or parameter in 7-segment code.
• This conversion can be done using look-up technique.
• In the look-up table the codes of the digits (0-9) to be displayed are stored
sequentially in the memory.
• The conversion program locates the code of a digit based on its BCD digit.
• Let us see the Program for BCD to common cathode 7-segment code
conversion.

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BCD to Seven Segment Conversion

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 BCD to Seven Segment Conversion
Problem Statement: Find the 7 segment codes for given 5 numbers from
memory location 6000H and store the result from memory location 7000H.

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 Binary to ASCII Code Conversion
• The ASCII Code (American Standard Code for Information Interchange) is
commonly used for communication.
• In such cases we need to convert binary number to its ASCII equivalent.
• It is a seven bit code.
• In this code number 0 through 9 are represented as 30 through 39
respectively and letters A through Z are represented as 41H through 5AH.
• Therefore, by adding 30H we can convert number into its ASCII equivalent
and by adding 37H we can convert letter to its ASCII equivalent.
• Let us see the Program for binary to ASCII code conversion.

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Binary to ASCII Code Conversion

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 Binary to ASCII Code Conversion
Program

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 ASCII Code to Binary Conversion
• It is exactly reverse process to binary to ASCII conversion.
• Here, if ASCII code is less than 3AH then 30H is subtracted to get the
binary equivalent and if it is in between 41H and 5AH then 37H is
subtracted to get the binary equivalent of letter (A-F).

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 BCD Addition
• The microprocessor cannot recognize BCD numbers; it adds any two numbers in binary. In
BCD addition, any number larger than 9 (from A to F) is invalid and needs to be adjusted by
adding 6 in binary.
• E.g. A: 0000 1010
+ 0000 0110
0001 0000 10 BCD
A special instruction called DAA performs the function of adjusting a BCD sum in 8085. It uses
the AC flag to sense that the value of the least four bits is larger than 9 and adjusts the bits to BCD
value. Similarly, it uses CY flag to adjust the most significant four bits.
E.g. Add BCD 77 and 48
77 = 0111 0111
+48 = 0100 1000
125 = 1011 1111
+0110
1 0101
+0110
CY = 0010 0101 25 BCD

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BCD Addition (2-digit)

47
BCD Addition (4-digit)

48
BCD Subtraction

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 BCD Subtraction
• 8085 performs subtraction operation by using 2’s complement and the steps used are:
1) Converts the subtrahend (the number to be subtracted) into its 1’s complement.
2) Adds 1 to 1’s complement to obtain 2’s complement of the subtrahend.
3) Adds 2’s complement to the minuend (the contents of the accumulator).
4) Complements the carry flag.

E.g. MVI A, 97H 65H: 0 1 1 0 0 1 0 1

MVI B, 65H 1’s complement of 65H : 1 0 0 1 1 0 1 0
SUB B +1
2’s Complement of 65H: 1 0 0 1 1 0 1 1
97H: +10010111
100110010
32
CY
Complement carry = 0 A=32 CY=0

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 BCD Subtraction
B=97H, A=65H
97H: 10010111
MVI B, 65H 1’s complement of 97H: 01101000
SUB B +1
2’s Complement of 97H: 0 1 1 0 1 0 0 1
65H: + 0 1 1 0 0 1 0 1
011001110
(Result in 2’s complement form)
CY
CY=1, A= CE: 110011110
1’s complement: 001100001
2’s complement: 001100010
32

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BCD Multiplication

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