NEHRU COLLEGE OF ENGINEERING AND RESEARCH CENTRE(AUTONOMUS)-KTU-89 DRAFT CURRICULUM COPY
Course Title: FPGA BASED SYSTEM DESIGN
Course Code: 23PVFSDT103 CIE Marks: 40
Teaching Hours/week(L:T:P) 3:1:0 SEE Marks:60
Total Contact Hours: 45 Total Marks: 100
Course Credits: 4 ExamDuration:3 hours
Course Outcomes (COs) with Revised Cognitive levels:
U-Understanding, R-Remembering-Applying, A-Analyzing, E-Evaluating, C-Creating
Course Description Revised
Outcomes Cognitive
levels
CO1 To apply verilog programming to develop and simulate digital sub systems. AP
CO2 To design RT-level combinational and regular sequential circuits C
CO3 To construct FSM and FSMD A
CO4 To analyse and implement UART subsystems in FPGA E
CO5 To explain architecture and features of programmable logic devices A
Contact
Unit Description
Hours
I (Verilog HDL – based design, Overview of FPGA and EDA software)
Introduction, General description, Basic lexical elements and data types, Data 08
types, Program skeleton, Structural description, Gate-level combinational
circuit, Testbench, Introduction and overview of a general FPGA device,
Overview of the Digilent S3 board, Development flow, Overview of the
digital design tool (Vivado / Xilinx ISE/any other open software) Suggested
experiments- Gate-level greater-than circuit, Gate-level binary decoder
II (RT-level combinational circuit and Regular sequential circuit)
Introduction, Operators, Always block for a combinational circuit, if
statement, Case statement, General coding guidelines for an always block,
10
Parameter and constant, Design examples: shift register, Binary counters,
Introduction to Regular Sequential Circuit, HDL code of the FF and register,
Test bench for sequential circuits, Case study
NEHRU COLLEGE OF ENGINEERING AND RESEARCH CENTRE(AUTONOMUS)-KTU-89 DRAFT CURRICULUM COPY
III (FSM & FSMD)
FSM: Introduction, FSM representation and code development, Mealy and 09
Moore outputs, Design examples. FSMD-Introduction, ASMD chart, Code
development of an FSMD, Design examples
IV (Implementation of UART sub system)
Introduction, UART receiving subsystem, UART transmitting subsystem, 09
Overall UART system Micro Project-Full-featured UART, UART with an
automatic baud rate detection circuit, UART with an automatic baud rate and
parity detection circuit, UART-controlled stopwatch, UART-controlled
rotating LED banner.
V (External SRAM and Programmable logic devices)
External SRAM: Introduction, Specification of the IS61LV25616AL SRAM, 09
Basic memory controller, a safe design. Programmable logic Devices: ROM,
PLA, PAL, CPLD, FPGA Features, Limitations, Architectures.
Question paper pattern:
1. The question paper will have Part A and Part B.
2. Part A contains 5 questions of 3 marks each which are compulsory with a total of 15 marks.
3. Part B contains 5 questions of 9 marks each, two questions from each module with choice for
attempting one question from each module and total will be 45 marks.
NEHRU COLLEGE OF ENGINEERING AND RESEARCH CENTRE(AUTONOMUS)-KTU-89 DRAFT CURRICULUM COPY
Sl. Name of the Name of
Title of the Book Edition and
Author/s the
No. Year
Publisher
Textbooks
1 FPGA Prototyping by Pong P. Chu John Wiley & 2008
Verilog Examples Sons
2 FPGA-Based System Design Wayne Wolf, Prentice Hall
Verlag
Reference Books
1 Modern VLSI Design: Wayne Wolf, System-on- (3rd Edition)
Verlag Chip Design
2 Field Programmable Gate S.Trimberger, Kluwer 1994
Array Technology Edr Academic
3 Digital Design Using Field P.K. Chan & S. Prentice Hall 1994
Programmable Gate Array Mourad
Web links and Video Lectures:
1. https://nptel.ac.in/courses/7
2. http://academicearth.org/
Activity-Based Learning (Suggested Activities in Class/ Practical)
1. Quiz
2. Assignment
3. Seminars
