VIVEK PAL
FUTERWIZ TRAINEE, ELECTRONICS & COMMUNICATION ENG.
TREASURE, IEEE CKPCET SB
EDUCATION CONTACT
2021 - 2025
8200788380
B.E, IN ELECTRONICS & COMMUNICATION, FROM
C.K PITHAWALA COLLEGE OF ENGINEERING AND
[email protected]
TECHNOLOGY,SURAT,GUJARAT
with 7.77 CGPA surat,Gujarat
2019 - 2020
www.linkedin.com/in/viv
HIGHER SECONDARY EDUCATION(12TH) IN
ek-pal-b025b9265
SARASWATI SCIENCE SCHOOL.
2017-2018
SECONDARY EDUCATION (10 T H ) IN SARASWATI SUMMARY
VIDHYALAYA. Motivated Electronics and
Communication Engineering
TRAINING AND EXPERIENCE graduate with a strong interest in
the VLSI domain. Currently gaining
FUTURWIZ: Digital Design & Verification hands-on experience as a Trainee at
Acquired strong practical skills in Advanced Digital Design
Futurwiz, focused on developing
concepts.
skills in VLSI design and verification.
Developed digital circuits using Verilog with extensive hands-on
Eager to apply technical knowledge
experience.
and grow in the semiconductor
Gained proficiency in System Verilog for complex verification
industry through continuous
tasks.
learning and practical exposure.
Applied UVM techniques for structured functional verification of
designs.
VLSI FOR BEGGGINERS: Calicut University. SKILLS
VERILOG HDL: VLSI Hardware Design Comprehensive - Adavanced Digital Design.
UDEMY. Verilog.
System Verilog.
PROJECTS UVM.
Trafic light controller:
Problem Solving.
Designed a traffic light controller using Verilog, implementing
Leadership Skill.
timing logic and state machines for efficient signal sequencing.
Time Management.
EXTRA CURRICULAR LANGUAGE
Treasurer ,IEEE CKPCET SB(2023 -2024). English.
Member of IEEE CKPCET SPS SBC (2022-2024). Hindi.
Gujarati.
