Enrolment No.
/Seat No_______________
GUJARAT TECHNOLOGICAL UNIVERSITY
BE- SEMESTER–III (NEW) EXAMINATION – WINTER 2024
Subject Code: 3131704 Date: 21-11-2024
Subject Name: Digital Electronics
Time: 10:30 AM TO 01:00 PM Total Marks: 70
Instructions:
1. Attempt all questions.
2. Make suitable assumptions wherever necessary.
3. Figures to the right indicate full marks.
4. Simple and non-programmable scientific calculators are allowed.
MARKS
Q.1 (a) Show how a full adder can be converted to a full subtractor with the 03
help of inverter circuit.
(b) Convert the following numbers into binary. 04
(i) (25.8)10
(ii) (47FD)16
(iii) (573.2)8
(c) Simplify the Boolean function F using don’t care conditions d, in (i) 07
sum of products and (ii) product of sums
F = w’(x’y + x’y’ + xyz) + x’z’(y + w)
d = w’x(y’z + yz’) + wyz
Q.2 (a) What do you mean by reflected code? Show one of the possible 03
combination of 4-bit reflected code.
(b) Explain standard and canonical forms along with example. 04
(c) Design a combinational circuit for BCD to excess-3 code converter. 07
OR
(c) Explain clocked RS flip-flop with circuit diagram and truth table. Also 07
discuss about limitation of RS flip-flop.
Q.3 (a) Construct a 4 x 16 decoder with 3x 8 decoder. 03
(b) Differentiate between 04
(i) Combination and sequential circuits
(ii) Edge triggered and level triggered flip-flop
(c) Explain the 4-bit magnitude comparator with necessary diagrams and 07
equations.
OR
Q.3 (a) Implement NOT, AND & OR gates with the help of NAND gate. 03
(b) Explain Master-Slave flip-flop. 04
(c) Explain bus system for four registers. 07
Q.4 (a) Prove the following Boolean expression using Boolean algebra 03
simplification.
BC + AC’ + AB + BCD = BC + AC'
(b) Explain TTL gate with Totem-pole output 04
(c) Explain ring counter in detail. 07
OR
1
Q.4 (a) Represent the decimal number 8620 in 03
(i) BCD
(ii) Excess-3 code
(iii) 5421 code
(b) Express the following function in a sum of minterms and a product of 04
maxterms.
F(A, B, C, D) = D(A’ + B) + B’D
(c) Explain 4-bit bidirectional shift register with parallel load. 07
Q.5 (a) Explain the working of JK flip-flop. 03
(b) Define 04
(i) Fan-out
(ii) Power Dissipation
(iii) Propagation delay
(iv) Noise Margin
(c) Design 3-bit Binary counter with T flip-flops. 07
OR
Q.5 (a) Explain Macro-operations versus Micro-operations. 03
(b) Explain arithmetic and logic micro-operations. 04
(c) Design BCD counter with T flip-flops. 07
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