Dataflow Modeling
Dr.Ravi Sindal
IET,DAVV,Indore
Introduction
Gate-level modeling is very intuitive to a designer
with a basic knowledge of digital logic design.
However, in complex designs the number of gates is
very large. Thus, designers can design more
effectively if they concentrate on implementing the
function at a level of abstraction higher than gate
level.
Dataflow modeling provides a powerful way to
implement a design.
Verilog allows a circuit to be designed in terms of
the data flow between registers and how a design
processes data rather than instantiation of individual
gates.
Dr.Ravi Sindal,IET,DAVV,Indore
With gate densities on chips increasing rapidly,
dataflow modeling has assumed great
importance.
Currently, automated tools are used to create a
gate-level circuit from a dataflow design
description. This process is called logic
synthesis.
Dataflow modeling has become a popular
design approach as logic synthesis tools have
become sophisticated.
This approach allows the designer to
concentrate on optimizing the circuit in terms of
data flow. Dr.Ravi Sindal,IET,DAVV,Indore
For maximum flexibility in the design process,
designers typically use a Verilog description
style that combines the concepts of gate-level,
data flow, and behavioral design.
In the digital design community , the term RTL
(Register Transfer Level) design is commonly
used for a combination of dataflow modeling and
behavioral modeling.
Dr.Ravi Sindal,IET,DAVV,Indore
Continuous Assignments
A continuous assignment is the most basic
statement in dataflow modeling, used to drive a
value onto a net.
A continuous assignment replaces gates in the
description of the circuit and describes the circuit
at a higher level of abstraction.
A continuous assignment statement starts with
the keyword assign
Dr.Ravi Sindal,IET,DAVV,Indore
1)Drive strength is optional and can be specified in
terms of strength levels.
2)The default value for drive strength is strong1 and
strong0.
3)The delay value is also optional and can be used to
specify delay on the assign statement.
4)This is like specifying delays for gates.
Dr.Ravi Sindal,IET,DAVV,Indore
Continuous assignments characteristics.
1.The left hand side of an assignment must always be a
scalar or vector net or a concatenation of scalar and
vector nets. It cannot be a scalar or vector register.
2. Continuous assignments are always active. The
assignment expression is evaluated as soon as one of
the right-hand-side operands changes and the value is
assigned to the left-hand-side net.
3. The operands on the right-hand side can be registers
or nets or function calls. Registers or nets can be scalars
or vectors.
4. Delay values can be specified for assignments in
terms of time units. Delay values are used to control the
time when a net is assigned the evaluated value. This
feature is similar to specifying delays for gates. It is very
useful in modeling timing behavior in real circuits.
Dr.Ravi Sindal,IET,DAVV,Indore
Examples of Continuous Assignment
Dr.Ravi Sindal,IET,DAVV,Indore
Implicit Continuous Assignment
Instead of declaring a net and then writing a
continuous assignment on the net, Verilog
provides a shortcut by which a continuous
assignment can be placed on a net when it is
declared.
There can be only one implicit declaration
assignment per net because a net is declared
only once.
Dr.Ravi Sindal,IET,DAVV,Indore
Dr.Ravi Sindal,IET,DAVV,Indore
Delays
Delay values control the time between the
change in a right-hand-side operand and when
the new value is assigned to the left-hand side.
Three ways of specifying delays in continuous
assignment statements are regular assignment
delay, implicit continuous assignment delay, and
net declaration delay.
Dr.Ravi Sindal,IET,DAVV,Indore
Regular Assignment Delay
The first method is to assign a delay value in a
continuous assignment statement. The delay
value is specified after the keyword assign.
Any change in values of in1 or in2 will result in a
delay of 10 time units before recomputation of
the expression in1 & in2, and the result will be
assigned to out.
If in1 or in2 changes value again before 10 time
units when the result propagates to out, the
values of in1 and in2 at the time of
recomputation are considered.
This property is called inertial delay. An input
pulse that is shorter than the delay of the
assignment statement does not propagate to the
output. Dr.Ravi Sindal,IET,DAVV,Indore
Dr.Ravi Sindal,IET,DAVV,Indore
Dr.Ravi Sindal,IET,DAVV,Indore
Implicit Continuous Assignment Delay
An equivalent method is to use an implicit
continuous assignment to specify both a delay
and an assignment on the net.
Dr.Ravi Sindal,IET,DAVV,Indore
Net Declaration Delay
A delay can be specified on a net when it is
declared without putting a continuous
assignment on the net.
If a delay is specified on a net out, then any
value change applied to the net out is delayed
accordingly.
Dr.Ravi Sindal,IET,DAVV,Indore
Expressions
Expressions are constructs that combine
operators and operands to produce a result.
Dr.Ravi Sindal,IET,DAVV,Indore
Operands
Operands can be any one of the data types .
Some constructs will take only certain types of
operands.
Operands can be constants, integers, real
numbers, nets, registers, times, bit-select (one
bit of vector net or a vector register), part-select
(selected bits of the vector net or register
vector),memories or function calls
Dr.Ravi Sindal,IET,DAVV,Indore
Dr.Ravi Sindal,IET,DAVV,Indore
Operators
Operators act on the operands to produce
desired results.
Verilog provides various types of operators.
Dr.Ravi Sindal,IET,DAVV,Indore
Operator Types and Symbols
Dr.Ravi Sindal,IET,DAVV,Indore
Dr.Ravi Sindal,IET,DAVV,Indore
Arithmetic Operators
Binary operators
Binary arithmetic operators are multiply (*),
divide (/), add (+), subfract (-) and modulus (%).
Binary operators take two operands.
If any operand bit has a value X, then the result
of the entire expression is X.
Modulus operators produce the remainder from
the division of two numbers
Dr.Ravi Sindal,IET,DAVV,Indore
Dr.Ravi Sindal,IET,DAVV,Indore
Unary operators
The operators + and - can also work as unary
operators.
They are used to specify the positive or negative
sign of the operand.
Unary + or - operators have higher precedence
than the binary + or - operators.
Negative numbers are represented as 2's
complement internally in Verilog.
It is advisable to use negative numbers only of
the type integer or real in expressions
Dr.Ravi Sindal,IET,DAVV,Indore
Dr.Ravi Sindal,IET,DAVV,Indore
Logical Operators
Logical operators are logical-and (&&), logical-or (ll ) and
logical-not (! ).
Operators && and ll are binary operators. Operator ! is a
unary operator.
Logical operators always evaluate to a 1-bit value, 0
(false), 1 (true), or X (ambiguous).
If an operand is not equal to zero, it is equivalent to a
logical 1 (true condition). If it is equal to zero, it is
equivalent to a logical 0 (false condition). If any operand
bit is X or z, it is equivalent to X (ambiguous condition)
and is normally treated by simulators as a false condition.
Logical operators take variables or expressions as
operands.
Dr.Ravi Sindal,IET,DAVV,Indore
Dr.Ravi Sindal,IET,DAVV,Indore
Relational Operators
Relational operators are greater-than (>), less-
than (<),greater-than-or-equal-to (>=),and less-
than-or-equal-to (<=).
If relational operators are used in an expression,
the expression returns a logical value of 1 if the
expression is true and 0 if the expression is false.
If there are any unknown or z bits in the
operands, the expression takes a value X.
Dr.Ravi Sindal,IET,DAVV,Indore
Dr.Ravi Sindal,IET,DAVV,Indore
Equality Operators
Equality operators are logical equality (==),
logical inequality ( !=) ,case equality (===), and
case inequality (!==).
When used in an expression, equality operators
return logical value 1 if true, 0 if false.
These operators compare the two operands bit
by bit, with zero filling if the operands are of
unequal length.
Dr.Ravi Sindal,IET,DAVV,Indore
It is important to note the difference between the
logical equality operators (==, !=) and case
equality operators (===, !==).
The logical equality operators (==,! =) will yield
an X if either operand has X or z in its bits.
However, the case equality operators (===, !==)
compare both operands bit by bit and compare
all bits, including X and z. The result is 1 if the
operands match exactly, including X and z bits.
The result is 0 if the operands do not match
exactly.
Case equality operators never result in an X.
Dr.Ravi Sindal,IET,DAVV,Indore
Dr.Ravi Sindal,IET,DAVV,Indore
Bitwise Operators
Bitwise operators are negation (~), and(&), or (l ),
xor (^), xnor (^~, ~^).
Bitwise operators perform a bit-by-bit operation
on two operands.
They take each bit in one operand and perform
the operation with the corresponding bit in the
other operand.
If one operand is shorter than the other, it will be
bit extended with zeros to match the length of
the longer operand.
Dr.Ravi Sindal,IET,DAVV,Indore
Truth Tables for Bitwise Operators
Dr.Ravi Sindal,IET,DAVV,Indore
Dr.Ravi Sindal,IET,DAVV,Indore
It is important to distinguish bitwise operators ~, &, and l
from logical operators !, &&, ll.
Logical operators always yield a logical value of 1, X,
whereas bitwise operators yield a bit-by-bit value.
Logical operators perform a logical operation,not a bit-
by-bit operation.
Dr.Ravi Sindal,IET,DAVV,Indore
Reduction Operators
Reduction operators are and (&), nand (~&), or ( I ), nor
(~ I ), xor (^), and xnor (~^,^~).
Reduction operators take only one operand.
Reduction operators perform a bitwise operation on a
single vector operand and yield a 1-bit result.
Dr.Ravi Sindal,IET,DAVV,Indore
Shift Operators
Shift operators are right shift ( >>) and left shift (<<).
These operators shift a vector operand to the right or the
left by a specified number of bits.
The operands are the vector and the number of bits to
shift.
When the bits are shifted, the vacant bit positions are
filled with zeros.
Shift operations do not wrap around.
Shift operators are useful because they allow the
designer to model shift operations, shift-and-add
algorithms for multiplication.
Dr.Ravi Sindal,IET,DAVV,Indore
Dr.Ravi Sindal,IET,DAVV,Indore
Concatenation Operator
The concatenation operator ( {,} ) provides a
mechanism to append multiple operands.
The operands must be sized.
Unsized operands are not allowed because the
size of each operand must be known for
computation of the size of the result.
Concatenations are expressed as operands
within braces, with commas separating the
operands. Operands can be scalar nets or
registers, vector nets or registers,bit-select, part-
select, or sized constants.
Dr.Ravi Sindal,IET,DAVV,Indore
Dr.Ravi Sindal,IET,DAVV,Indore
Replication Operator
Repetitive concatenation of the same number
can be expressed by using a replication constant.
A replication constant specifies how many times
to replicate the number inside the brackets ( { } ).
Dr.Ravi Sindal,IET,DAVV,Indore
Conditional Operator
The conditional operator(? :) takes three
operands.
Usage: condition-expr ? true-expr : false-expr ;
The condition expression (condition-expr) is first
evaluated. If the result is true (logical 1), then the
true-expr is evaluated. If the result is false
(logical 0), then the false-expr is evaluated.
If the result is X (ambiguous), then both true-
expr and false-expr are evaluated and their
results are compared, bit by bit, to return for
each bit position an X if the bits are different and
the value of the bits if they are the same.
Dr.Ravi Sindal,IET,DAVV,Indore
The action of a conditional operator is similar to
a multiplexer.
Alternately, it can be compared to the if-else
expression.
Dr.Ravi Sindal,IET,DAVV,Indore
Conditional operators are frequently used in dataflow
modeling to model conditional assignments.
The conditional expression acts as a switching control.
Conditional operations can be nested. Each true-expr or
false-expr can itself be a conditional operation.
Dr.Ravi Sindal,IET,DAVV,Indore
Operator Precedence
Dr.Ravi Sindal,IET,DAVV,Indore
4-to-1 Multiplexer
Method 1: logic equation
Dr.Ravi Sindal,IET,DAVV,Indore
Method 2: conditional operator
Dr.Ravi Sindal,IET,DAVV,Indore
4-bit Full Adder
Method 1: dataflow operators
Dr.Ravi Sindal,IET,DAVV,Indore
