DEIE / Semester – 5th / Subject: Microprocessor

Group – B
Module - 3

Programming of 8085 Microprocessor

• 3.1 Instruction set of 8085
• 3.2 Addressing modes
• 3.3 Writing assembly language program- looping,
counting, indexing, BCD arithmetic, stack and
subroutine, Delay, conditional call & return
Instruction
 Instruction Set of 8085 Microprocessor
Classification of Instruction Set

Data Transfer Group

Arithmetic Group

Logical Group

Branch Control Group

I/O and Machine Control Group

Data Transfer Group:

Instructions, which are used to transfer data from one register to

another register or from memory to register or register to memory,
come under this group.

Examples are: MOV, MVI, LXI, LDA, STA etc.

When an instruction of data transfer group is executed, data is transferred

from the source to the destination without altering the contents of the source.

Example: when MOV A, B is executed, the content of the register B is copied

into the register A, and the content of register B remains unaltered. Similarly,
when LDA 2500 is executed the content of the memory location 2500 is loaded
into the accumulator. But the content of the memory location 2500 remains
unaltered.

Arithmetic Group:

The instructions of this group perform arithmetic operations such as addition,

subtraction; increment or decrement of the content of a register or memory.

Examples are: ADD, SUB, INR, DAD etc.

Logical Group:

The instruction under this group perform logical operation such as AND, OR,
compare, rotate etc.
Examples are: ANA, XRA, ORA, CMP, RAL etc.

Branch Control Group:

This group includes the instructions for conditional and unconditional jump,
subroutine call and return, and restart.

Examples are: JMP, JC, JZ, CALL, CZ, RST etc.

I/O and Machine Control Group:

This group includes the instructions for input/output of Data to and from ports,
stack purpose and machine control purpose.

Examples are: IN, OUT, PUSH, POP, HLT etc.

Instruction and Data formats

Intel 8085 microprocessor handles 8-bit data at a time. One byte
consists of 8 bits.

A memory location for Intel 8085 microprocessor is designed to

accommodate 8-bit data.

If 16-bit data are to be stored, they are stored in two consecutive memory
locations. The address of a memory location is of 16 bits i.e. 2 bytes.

The various techniques to specify data for instructions

are:
8–bit or 16-bit data may be directly given in the instruction itself.

The address of the memory location, I/O port or I/O device, where data
resides, may be given in the instruction itself.

In some instructions only one register is specified. The content of the

specified register is one of the operands. It is understood that the other
operand is in the accumulator.
In some instructions data are implied. The most instructions of this type
operate on the content of the accumulator.

Due to different ways of specifying data for instructions, the machine codes of
all instructions are not of the same length.

There are three types of the Intel 8085 instructions depending upon their size
(in ‘Byte’) as described below:

Single – Byte Instruction

Two – Byte Instruction

Three-Byte Instruction

Address modes
Each instruction requires certain data on which it has to operate. It has already
been explained that there are various techniques to specify data for
instructions. These techniques are called addressing modes. Intel 8085 uses
the following addressing modes.

Direct addressing

Register addressing

Register indirect addressing

Immediate addressing

Direct Addressing:
In this mode of addressing the address of the operand (data) is given in the
instruction itself.

Examples are:

STA 2400(H): Store the content of the accumulator in the memory location
2400(H).

The relevant code is: 32, 00, 24 (H)

In this instruction 2400(H) is the memory address where data is to be stored. It
is given in the instruction itself. The 2nd and 3rd bytes of the instruction specify
the address of the memory location. Here, it is understood that the source of
the data is accumulator.

IN 02: Read data from the port C

DB, 02: Instruction in the code form.

In this instruction 02 is the address of the port C of an I/O port from where the
data is to be read. Here, it is implied that the destination is the accumulator.
The 2nd byte of the instruction specifies the address of the port.

Register Addressing:
In register addressing mode the operands are in the general purpose registers.
The Opcode specifies the address of the registers in addition to the operation
to be performed.

Examples are:

1) MOV A, B: Move the content of the register B to register A.

78 The instruction in the code form.

2) ADD B: Add the content of register B to the content of register A.

80 The instruction in the code form.

In example 1 the Opcode for MOV A, B is 78H. Besides the operation to be

performed the Opcode also specifies the registers, which contain data. The
Opcode 78H can be written in binary form as 01111000. The first two bits, i.e.
01 are for MOV operation, the next three bits 111 are the binary code for
register A, and the last three bits 000 are the binary code for register B.

In example 2 the Opcode for ADD B is 80H. IN this instruction one of the
operands is register B (its content is one of the data), which is indicated in the
instruction itself. In this type of instruction (arithmetic group) it is understood
that the other operand is in the accumulator. The Opcode 80H in the binary
form is 1000000. The first five bits, i.e. 10000 specify the operation to be
performed, i.e. ADD. The last three bits 000 are the binary code for register B
of 8085 microprocessor.

Register Indirect Addressing:

In this mode of addressing the address of the operand is specified by a register
pair. Examples are:

LXI H, 2500 H Load H-L pair with 2500 H.

MOV A,M Move the content of the memory location, whose address is

in H-L pair (i.e. 2500 H) to the accumulator

HLT Halt

In the above program the instruction MOV A, M is an example of register

indirect addressing. For this instruction the operand is in the memory. The
address of the memory is not directly given in the instruction. The address of
the memory resides in H-L pair and this has already specified by an earlier
instruction in the program, i.e. LXIH, 2500H.

LXI H, 2500 H-Load the H-L pair with 2500 H.

ADD M Add the content of the memory location, whose address is in

H-L pair (i.e. 2500 H), to the content of the accumulator.

HLT Halt

In this program the instruction ADD M is an example of register indirect

addressing.

Implicit Addressing:
There are certain instructions, which operate on the content of the
accumulator. Such instructions do not require the address of the operand.
Examples are: CMA, RAL, and RAR etc.
Some of Intel 8085 instructions are frequently, some occasionally
and some seldom used by the programmer. It is not necessary that
one should learn all the instructions to understand simple
programs. The beginner can learn about 15 to 20 important
instructions such as MOV, MVI, LXI, LDA, LHLD, STA, SHLD, ADD,
ADC, SUB, JMPJC, JNC, JZ, INZ, INX, DCR, CMP etc., and start to
understand simple programs given in later pages. While learning
programs one can understand new instructions, which he has not
learnt earlier. The explanations of some of the instructions are
given below.

Data Transfer Group:

MOV r1, r2

(Move data; Move the content of the one register to another)

[r1][r2]. States 4. Flags none. Addressing; register. Machine cycle:1.

The content of register r2 is moved to register r1. For example, the

instruction MOV A, B moves the content of register B to register A. The
instruction MOV B, A moves the content of register A to register B. The
time for the execution of this instruction is 4 clock period. One clock
period is called State. No flag is affected.

MOV r,M

(Move the content of memory to register)

[r][[H-L]]. States 7. Flag none. Addressing register indirect. Machine

cycles 2. The content of the memory location, whose address is in H – L pair, is
moved to register r.

Example:

LXI H, 2000H Load H-L pair by 2000H

MOV B, M Move the content of the memory location 2000H to

register B.
HLT Halt

In this example the instruction LXI H, 2000H loads H – L pair with 2000 H which
is the address of a memory location. Then the instruction MOV B, M will move
the content on the memory location 2000H to register B.

MOV M, r

(Move the content of register to memory).

[[H-L]][r]. States 7. Flags: none. Addressing: reg. indirect. Machine cycles: 2

The instruction is 1 byte. The data stored in register ‘r’ will be copied in the
memory address stored in H – L register pair.

MVI M, data

(Move immediate data to memory)

[[H-L]] data. States 10. Flags none. Addressing immediate/reg. indirect.

Machine cycle: 3. The data is moved to memory location whose address is in H-
L pair.

Example:

LXI H, 2400H Load H – L pair with 2400H

MVI M, 08 Move 08 to the memory location 2400H

HLT Halt.

In the above example the instruction LXI H, 2400 H loads H – L pair with 2400 H
which is the address of a memory location. Then the instruction MVI M, 08 will
move 08 (H) data to memory location 2400 H. In the code form it is written as
36, 08. The Opcode for MVI is 36 and 08 (H) is the data which is to be moved to
the memory location 2400 H.
LXI rp, data 16Bit

(Load register pair immediate)

[rp] data 16 bits, [rh]8 MSBs [rl]8 LSBs of data.
States: 10 Flags: none. Addressing immediate. Machine cycles: 3
This instruction loads 16-bit immediate data into register pair rp. This
instruction is for register pair; only high order register is mentioned after the
instruction. For example, H in the instruction LXI H stands for H – L pair.
Similarly, LXI B is for B-C pair. LXI H, 2500 H loads 2500 H into H-L pair.
In the code form it is written as 21, 00, 25. The 1st byte 3A is the opcode of the
instruction. The 2nd byte 00 is of 8 LSBs of the memory address. The 3rd byte
25 is 8 MSBs of the memory address.

STA Addr 16Bit

(Store accumulator direct)

[addr][A]. States 13. Flags none. Addressing direct, Machine cycles: 4

The content of the accumulator is stored in the memory location whose

address is specified by the 2nd and 3rd byte of the instruction. STA 2000H will
store the content of the accumulator in the memory location 2000 H.

LHLD addr16Bit

[Load H – L pair direct]

[L] [addr], [H][addr+1]. States: 16 Flags none, Adressing : direct. Machine

cycles 5.

The content of the memory location, whose address is specified by the 2nd and
3rd bytes of the instruction, is loaded into register L. The content of the next
memory location is loaded into register H. For example, LHLD 2500H will load
the content of the memory location 2500 (H) into register L. The content of the
memory location 2501 (H) is loaded into register H.

SHLD addr 16Bit

(Store H – L pair direct)

[addr] [L], [addr+1][H]. States : 16. Flags. None, Addressing: direct. Machine
cycles: 5

The content of register L is stored in the memory location whose address is

specified by the 2nd and 3rd bytes of the instruction. The content of register H
is stored in the next memory location. For example, SHLD 2500 H will store the
content of register L in the memory location 2500 H. The content of register H
is stored in the memory location 2501 H.

LDAX rp

(Load Accumulator Indirect)

[A] [[rp]]. States 7, Flags; none. Addressing: register indirect. Machine cycles
2. The content of the memory location, whose address is in the register pair rp,
is loaded into the accumulator. For example LDAX B will load the content of
the memory location, whose address is in the B-C pair, into the accumulator.
This instruction is used only for B-C and D-E register pairs.

XCHG

(Exchange the contents of H – L with D-E pair)

[H–L][D-E] States: 4. Flags: none Addressing register. Machine cycles 1.
The contents of H-L pair are exchanged with contents of D-E pair.

Arithmetic Group:

ADD r. (Add register to accumulator)

[A] [A] +[r] States: 4 Flags: all. Addressing register. Machine cycles 2.

The content of register r is added to the content of the accumulator. The sum
is placed in the accumulator.

ADC M. (Add memory content with carry to accumulator)

[A] [A] + [H-L]. States: 7. Flags: all. Addressing: indirect. Machine cycles 2.The
Data stored in H-L register pair is added to the content of the accumulator.
The instruction is 1 byte. The data stored in the address specified by H –L
register pair is added to content of the accumulator along with the Carry Flag.
The sum is placed in the accumulator. Previous Carry Flag is reset. In code form
the instruction is written as 8E.

SUB r. (Subtract register from accumulator)

[A] [A] – [r], States: 4 Flags: all. Addressing: register. Machine cycles:1.

The content of register r is subtracted from the content of the accumulator,

and the result is placed in the accumulator.

SUB M. (Subtract memory from accumulator)

[A] [A] – [[H-L]]. States: 7. Flags all. Addressing : reg. indirect Machine cycles
: 2 The content of the memory location addressed by H-L pair is subtracted
from the content of the accumulator. The result is placed in the accumulator.

SBB r. (Subtract register from accumulator with borrow).

[A] [A] – [r] – [CS]. States: 4. Flags all. Addressing : register. Machine cycles:1.

The content of register r and carry status are subtracted from the content of
the accumulator. The result is placed in the accumulator. Carry Flag is reset.

SBB M. (Subtract memory from accumulator with borrow).

[A] [A] – [[H-L]] – [CS]. States 7. Flags : all. Addressing: reg. indirect. Machine
cycles : 2 The content of the memory location addressed by H-L pair and carry
status are subtracted from the content of the accumulator. The result is placed
in the accumulator.

SUI data. (Subtract immediate data from accumulator)

[A] [A]-data. States 7. Flags: all. Addressing: immediate. Machine cycles: 2.

The 2nd byte of instruction is data. It is subtracted from the content of the
accumulator. The result is placed in the accumulator. For example, the
instruction SUI 05 will subtract 05 from the content of the accumulator and
place the result in the accumulator. In the code form the above instruction is
written as D6, 05.

SBI data. (Subtract immediate data from accumulator with borrow)

[A] [A] – data – [CS]. States : 7 Flags: all. Addressing: immediate. Machine
cycles 2.The data and carry status are subtracted from the content of the
accumulator. The result is placed in the accumulator. Carry Flag is reset.

INR r. (Increment register content)

[r][r] + 1. States 4. Flags all except carry flag. Addressing : register, Machine
cycle : 1.The content of register r is incremented by one. All flags except CS are
affected.

INR M. (Increment memory content)

[[H-L]] [[H-L]] +1. States : 10 Flags: all except carry flag. Addressing: reg,
indirect.Machine cycles 3.The content of the memory location addressed by H
– L pair is incremented by one. All flags except CS are affected.

DCR r. (Decrement register content)

[r] [r] – 1. States: 4. Flags: all except carry flag, Addressing: register. Machine
cycles: 1. The content of register r is decremented by one. All flags except CS
are affected.

DCR M. (Decrement memory content)

[[H-L]] [[H-L]] – 1. States: 10. Flags: all except carry flag. Addressing reg.
indirect. Machine cycles: 3. The content of the memory location addressed by
H-L pair is decremented by one. All flags except CS are affected.

INX rp. (Increment register pair)

[rp][rp]+1. States: 6, Flags: none, Addressing : register. Machine cycles: 1

The content of the register pair rp is incremented by one. No flag is affected.

DCX rp. (Decrement register pair)

[rp][rp]-1. States 6. Flags: none. Addressing: register. Machine cycles 1.

The content of the register pair rp is decremented by one. No flag is affected.

DAA (Decimal adjust accumulator)

States: 4 Flags: all. Machine cycle: 1

The instruction DAA is used in the program after ADD, ADI, ACI, ADC, etc
instructions. After the execution of ADD, ADC, etc instructions the result is in
hexadecimal and it is placed in the accumulator. The DAA instruction operates
on this result and gives the final result in Binary Coded Decimal (BCD) system.
It uses carry and auxiliary carry for decimal adjustment. 6 is added to 4 LSBs of
the content of the accumulator if their value lies in between A and F or the AC
flag is set to 1. Similarly, 6 is also added to 4 MSBs of the content of the
accumulator if their value lies in between A and F or the CS flag is set to 1. All
status flags are affected. When DAA is sued data should be in decimal
numbers.

Logical Group:
The instructions of this group perform AND, OR, EXCLUSIVE-OR, EXCLUSIVE-
OR operations; compare, rotate or take complement of data in register or
memory.
ANA r. (AND memory with content of any register)

[A][A]  [r]. States: 4. Flags: all. Addressing. reg. indirect. Machine cycles
1.The content of the register ‘r’ is AND ed with the accumulator. The result is
placed in the accumulator. All status flags are affected. The CS flag is set to 0
and AC to 1.

ANA M. (AND memory with accumulator)

[A][A]  [[H-L]]. States: 7. Flags all, Addressing: reg. indirect. Machine cycles:
2. The content of the memory location addressed by H-L pair is AND ed with
the accumulator. The result is placed in the accumulator. All status flags are
affected. The CS flag is set to 0 and AC to 1.

ANI data. (AND immediate data with accumulator)

[A][A]  data States : 7. Flags all, Addressing: reg. indirect. Machine cycles: 2

The 2nd byte of the instruction is data, and it is ANDed with the content of the
accumulator. The result is placed in the accumulator. The CS flag is set to 0 and
AC to 1.

ORA r. (OR register with accumulator)

[A] [A]  [r] States 4. Flags. All. Addressing: register. Machine cycles 1.

The content of register r is OR with the content of the accumulator. The result
is placed in the accumulator. All status flags are affected. Carry and auxiliary
carry are cleared i.e. the CS and AC flags are set to 0.

ORA M. (OR memory with accumulator)

[A][A] [[H-L]]. States : 7. Flags all. Addressing register. Machine cycles 2.

The content of the memory location addressed by H-L pair is OR with the
content of the accumulator. All status flags are affected. Carry and auxiliary
carry are cleared i.e. the CS and AC flags are set to 0.

ORI data. (OR immediate data with accumulator)

[A][A]  data. States 7. Flags: all. Addressing. immediate. Machine cycles 2.

The 2nd byte of the instruction is data, and it is OR with the content of the
accumulator. The result is placed in the accumulator. All status flags are
affected. The CS and AC flags are set 0.

XRA r. (EXCLUSIVE-OR register with accumulator)

[A][A] [r] States 4. Flags: all. Addressing: register. Machine cycles : 1.

The content of register r is EXCLUSIVE – Ored with the content of the

accumulator. The result is placed in the accumulator. All status flags are
affected. The CS and AC flags are set to 0.

XRA M. (EXCLUSIVE – OR memory with accumulator)

[A][A] [[H-L]] States 7. Flags: all. Addressing: register. Machine cycles : 2.

The content the memory location addressed by H-L pair is EXCLUSIVE – Ored
with the content of the accumulator. The result is placed in the accumulator.
All status flags are affected. The CS and AC flags are set to 0.

XRI data. (EXCLUSIVE OR immediate data with accumulator)

[A] [A] data States : 7 Flags : all Addressing immediate Machine cycles 2.

The 2nd byte of the instruction is data, and it is EXCLUSIVE – OR with the
content of the accumulator. The result is placed in the accumulator. All flags
are affected. The CS and AC flags are set to 0.

CMA. (Complement the accumulator)

[A] 1’s Complement of [A]. States 4 Flags none. Machine cycles 1. Addressing :
implicit. 1’s complement of the content of the accumulator is obtained, and
the result is placed in the accumulator. To obtain the 1’s complement of a
binary number 0 is replaced by 1, and 1 by 0. For example, one’s complement
of 1100 is 0011.

CMC r. (Complement the carry status)

[CS]1’s complement of [CS] States 4. Flags CS, Machine Cycles 1.

The status flag CS is modified. Other flags are not affected.

CMP r. (Compare register with accumulator)

[A] – [r]. States 4. Flags all. Addressing: register. Machine cycles 1.

The content of register r is subtracted from the content of the accumulator

and status flags are set according to the result of the subtraction. But the
result is discarded. The content of the accumulator remains unchanged.

CMP M. (Compare memory with accumulator)

[A] – [[H-L]] States 7. Flags all. Addressing register indirect. Machine cycles 2

The content of the memory location addressed by H – L pair is subtracted from

the content of the accumulator, and status flags are set according to the result
of the subtraction. But the result is discarded. The content of the accumulator
remains unchanged.

CPI data. (Compare immediate data with accumulator)

[A] – data. States 7. Flags: all. Addressing immediate Machine cycles 2.

The 2nd byte of the instruction is data, and it is subtracted from the content of
the accumulator. The status flags are set according to the result of
subtraction. But the result is discarded. The content of the accumulator
remains unchanged.

RLC. (Rotate accumulator left)

[An+1][An], [A0][A7],[CS][A7].

States: 4. Flags: CS. Machine cycles :1. Addressing: implicit.

The content of the accumulator is rotated left by one bit. The seventh bit of
the accumulator is moved to carry bit as well as to the zero bit of the
accumulator. Only CS flag is affected as shown in Fig.3.1.
RRC. (Rotate accumulator right)

[A7][Ao], [CS] [AO],[An][An+1]

States: 4 Flags: CS Machine cycles : 1. Addressing implicit

The content of the accumulator is rotated right by one bit. The zero bit of the
accumulator is moved to the seventh bit as well as to carry bit. Only CS flag is
affected as depicted in Fig.3.2

RAL (Rotate accumulator left through carry)

[An+1][An], [CS][A7], [A0][CS]

States: 4. Flags: CS. Machine cycles: 1. Addressing implicit.

The content of the accumulator is rotated left one bit through carry. The
seventh bit of the accumulator is moved to carry, and the carry bit is moved to
the zero bit of the accumulator. Only carry flag is affected as shown in Fig.3.3

RAR. (Rotate accumulator right through carry)

[An] [An+1], [CS][A0],[A7][CS]

States : 4 Flags: CS. Machine cycle: 1. Addressing implicit

The content of the accumulator is rotated right one bit through carry. The zero
bit of the accumulator is moved to carry, and the carry bit to the seventh bit of
the accumulator. Only CS flag is affected as shown in Fig.3.4

Branch Group:
The instructions of this group change the normal sequence of the Program.
There are two types of branch instructions: conditional and unconditional.
The conditional branch instructions transfer the program to the specified
label when certain condition is satisfied. The unconditional branch
instructions transfer the program to the specified label unconditionally.

JMP addr (label). (Unconditional jump: jump to the instruction specified by the
address).[PC]Label. States 10, Flags none. Addressing. immediate. Machine
cycles 3. Byte 2nd and byte 3rd of the instruction give the address of the label
where the program jumps. The address of the label is the address of the
memory location for next instruction to be executed. The program jumps to
the instruction specified by the address (label) unconditionally.

Conditional Jump addr (label):

After the execution of the conditional jump instruction the program jumps
to the instruction specified by the address (label) if the specified condition is
fulfilled. The program proceeds further in the normal sequence if the
specified condition is not fulfilled. The execution of a conditional jump takes
3 machine cycles: 10 states. If condition is not true, only 2 machine cycles; 7
states are required for the execution of the instruction.

JZ addr (label). (jump if the result is zero )

[PC] address (label), jump if the result is zero

[PC] address (label), jump if Z=1. States : 7/10. Flags: none. Addressing :
immediate.Machine cycles: 2/3 The program jumps to the instruction specified
by the address (label) if the result is zero (i.e. the zero status Z=1). Here the
result after the execution of the preceding instruction is under consideration.

JNZ addr (label). (Jump if the result is not zero)

[PC] address (label), jump if Z=0. States : 7/10. Flags: none. Addressing :
immediate.Machine cycles: 2/3 The program jumps to the instruction specified
by the address (label) if the result is non zero (i.e. the zero status Z=0). Here
the result after the execution of the preceding instruction is under
consideration.

JC addr (label). (jump if there is carry)

[PC] address (label), jump if CS = 1. States: 7/10. Flags: none. Addressing:

immediate. Machine cycles. 2/3. The program jumps to the instruction
specified by the address (label) if there is a carry (i.e. the carry status CS = 1).
Here the carry after the execution of the preceding instruction is under
consideration.

JNC addr (label). (jump if there is no carry)

[PC] address (label) , jump if CS = 0. States: 7/10. Flags none. Addressing:

immediate. Machine cycles : 2/3. The program jumps to the instruction
specified by the address (label) if there is no carry (i.e. the carry states CS = 0)

JP addr (label). (Jump if the result is plus)

[PC] address (label), jump if S = 0. States : 7/10. Flags: none Addressing :

immediate. Machine cycles: 2/3.The program jumps to the instruction
specified by the address (label) if the result is positive.

JM addr (label). (Jump if the result is minus)

[PC] address (label), jump if S = 1. States : 7/10. Flags: none. Addressing:
immediate.Machine cycles : 2/3.If the result is negative the program jumps to
the instruction specified by the address (label).

JPE addr (label). (Jump if even parity)

[PC] address (label), (jump if even parity P = 1)

Addressing: immediate. Machine cycles: 2/3.If the result contains even number
of 1s, the program jumps to the instruction specified by the address (label).

JPO addr (label) (Jump if odd parity)

[PC] address (label), jump if odd pairty; the parity status P = O, States: 7/10,
Flags: none, Addressing: immediate, Machine cycles 2/3. If the result contains
odd number of 1s, the program jumps to the instruction specified by the
address (label).

CALL addr (label). (Unconditional CALL: call the subroutine identified by the
operand)

[[SP] – 1] [PCH] , [[ISP]]-2][PCL],

[PC]addr (label), [SP][SP]-2

States : 9/18. Flags: none. Addressing; immediate/reg. indirect. Machine

cycles. 2/5. If the condition is true and program calls the specified subroutine,
the execution of a conditional call instruction takes 5 machine cycles; 18 states.
If condition is not true, only 2 machine cycles; 9 states are required for the
execution of the instruction.

(i) CC addr (label) Call subroutine if carry status CS = 1

(ii) CNC addr (label) Call subroutine if carry status CS = 0
(iii) CZ addr (label) Call subroutine if the result is zero; the zero
status Z =1
(iv) CNZ addr (label) Call subroutine if the result is not zero; the zero
status Z =0
(v) CP addr (label) Call subroutine if the result is plus; the sign
status S = 0
 (vi) CM addr (label) Call subroutine if the result is minus; the sign
status S =1
(vii) CPE addr (label) Call subroutine if even parity; the parity status
P =1
(viii) CPOaddr (label) Call subroutine if the odd parity; the parity
status P =0

RET. (Return from subroutine)

[PCL][[SP]], [PCH] [[sp]+1], [SP] [SP]+2

States : 10. Flags: none. Addressing: reg. indirect. Machine cycles 3.

RET instruction is used at the end of a subroutine. Before the execution of a

subroutine the address of the next instruction of the main program is saved in
the stack. The execution of RET instruction brings back the saved address from
the stack to the program counter. The content of the stack pointer is
incremented by 2 to indicate the new stack top. Then the program jumps to
the instruction of the main program next to CALL instruction which called the
subroutine.

Conditional Return

[PCL] [[SP]], [PCH][[SP]]+1], [SP] [SP] +2

States 6/12. Flags none. Addressing: reg. indirect. Machine cycles. 1/3. If the
condition is true and the program returns from the subroutine, the execution
of a conditional return instruction takes 3 machine cycles, 12 states. If
condition is not true only 1 machine cycle, 6 states are required.

RC Return from subroutine if carry status CS = 1

RNC Return from subroutine if carry status CS = 0
RZ Return from subroutien if the result is zero, the zero status Z = 1.
RNZ Return from subroutien if the result is zero, the zero status Z = 0.
RP Return from subroutine if the result is plus; the sign status S = 0
RM Return from subroutine if the result is plus; the sign status S = 1
RPE Return from subroutine if even parity, the parity status P =1.
RPO Return from subroutine if even parity, the parity status P =0.
RST n (Restart)

[[SP]] – 1] [PCH], [[SP] – 2] [PCL], [SP] [SP] – 2] [PC]  8 times n

States : 12. Flags: none. Addressing: reg. indirect. Machine cycles : 3.

Restart are equivalent to one-byte CALL instructions to one of the eight

memory locations on page 0. The instructions are generally used in conjunction
with interrupts and inserted using hardware. However, these can be used as
software instructions in a program to transfer program execution to one of the
eight locations.

PCHL (Jump to address specified by H-L pair)

[PC][H-L], [PCH], [H], [PCH] [L]

States: 6 Flags: none. Addressing: register Machine cycle: 1.The contents of H-L
pair are transferred to program counter. The contents of register H are moved
to high order 8 bits of register PC. The contents of register L are transferred to
low order 8 bits of register PC.

Stack, I/O and Machine Control Group:

IN port-address. (Input to accumulator from I/O port)

[A][Port]. States: 10 Flags: none. Addressing direct. Machine cycles 3

The data available on the port is moved to the accumulator . After instruction
IN, the address of the port is specified. The 2nd byte of the instruction contains
the address of the port. The address of a port is an 8-bit address. For
example, IN 01. The address of the port B of a microprocessor kit is 01 where
the processor is interfaced with a peripheral interfacing device 8255.

OUT port-address. (Output from accumulator to I/O port)

[Port][A]. States 10. Flags none. Addressing: direct. Machine cycles: 3.

The content of the accumulator is moved to the port specified by its address.
After the OUT instruction, the port address is specified. The 2nd byte of the
instruction contains the address of the port. For example OUT 00. The address
of the port A of a microprocessor kit is 00 where the processor is interfaced
with a peripheral interfacing device 8255.

PUSH rp. (Push the content of register pair to stack)

[[SP] – 1] [rh], [[SP] –2] [rl], [SP][SP] –2

States: 12. Flags none. Addressing reg. indirect. Machine cycles 3.The content
of the register pair rp is pushed into the stack. The content of the register SP is
decremented by 2 to indicate new stack top.

PUSH PSW. (PUSH processor status Word)

[[SP] – 1] [A], [[SP] – 2]PSW (Program Status Word),[SP] [SP] –2

Status: 12 Flags: none. Addressing: reg. indirect, Machine cycles 3

The content of the accumulator is pushed into the stack. The contents of
status flags are also pushed into the stack. The content of the register SP is
decremented by 2 to indicate new stack top.

POP rp. (Pop the content of register pair, which was saved, from the stack)

[rl][[SP]], [rh][[SP] +1], [SP][SP] +2

Status: 10. Flags: none. Addressing: reg. indirect. Machine cycles: 3.

The content of the register pair, which was saved earlier is moved from the
stack to the register pair.

POP PSW. (Pop Processor Status Word)

PSW[[SP]], [rh][[SP]+1, [SP][SP]+2

States 10. Flags: none. Addressing: reg. indirect. Machine cycles: 3. The process
status word which was saved earlier during the execution of the program is
moved from the stack to PSW. The content of the accumulator, which was also
saved, is moved from the stack to the accumulator.

HLT (Halt)

States: 5 or more. Flags: none. Machine cycle: 2 or more.The execution of the

instruction HLT stops the microprocessor. The register and status flags remain
unaffected. An interrupt or reset is necessary to exit from the Halt state.

XTHL. (Exchange stack-top with H-L)

[L]  [[SP]], [H]  [[SP]]+1]

States: 16. Flags: none. Addressing: register indirect. Machine cycles: 5

The content of the register L are exchanged with the byte of the stack-top. The
contents of the H register exchanged with the byte below the stack-top.

SPHL (Move the contents of H-L pair to stack pointer)

[H-L]→[SP].

States : 6. Flags none. Addressing: register. Machine cycle: 1. The contents of

H-L pair are transferred to the SP register.

EI. (Enable interrupts)

States: 4, Flags: none, Machine cycle 1. When this instruction is executed the
Interrupt Enable Flag is set and all interrupts are enabled.

DI (Disable Interrupt)

States:4. Flags: none, Machine cycle:1 When this instruction is executed the
Interrupt Enable Flag is reset and all interrupts are disabled.

NOP (No operations)

States: 4. Flags: none. Machine Cycle: 1 No operation is performed when this

instruction is executed. The registers and fags remain unaffected. This
instruction is used to fill in time delays.
 : PROGRAMMING 8085:

A microprocessor executes instructions given by the user. Instructions should

be in a language known to the microprocessor. Microprocessor understands
the language of 0’s and 1’s only. This language is called Machine Language.

Assembly Language of 8085: It uses English like words to convey the

action/meaning called as MNEMONICS.
For e.g.: MOV, ADD, SUB
Note: Assembly language is specific to a given processor.
For e.g. assembly language of 8085 is different than that of Motorola 6800
microprocessor. Microprocessor cannot understand a program written in
Assembly language.
A software program known as Assembler is used to convert an Assembly
language program to a machine language program.

To write a Assembly Language Program following steps are to be followed:

1. Analyze the problem
2. Develop program Logic
3. Write an Algorithm
4. Make a Flowchart
5. Write program Instructions using Assembly language of 8085

In Flowchart, following symbols are used:

Decision Contin
Process/ Start or End of a
making uation
Operation Program
to a

Programming Techniques in Microprocessor 8085:

We have seen the instruction set of 8085 and some simple assembly language
programs using it. We know that, the program is an implementation of certain
logic by executing group of instructions. To implement program logic we need
to take help of some common Programming Techniques in Microprocessor
8085 such as looping, counting, indexing and code conversion.
In this section, we are going to study how to implement these Programming
Techniques in Microprocessor 8085 assembly language and some
programming examples using them.

Looping, Counting and Indexing:

Before going to implement these Programming Techniques in Microprocessor

8085, we get conversant with these techniques and understand the use of
them.

Looping: In this Programming Techniques in Microprocessor 8085, the

Program is instructed to execute certain set of instructions repeatedly to
execute a particular task number of times. For example, to add ten numbers
stored in the consecutive memory locations we have to perform addition ten
times.

Counting: This technique allows programmer to count how many times the
instruction/set of instructions are executed.

Indexing: This Programming Techniques in Microprocessor 8085 allows

programmer to point or refer the data stored in sequential memory locations
one by one. Let us see the program loop to understand looping, counting and
indexing.

The Program loop is the basic structure which forces the processor to repeat a
sequence of instructions. Loops have four sections.

• Initialization section.
• Processing section.
• Loop control section
• Result section.

1. The initialization section establishes the starting values of

• loop counters for counting how many times loop is executed,

• address registers for indexing which give pointers to memory locations
and other variables

2. The actual data manipulation occurs in the processing section. This is

the section which does the work.
 3. The loop control section updates counters, indices (pointers) for the
next iteration.
4. The result section analyzes and stores the results.

Note: The processor executes initialization section and result section only
once, while it may execute processing section and loop control section many
times. Thus, the execution time of the loop will be mainly dependent on the
execution time of the processing section and loop control section. The
flowchart 1 shows typical Program loop. The processing section in this
flowchart is always executed at least once. If you interchange the position of
the processing and loop control section then it is possible that the processing
section may not be executed at all, if necessary.

Programming Examples
ADDITION OF TWO 8 BIT NUMBERS

Algorithm:

1) Start the program by loading the first data into accumulator.

2) Move the data to a register, say B.
3) Get the second data and load into Accumulator.
4) Add the two register contents.
5) Check for carry.
6) Store the value of sum and carry in memory location.
7) Terminate the program.

Program:
MVI C, 00 : Initialize C register to 00
LDA 4150 : Load the 1st data to Accumulator
MOV B, A : Move the content of Accumulator to B
LDA 4151 : Load the 2nd data to Accumulator
ADD B : Add the value of register B with A
JNC LOOP : Jump on no carry to Label LOOP
INR C : Increment value of register C
LOOP: STA 4152 : Store the value of Accumulator (SUM)
MOV A, C : Move content of register C to Acc.
STA 4153 : Store the value of Acc. (CARRY)
HLT : Halt the program
 Data 1
Illustration: Before execution: 4150
4151 Data 2

SUM
After execution: 4152
4153 CARRY

Flowchart:
 SUBTRACTION OF TWO 8 BIT NUMBERS

Algorithm:

1) Start the program by loading the first data into Accumulator.

2) Move the data to a register, say B.
3) Get the second data and load into Accumulator.
4) Subtract the two register contents.
5) Check for Borrow (by checking the status of Carry Flag).
6) If Borrow is present take 2’s complement of Accumulator.
7) Store the value of Borrow in memory location.
8) Store the difference value present in Accumulator in memory location.
9) Terminate the program.
Flowchart:
Program:
MVI C, 00 : Initialize C register to 00
LDA 4150 : Load the 1st data to Accumulator
MOV B, A : Move the content of Accumulator to B
LDA 4151 : Load the 2nd data to Accumulator
SUB B : Subtract the value of register B from A
JNC LOOP : Jump on no carry to Label LOOP
CMA : Complement Accumulator contents
INR A : Increment value in Accumulator
INR C : Increment value of register C
LOOP: STA 4152 : Store the value of Accumulator (DIFFERENCE)
MOV A, C : Move content of register C to Acc.
STA 4153 : Store the value of Acc. (BORROW)
HLT : Halt the program

Data 1
Illustration: Before execution: 4150
4151 Data 2

DIFFERENCE
After execution: 4152
4153 BORROW

MULTIPLICATION OF TWO 8 BIT NUMBERS

Algorithm:
1) Start the program by loading the first data into accumulator.
2) Move the data to a register, say B.
3) Get the second data and load into Accumulator.
4) Move the data to another register, C
5) Initialize the Accumulator with zero value
6) Initialize another register D with zero value which will store the Carry.
7) Add the content of B register with Accumulator content.
8) Check for carry.
9) Increment D (Carry) by 1 if carry present.
10) Decrement the 2nd data stored in Counter register C and repeat from
step 7, till Counter value decreases to zero.
11) Store the multiplied value and carry in memory location.
12) Terminate the program.
Flowchart: Draw it yourself
Program:
LDA 4150 : Load the 1st data to Accumulator
MOV B, A : Move the content of Accumulator to B
LDA 4151 : Load the 2nd data to Accumulator
MOV C, A : Move the content of Accumulator to B
MVI A, 00 : Initialize Accumulator with 00
MVI D, 00 : Initialize register D (Carry) with 00
REPEAT ADD B : Add the value of register B with A
JNC LOOP : Jump on no carry to Label LOOP
INR D : Increment value of register D if Carry present
LOOP DCR C : Decrement value of Counter register C
JNZ REPEAT : Repeat addition until Counter becomes zero
STA 4152 : Store the value of Accumulator (SUM)
MOV A, D : Move content of register D to Acc.
STA 4153 : Store the value of Acc. (CARRY)
HLT : Halt the program

Illustration: Before execution: 4150 Data 1

4151 Data 2

After execution: 4152 RESULT

4153 CARRY

DIVISION OF TWO 8 BIT NUMBERS

Algorithm:

1) Start the program by initializing H-L reg. pair with the address of
memory location.
2) Move the data to a register, say B.
3) Initialize reg. C with 00 (H) which will be used to store the ‘Quotient’.
4) Get the second data and load into Accumulator.
5) Compare the two numbers to check for carry.
6) Subtract the two numbers.
7) Increment the value of C reg.
8) Check whether repeated subtraction is over and store the value of
Quotient and Remainder in memory location.
9) Terminate the program.
Flowchart: Draw it yourself
Program:
LXI H, 4150 : Load H-L reg. pair with memory address of 1st data
MOV B, M : Get the Dividend in reg. B
MVI C, 00 : Initialize reg. C with 00(H) for ‘Quotient’
INX H : Load H-L reg. pair with memory address of 2nd data
MOV A, M : Get the Divisor in accumulator A
NEXT: CMP B : Compare the two data
JC LOOP : Jump on carry to Label LOOP
SUB B : Subtract the value of reg. A from reg. B
INR C : Increment value of register C
JMP NEXT : Jump to NEXT
LOOP STA 4152 : Store the remainder in Memory
MOV A, C : Get the ‘Quotient’ in accumulator A
STA 4153 : Store the ‘Quotient’ in Memory Location
HLT : Terminate the program

Illustration: Before execution: 4150 Data 1

4151 Data 2

After execution: 4152 REMAINDER

4153 QUOTIENT
 BCD ARITHMETIC

Problem: A 4-digit BCD number is stored in memory locations 9000(H)

and 9001(H) and another in memory locations 9002(H) and 9003(H).
Add the two BCD numbers and store the result in memory locations
9004(H) and 9005(H). Ignore the carry after the 16th bit.

Algorithm:
Let us assume, [HL] = 3629 & [DE] = 4738
Step1: Addition of two lower digits of the two numbers.
29 + 38 = 61 and auxiliary carry flag = 1, i.e. Auxiliary carry flag is set.
So add 06 (Decimal Adjust Accumulator) with the result to get actual
BCD result for the lower two digits, which will be: 61+06 = 67
Step2: Addition of two higher digits of the two numbers.
36+47+0 (carry of LSB) = 7D
Lower nibble is greater than 9. So add 06 with it to get actual BCD value.
7D+06 = 83 (Decimal Adjust Accumulator)
Result = 8367

Flowchart: See the next page

Program:
LHLD 9000(H) : Load the 1st 4 digit of BCD number in HL reg. pair
XCHG : Move it to DE
LHLD 9002(H) : Load the 2nd 4 digit of BCD number in HL reg. pair
MOV A, L : Move the two lower order digits of the 2nd no. in A
ADD E : Add the two lower order digits of the two no.
DAA : Adjust the result to make it a valid BCD no.
STA 9004(H) : Store the partial result in memory location
MOV A, H : Load the two higher order digits of 2nd no. in A
ADC D : Add the 2 higher order digits of the 2 no. with previous carry
DAA : Adjust the result to make it a valid BCD no.
STA 9005(H) : Store the partial result in memory location
HLT : Terminate the program.
Flowchart: Addition of two 4 digit BCD numbers.
What is Subroutine in Assembly Language?

A subroutine is a small program written separately from the main program to

perform a particular task that you may repeatedly require in the main
program. Essentially, the concept of a subroutine is that it is used to avoid the
repetition of smaller parts of a program.

Subroutines are written separately and are stored in a memory location that is
different from the main program. You can call a subroutine multiple times
from the main program using a simple CALL instruction.

What are the advantages of using subroutines?

• Subroutines avoid the repetition of instructions.

• They give an aspect of modular programming to the entire program.
• Improves efficiency by reducing the size of the memory needed to store
the program.
 HEX TO ASCII CONVERSION

Aim: To convert given Hexadecimal number into its equivalent ASCII number
using 8085 instructions.

Algorithm:

1. Load the given data in A reg. and move to B reg.

2. Mask the upper nibble of the Hexadecimal number in A reg.
3. Call subroutine to get ASCII of lower nibble.
4. Store it in memory.
5. Move B reg. to A reg. and mask the lower nibble.
6. Rotate the upper nibble to lower nibble position.
7. Call subroutine to get ASCII of upper nibble.
8. Store it in memory.
9. Terminate the program.

Program:

LDA 4200 : Get Hex Data

MOV B, A
ANI 0F : Mask upper nibble
CALL SUB1 : Get ASCII code for lower nibble
STA 4201
MOV A, B
ANI F0 : Mask lower nibble
RLC
RLC
RLC
RLC
CALL SUB1 : Get ASCII code for upper nibble
STA 4202
HLT
SUB1: CPI 0A
JC SKIP
ADI 07
SKIP: ADI 30
RET
Illustration: Input 4200(H): E4 (Hex Data)
Output 4201(H): 34(ASCII code for 4)
4202 (H): 45(ASCII code for E)
 TIME DELAY GENERATION:

In this section we will see how to generate the time delay using 8085
programs. The delay will be used in different places to simulate clocks, or
counters or some other area.

When the delay subroutine is executed, the microprocessor does not execute
other tasks. For the delay we use the instruction execution times. Executing
some instructions in a loop, the delay is generated. There are some methods of
generating delays. These methods are as follows.

• Using NOP instructions

• Using 8-bit register as Counter
• Using 16-bit register pair as Counter.

Using NOP Instructions:

One of the main usage of NOP instruction is in delay generation. The NOP
instruction takes four clock pulses for fetching, decoding and executing. If the
8085 MPU is working on 6MHz clock frequency, then the internal clock
frequency is 3MHz. So from that we can easily determine that each clock
period is 1/3 of a microsecond. So the NOP will be executed in 1/3 * 4 =
1.333µs. If we use the entire memory with NOP instruction, then 64K NOP
instructions will be executed. Then the overall delay will be 216 * 1.333µs =
87359.488µs, though the time is not so large and the program size is also large.
So this type of NOP instruction can be used to generate a short time delay for
few milliseconds.

Using 8-bit register as counter:

Counter is another approach to generate a time delay. In this case the program
size is smaller. So in this approach we can generate more time delay in less
space. The following program will demonstrate the time delay using 8-bit
counter.

Program:

MVI B, FFH Load FF (H) data as ‘Count Value’ in reg. B

LOOP: DCR B Decrement the content of reg. B by 1
JNZ LOOP Repeat above instruction till content of B becomes 0
RET Return to the main program
Here the first instruction will be executed once, it will take 7 T-states. DCR B
instruction takes 4 T-states. This will be executed 255 (FF) times. The JNZ
instruction takes 10 T-states when it jumps (It jumps 254 times), otherwise it
will take 7 T-States. And the RET instruction takes 10 T-States.

7 + ((4*255) + (10*254)) + 7 + 10 = 3584. So the time delay will be 3584 * 1/3µs

= 1194.66µs. So when we need some small delay, then we can use this
technique with some other values in the place of FF (H).

This technique can also be done using some Nested Loops to get larger delays.
The following code is showing how we can get some delay with one loop inside
another loop.

Program:

MVI B, FFH
Loop1: MVI C, FFH
Loop2: DCR C
JNZ Loop2
DCR B
JNZ Loop1
RET

From this block, if we calculate the delay, it will be nearly 305µs delay. It
extends the time of delay.

Using 16-bit register-pair as counter:

Instead of using 8-bit Counter, we can do that kind of task using 16-bit register
pair as 16 bit Counter. Using this method more time delay can be generated as
we use larger data as ‘Count Value’. As an example say, FFFF (H) instead of FF
(H). This method can be used to get more than 0.5 seconds delay.

------------------------------------------- END -----------------------------------------------