TPA3123D2

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25-W STEREO CLASS-D AUDIO POWER AMPLIFIER

Check for Samples: TPA3123D2

1FEATURES APPLICATIONS
•
2 25-W/ch into a 4-Ω Load from a 27-V Supply • Televisions
• 20-W/ch into a 4-Ω Load from a 24-V Supply
• Operates from 10 V to 30 V
DESCRIPTION
• Efficient Class-D Operation Eliminates Need The TPA3123D2 is a 25-W (per channel) efficient,
for Heat Sinks Class-D audio power amplifier for driving stereo
speakers in a single-ended configuration or a mono
• Four Selectable, Fixed-Gain Settings speaker in a bridge-tied-load configuration. The
• Internal Oscillator (No External Components TPA3123D2 can drive stereo speakers as low as 4 Ω.
Required) The efficiency of the TPA3123D2 eliminates the need
• Single-Ended Analog Inputs for an external heat sink when playing music.
• Thermal and Short-Circuit Protection With The gain of the amplifier is controlled by two gain
Auto Recovery select pins. The gain selections are 20, 26, 32,
36 dB.
• Space-Saving Surface-Mount 24-Pin TSSOP
Package TPA3120D2 The patented start-up and shut-down sequences
• Pin-to-Pin compatible with TPA3120D2 minimize pop noise in the speakers without additional
circuitry.
• Advanced Power-Off Pop Reduction

SIMPLIFIED APPLICATION CIRCUIT

TPA3123D2
1 mF
0.22 mF
Left Channel LIN BSR
22 mH 470 mF
Right Channel RIN ROUT
1 mF 0.68 mF
PGNDR

PGNDL 0.68 mF
1 mF
BYPASS LOUT
22 mH 470 mF
AGND BSL
0.22 mF

PVCCL 10 V to 30 V
10 V to 30 V AVCC
PVCCR

VCLAMP
Shutdown
SD 1 mF
Control

Mute Control MUTE

GAIN0

GAIN1
} 4-Step Gain
Control

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 System Two, Audio Precision are trademarks of Audio Precision, Inc.
PRODUCTION DATA information is current as of publication date. Copyright © 2007–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

PWP (TSSOP) PACKAGE

(TOP VIEW)

PVCCL 1 24 PGNDL
SD 2 23 PGNDL
PVCCL 3 22 LOUT
MUTE 4 21 BSL
LIN 5 20 AVCC
RIN 6 19 AVCC
BYPASS 7 18 GAIN0
AGND 8 17 GAIN1
AGND 9 16 BSR
PVCCR 10 15 ROUT
VCLAMP 11 14 PGNDR
PVCCR 12 13 PGNDR

Table 1. PIN FUNCTIONS

PIN
24-PIN I/O/P DESCRIPTION
NAME
(PWP)
Shutdown signal for IC (low = disabled, high = operational). TTL logic levels with compliance to
SD 2 I
AVCC
RIN 6 I Audio input for right channel
LIN 5 I Audio input for left channel
GAIN0 18 I Gain select least-significant bit. TTL logic levels with compliance to AVCC
GAIN1 17 I Gain select most-significant bit. TTL logic levels with compliance to AVCC
Mute signal for quick disable/enable of outputs (high = outputs switch at 50% duty cycle, low =
MUTE 4 I
outputs enabled). TTL logic levels with compliance to AVCC
BSL 21 I/O Bootstrap I/O for left channel
PVCCL 1, 3 P Power supply for left-channel H-bridge, not internally connected to PVCCR or AVCC
LOUT 22 O Class-D 1/2-H-bridge positive output for left channel
PGNDL 23, 24 P Power ground for left-channel H-bridge
VCLAMP 11 P Internally generated voltage supply for bootstrap capacitors
BSR 16 I/O Bootstrap I/O for right channel
ROUT 15 O Class-D 1/2-H-bridge negative output for right channel
PGNDR 13, 14 P Power ground for right-channel H-bridge.
PVCCR 10, 12 P Power supply for right-channel H-bridge, not connected to PVCCL or AVCC
AGND 9 P Analog ground for digital/analog cells in core
AGND 8 P Analog ground for analog cells in core
Reference for preamplifier inputs. Nominally equal to AVCC/8. Also controls start-up time via
BYPASS 7 O
external capacitor sizing.
AVCC 19, 20 P High-voltage analog power supply. Not internally connected to PVCCR or PVCCL
Connect to ground. Thermal pad should be soldered down on all applications to secure the
Thermal pad Die pad P
device properly to the printed wiring board.

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ABSOLUTE MAXIMUM RATINGS

(1)
over operating free-air temperature range (unless otherwise noted)
VALUE UNIT
VCC Supply voltage AVCC, PVCC –0.3 to 36 V
VI Logic input voltage SD, MUTE, GAIN0, GAIN1 –0.3 to VCC + 0.3 V
VIN Analog input voltage RIN, LIN –0.3 to 7 V
Continuous total power dissipation See the Thermal Information table
TA Operating free-air temperature range –40 to 85 °C
TJ Operating junction temperature range –40 to 150 °C
Tstg Storage temperature range –65 to 150 °C
RL Load resistance (minimum value) 3.2 Ω
Human-body model (all pins) ±2 kV
ESD Electrostatic Discharge
Charged-device model (all pins) ± 500 V

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operations of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

THERMAL INFORMATION
TPA3123D2
THERMAL METRIC (1) (2) PWP UNITS
24 PINS
qJA Junction-to-ambient thermal resistance 30.2
qJCtop Junction-to-case (top) thermal resistance 27.8
qJB Junction-to-board thermal resistance 6.8
°C/W
yJT Junction-to-top characterization parameter 0.3
yJB Junction-to-board characterization parameter 32.1
qJCbot Junction-to-case (bottom) thermal resistance 0.5

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.

RECOMMENDED OPERATING CONDITIONS

MIN MAX UNIT
VCC Supply voltage PVCC, AVCC 10 30 V
VIH High-level input voltage SD, MUTE, GAIN0, GAIN1 2 V
VIL Low-level input voltage SD, MUTE, GAIN0, GAIN1 0.8 V
SD, VI = VCC, VCC = 30 V 125
IIH High-level input current MUTE, VI = VCC, VCC = 30 V 125 mA
GAIN0, GAIN1, VI = VCC, VCC = 24 V 125
SD, VI = 0, VCC = 30 V 1
IIL Low-level input current MUTE, VI = 0 V, VCC = 30 V 1 mA
GAIN0, GAIN1, VI = 0 V, VCC = 24 V 1
TA Operating free-air temperature –40 85 °C

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DC CHARACTERISTICS
TA = 25°C, VCC = 24 V, RL = 4 Ω (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Class-D output offset voltage
| VOS | (measured differentially in BTL mode as shown in VI = 0 V, AV = 36 dB 7.5 50 mV
Figure 30)
V(BYPASS) AVCC/
Bypass output voltage No load V
8
ICC(q) SD = 2 V, MUTE = 0 V, No
Quiescent supply current 23 37 mA
load
ICC(q) Quiescent supply current in mute mode MUTE = 0.8 V, No load 23 mA
ICC(q) Quiescent supply current in shutdown mode SD = 0.8 V , No load 0.39 1 mA
rDS(on) Drain-source on-state resistance 200 mΩ
GAIN0 = 0.8 V 18 20 22
GAIN1 = 0.8 V
GAIN0 = 2 V 24 26 28
G Gain dB
GAIN0 = 0.8 V 30 32 34
GAIN = 2 V
GAIN0 = 2 V 34 36 38
Mute Attenuation VI = 1 Vrms –82 dB

AC CHARACTERISTICS
TA = 25°C, VCC = 24 V, RL = 4Ω (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCC = 24, Vripple = 200 mVPP 100 Hz –48
ksvr Supply ripple rejection Gain = 20 dB dB
1 kHz –52
VCC = 24 V, RL = 4 Ω, f = 1 kHz 16
Output power at 1% THD+N
VCC = 24 V, RL = 8 Ω, f = 1 kHz 8
PO W
VCC= 24 V, RL = 4 Ω, f = 1 kHz 20
Output power at 10% THD+N
VCC = 24 V, RL = 8 Ω, f = 1 kHz 10
RL = 4 Ω, f = 1 kHz, PO = 10 W 0.08%
THD+N Total harmonic distortion + noise
RL = 8 Ω, f = 1 kHz, PO = 5 W 0.08%
85 mV
Vn Output integrated noise floor 20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB
–80 dBV
Crosstalk PO = 1 W, f = 1 kHz; Gain = 20 dB –60 dB
Max output at THD+N < 1%, f = 1 kHz,
SNR Signal-to-noise ratio 99 dB
Gain = 20 dB
Thermal trip point 150 °C
Thermal hysteresis 30 °C
fOSC Oscillator frequency 230 250 270 kHz
time from mute input switches high until outputs
mute delay 120 msec
muted
Δt
time from mute input switches low until outputs
unmute delay 120 msec
unmuted

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FUNCTIONAL BLOCK DIAGRAM

BSL
AVCC AVDD PVCCL

REGULATOR
HS
+ LOUT
- VCLAMP

LS
AVDD AVDD PGNDL
LIN

SC
AVDD/2 DETECT

AGND

CONTROL
SD
BIAS
VCLAMP
THERMAL
MUTE
MUTE CONTROL

OSC/RAMP
BYPASS BYPASS

GAIN1 AV
CONTROL
GAIN0

SC
DETECT

BSR
PVCCR

HS
ROUT
-
VCLAMP
+
LS

PGNDR
AVDD
AVDD
RIN

AVDD/2

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TYPICAL CHARACTERISTICS
All tests are made at frequency = 1 kHz unless otherwise noted.
TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE
vs vs
FREQUENCY FREQUENCY
10 10
THD+N - Total Harmonic Distortion + Noise - %

THD+N - Total Harmonic Distortion + Noise - %

VCC = 18 V VCC = 24 V
RL = 4 W (SE) RL = 4 W (SE)
Gain = 20 dB Gain = 20 dB

1 1
PO = 10 W
PO = 5 W

PO = 1 W PO = 1 W
0.1 0.1

PO = 2.5 W PO = 5 W

0.01 0.01
20 100 1k 10k 20k 20 100 1k 10k 20k
f − Frequency − Hz f − Frequency − Hz
Figure 1. Figure 2.

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

vs vs
FREQUENCY OUTPUT POWER
10 10
THD+N - Total Harmonic Distortion + Noise - %
THD+N - Total Harmonic Distortion + Noise - %

RL = 4 W (SE)
VCC = 24 V
Gain = 20 dB
RL = 8 W (SE)
Gain = 20 dB VCC = 24 V

1 1 VCC = 18 V
PO = 2.5 W

VCC = 12 V

PO = 5 W
0.1 0.1

PO = 1 W

0.01
0.01
20 100 1k 10k 20k 10 m 100 m 1 10 40
f − Frequency − Hz PO − Output Power − W
Figure 3. Figure 4.

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TYPICAL CHARACTERISTICS (continued)

All tests are made at frequency = 1 kHz unless otherwise noted.
TOTAL HARMONIC DISTORTION + NOISE CROSSTALK
vs vs
OUTPUT POWER FREQUENCY
10 0
RL = 8 W (SE)
THD+N - Total Harmonic Distortion + Noise - %

VCC = 18 V
Gain = 20 dB -10 VO = 1 Vrms
RL = 4 W (SE)
VCC = 24 V -20
Gain = 20 dB
-30
1 VCC = 18 V

Crosstalk - dB
-40
VCC = 12 V -50
L to R
-60
0.1
-70

-80
R to L
-90

0.01 -100
10 m 100 m 1 10 40 20 100 1k 10k 20k
PO − Output Power − W f − Frequency − Hz
Figure 5. Figure 6.

CROSSTALK GAIN/PHASE
vs vs
FREQUENCY FREQUENCY
0 200
VCC = 18 V,
-10 VO = 1 V, Gain
20
-20 RL = 8 W, 100
Gain = 20 dB
-30
15
Crosstalk - dB

0
Gain - dB

-40

Phase - o
Phase
-50 L to R
10
-60 VCC = 24 V -100
RL = 4 W (SE)
-70 Gain = 20 dB
5
R to L Lfilt = 33 mH
-80 -200
Cfilt = 1 mF
-90 Cdc = 470 mF
0

-100 -300
20 100 1k 10k 20k 20 100 200 1k 2k 10k 20k 100k
f − Frequency − Hz f − Frequency − Hz

Figure 7. Figure 8.

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TYPICAL CHARACTERISTICS (continued)

All tests are made at frequency = 1 kHz unless otherwise noted.
GAIN/PHASE OUTPUT POWER
vs vs
FREQUENCY SUPPLY VOLTAGE
200 32
22.5 30 RL = 4 W (SE)
150 Gain = 20 dB
28
Gain
20 26
100
24

PO - Output Power - W
17.5 50 22
20 THD = 10%
Gain - dB

Phase - o
15 0 18
Phase
-50 16
12.5
VCC = 24 V 14
RL = 8 W (SE) -100 12 THD = 1%
10 Gain = 20 dB 10
Lfilt = 47 mH -150
7.5 8
Cfilt = 0.22 mF
6
Cdc = 470 mF -200
5 4
-250 2
20 100 200 1k 2k 10k 20k 100k 10 12 14 16 18 20 22 24 26 28 30
f − Frequency − Hz VSS − Supply Voltage − V
A. Dashed line represents thermally limited region.
Figure 9. Figure 10.

OUTPUT POWER EFFICIENCY

vs vs
SUPPLY VOLTAGE OUTPUT POWER
17 100
16 RL = 8 W (SE)
90
15 Gain = 20 dB
14 80
13
PO - Output Power - W

12 THD = 10% 70
18 V 24 V
Efficiency - %

11 60
10 12 V
9 50
8
40
7
6 THD = 1%
30
5
4 20
RL = 4 W (SE)
3 10 Gain = 20 dB
2
1 0
10 12 14 16 18 20 22 24 26 28 30 0 2 4 6 8 10 12 14 16 18 20

VSS - Supply Voltage - V PO − Output Power − W

Figure 11. Figure 12.

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TYPICAL CHARACTERISTICS (continued)

All tests are made at frequency = 1 kHz unless otherwise noted.
EFFICIENCY SUPPLY CURRENT
vs vs
OUTPUT POWER OUTPUT POWER
100 2

90 1.8 RL = 4 W (SE)
Gain = 20 dB
80 1.6

ICC − Supply Current − A

70 18 V 24 V 1.4
12 V
Efficiency - %

60 1.2

50 1
24 V
40 0.8

30 0.6 18 V

20 0.4
RL = 8 W (SE) 12 V
10 Gain = 20 dB 0.2

0 0
0 1 2 3 4 5 6 7 8 9 10 11 12 0 4 8 12 16 20 24 28 32 36 40

PO − Output Power − W PO − Output Power − W

Figure 13. Figure 14.

SUPPLY CURRENT POWER SUPPLY REJECTION RATIO

vs vs
OUTPUT POWER FREQUENCY
0.9 0
VCC = 24 V
RL = 8 W, 24 V -10
0.8 VO(ripple) = 0.2 VPP
Gain = 20 dB
-20 RL = 4 W (SE)
Power Supply Rejection Ratio - dB

0.7 Gain = 20 dB
-30
ICC - Supply Current - A

0.6 18 V -40
-50
0.5
-60
12 V
0.4
-70

0.3 -80

-90
0.2
-100
0.1
-110

0 -120
0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25 20 100 1k 10k 20k
PO - Output Power - W f − Frequency − Hz
Figure 15. Figure 16.

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TYPICAL CHARACTERISTICS (continued)

All tests are made at frequency = 1 kHz unless otherwise noted.
TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE
vs vs
FREQUENCY OUTPUT POWER
10 10

THD+N - Total Harmonic Distortion + Noise - %

THD+N - Total Harmonic Distortion + Noise - %

VCC = 24 V RL = 8 W (BTL)
RL = 8 W (BTL) Gain = 20 dB
PO = 20 W
Gain = 20 dB
1 VCC = 24 V

1
VCC = 18 V

0.1
PO = 5 W VCC = 12 V

0.1
PO = 1 W
0.01

0.001 0.01
20 100 1k 10k 20k 10 m 100 m 1 10 40
f − Frequency − Hz PO − Output Power − W
Figure 17. Figure 18.

GAIN/PHASE OUTPUT POWER

vs vs
FREQUENCY SUPPLY VOLTAGE
30 65
400 60 RL = 8 W (BTL)
Gain = 20 dB
20 Gain 55
300 50
PO - Output Power - W

45
10 Phase
200 40 THD = 10%
Gain - dB

Phase - °

35
0
100 30
25 THD = 1%
-10 VCC = 24 V,
0 20
RL = 8 W (BTL),
15
Gain = 20 dB,
-20 Lfilt = 33 mH, -100 10
Cfilt = 1 mF 5
-30 -200 0
20 100 1k 10k 200k 10 12 14 16 18 20 22 24 26 28 30
f - Frequency - Hz VSS − Supply Voltage − V
A. Dashed line represents thermally limited region.
Figure 19. Figure 20.

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TYPICAL CHARACTERISTICS (continued)

All tests are made at frequency = 1 kHz unless otherwise noted.
EFFICIENCY POWER SUPPLY REJECTION RATIO
vs vs
OUTPUT POWER FREQUENCY
100 0
VCC = 24 V
90 VO(ripple) = 200 mV
-20
RL = 8 W (BTL)

Power Supply Rejection Ratio - dB

80
Gain = 20 dB
70 -40
18 V 24 V
Efficiency - %

60 12 V
-60
50

40
-80

30 -100
20
RL = 8 W (BTL) -120
10 Gain = 20 dB
0 -140
0 4 8 12 16 20 24 28 32 36 40 20 100 1k 10k 20k
PO − Output Power − W f − Frequency − Hz
Figure 21. Figure 22.

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APPLICATION INFORMATION

CLASS-D OPERATION
This section focuses on the class-D operation of the TPA3123D2.

Traditional Class-D Modulation Scheme

The TPA3123D2 operates in AD mode. There are two main configurations that may be used. For stereo
operation, the TPA3123D2 should be configured in a single-ended (SE) half-bridge amplifier. For mono
applications, TPA3123D2 may be used as a bridge-tied-load (BTL) amplifier. The traditional class-D modulation
scheme, which is used in the TPA3123D2 BTL configuration, has a differential output where each output is 180
degrees out of phase and changes from ground to the supply voltage, VCC. Therefore, the differential prefiltered
output varies between positive and negative VCC, where filtered 50% duty cycle yields 0 V across the load. The
class-D modulation scheme with voltage and current waveforms is shown in Figure 23 and Figure 24.

+VCC

0V

Output Current

Figure 23. Class-D Modulation for TPA3123D2 SE Configuration

+VCC

0V

+VCC

0V

+VCC

Differential Voltage
Across Speaker 0V

–VCC

Output Current

Figure 24. Class-D Modulation for TPA3123D2 BTL Configuration

Supply Pumping
One issue encountered in single-ended (SE) class-D amplifier designs is supply pumping. Power-supply pumping
is a rise in the local supply voltage due to energy being driven back to the supply by operation of the class-D
amplifier. This phenomenon is most evident at low audio frequencies and when both channels are operating at
the same frequency and phase. At low levels, power-supply pumping results in distortion in the audio output due
to fluctuations in supply voltage. At higher levels, pumping can cause the overvoltage protection to operate,
which temporarily shuts down the audio output.

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Several things can be done to relieve power-supply pumping. The lowest impact is to operate the two inputs out
of phase 180° and reverse the speaker connections. Because most audio is highly correlated, this causes the
supply pumping to be out of phase and not as severe. If this is not enough, the amount of bulk capacitance on
the supply must be increased. Also, improvement is realized by hooking other supplies to this node, thereby
sinking some of the excess current. Power supply pumping should be tested by operating the amplifier at low
frequencies and high output levels.

Gain Setting via GAIN0 and GAIN1 Inputs

The gain of the TPA3123D2 is set by two input terminals, GAIN0 and GAIN1.
The gains listed in Table 2 are realized by changing the taps on the input resistors and feedback resistors inside
the amplifier. This causes the input impedance (ZI) to be dependent on the gain setting. The actual gain settings
are controlled by ratios of resistors, so the gain variation from part-to-part is small. However, the input impedance
from part-to-part at the same gain may shift by ±20% due to shifts in the actual resistance of the input resistors.
For design purposes, the input network (discussed in the next section) should be designed assuming an input
impedance of 8 kΩ, which is the absolute minimum input impedance of the TPA3123D2. At the higher gain
settings, the input impedance could increase as high as 72 kΩ.

Table 2. Gain Setting

AMPLIFIER GAIN (dB), INPUT IMPEDANCE (kΩ),
GAIN1 GAIN0
TYPICAL TYPICAL
0 0 20 60
0 1 26 30
1 0 32 15
1 1 36 9

INPUT RESISTANCE
Changing the gain setting can vary the input resistance of the amplifier from its smallest value, 10 kΩ ±20%, to
the largest value, 60 kΩ ±20%. As a result, if a single capacitor is used in the input high-pass filter, the –3-dB
cutoff frequency may change when changing gain steps.

Zf

Ci
Zi
Input IN
Signal

The –3-dB frequency can be calculated using Equation 1. Use the Zi values given in Table 2.
1
f =
2p Zi Ci (1)

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INPUT CAPACITOR, CI
In the typical application, an input capacitor (Ci) is required to allow the amplifier to bias the input signal to the
proper dc level for optimum operation. In this case, Ci and the input impedance of the amplifier (Zi) form a
high-pass filter with the corner frequency determined in Equation 2.

–3 dB

1
fc =
2p Zi Ci

fc (2)
The value of Ci is important, as it directly affects the bass (low-frequency) performance of the circuit. Consider
the example where Zi is 20 kΩ and the specification calls for a flat bass response down to 20 Hz. Equation 2 is
reconfigured as Equation 3.
1
Ci =
2p Zi fc (3)
In this example, Ci is 0.4 mF; so, one would likely choose a value of 0.47 mF, as this value is commonly used. If
the gain is known and is constant, use Zi from Table 2 to calculate Ci. A further consideration for this capacitor is
the leakage path from the input source through the input network (Ci) and the feedback network to the load. This
leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom, especially
in high-gain applications. For this reason, a low-leakage tantalum or ceramic capacitor is the best choice. When
polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most
applications as the dc level there is held at VBYP (VCC/8), which is likely higher than the source dc level. Note that
it is important to confirm the capacitor polarity in the application. Additionally, lead-free solder can create dc
offset voltages, and it is important to ensure that boards are cleaned properly.

Single-Ended Output Capacitor, CO

In single-ended (SE) applications, the dc blocking capacitor forms a high-pass filter with the speaker impedance.
The frequency response rolls of with decreasing frequency at a rate of 20 dB/decade. The cutoff frequency is
determined by:
fc = 1/2pCOZL (4)
Table 3 shows some common component values and the associated cutoff frequencies:

Table 3. Common Filter Responses

CSE – DC Blocking Capacitor (mF)
Speaker Impedance (Ω)
fc = 60 Hz (–3 dB) fc = 40 Hz (–3 dB) fc = 20 Hz (–3 dB)
4 680 1000 2200
8 330 470 1000

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Output Filter and Frequency Response

For the best frequency response, a flat-passband output filter (second-order Butterworth) may be used. The
output filter components consist of the series inductor and capacitor to ground at the LOUT and ROUT pins.
There are several possible configurations depending on the speaker impedance, and whether the output
configuration is single ended (SE) or bridge-tied load (BTL). Table 4 lists the recommended values for the filter
components. It is important to use a high-quality capacitor in this application. A rating of at least X7R is required.

Table 4. Recommended Filter Output Components

Output Configuration Speaker Impedance (Ω) Filter Inductor (mH) Filter Capacitor (nF)
4 22 680
Single Ended (SE)
8 47 390
4 10 1500
Bridge Tied Load (BTL)
8 22 680

LOUT LOUT / ROUT

Lfilter Lfilter

Cfilter
Cfilter

ROUT
Lfilter
Cfilter

Figure 25. BTL Filter Configuration Figure 26. SE Filter Configuration

Power-Supply Decoupling, CS
The TPA3123D2 is a high-performance CMOS audio amplifier that requires adequate power-supply decoupling
to ensure that the output total harmonic distortion (THD) is as low as possible. Power-supply decoupling also
prevents oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is
achieved by using two capacitors of different types that target different types of noise on the power-supply leads.
For higher-frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR)
ceramic capacitor, typically 0.1 mF to 1 mF, placed as close as possible to the device VCC lead works best. For
filtering lower frequency noise signals, a larger aluminum electrolytic capacitor of 470 mF or greater placed near
the audio power amplifier is recommended. The 470-mF capacitor also serves as local storage capacitor for
supplying current during large signal transients on the amplifier outputs. The PVCC terminals provide the power
to the output transistors, so a 470-mF or larger capacitor should be placed on each PVCC terminal. A 10-mF
capacitor on the AVCC terminal is adequate. These capacitors must be properly derated for voltage and ripple
current rating to ensure reliability.

BSN and BSP Capacitors

The half H-bridge output stages use only NMOS transistors. Therefore, they require bootstrap capacitors for the
high side of each output to turn on correctly. A 220-nF ceramic capacitor, rated for at least 25 V, must be
connected from each output to its corresponding bootstrap input. Specifically, one 220-nF capacitor must be
connected from LOUT to BSL, and one 220-nF capacitor must be connected from ROUT to BSR.
The bootstrap capacitors connected between the BSx pins and their corresponding outputs function as a floating
power supply for the high-side N-channel power MOSFET gate-drive circuitry. During each high-side switching
cycle, the bootstrap capacitors hold the gate-to-source voltage high enough to keep the high-side MOSFETs
turned on.

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VCLAMP Capacitor
To ensure that the maximum gate-to-source voltage for the NMOS output transistors is not exceeded, one
internal regulator clamps the gate voltage. One 1-mF capacitor must be connected from VCLAMP (pin 11) to
ground and must be rated for at least 16 V. The voltages at the VCLAMP terminal may vary with VCC and may
not be used for powering any other circuitry.

VBYP Capacitor Selection

The scaled supply reference (VBYP) nominally provides an AVCC/8 internal bias for the preamplifier stages. The
external capacitor for this reference (CBYP) is a critical component and serves several important functions. During
start-up or recovery from shutdown mode, CBYP determines the rate at which the amplifier starts. The start up
time is proportional to 0.5 s per microfarad. Thus, the recommended 1-mF capacitor results in a start-up time of
approximately 500 ms. The second function is to reduce noise produced by the power supply caused by coupling
with the output drive signal. This noise could result in degraded power-supply rejection and THD+N.
The circuit is designed for a CBYP value of 1 mF for best pop performance. The input capacitors should have the
same value. A ceramic or tantalum low-ESR capacitor is recommended.

SHUTDOWN OPERATION
The TPA3123D2 employs a shutdown mode of operation designed to reduce supply current (ICC) to the absolute
minimum level during periods of nonuse for power conservation. The SHUTDOWN input terminal should be held
high (see specification table for trip point) during normal operation when the amplifier is in use. Pulling
SHUTDOWN low causes the outputs to mute and the amplifier to enter a low-current state. Never leave
SHUTDOWN unconnected, because amplifier operation would be unpredictable.
For the best power-up pop performance, place the amplifier in the shutdown or mute mode prior to applying the
power-supply voltage.

MUTE Operation
The MUTE pin is an input for controlling the output state of the TPA3123D2. A logic high on this terminal causes
the outputs to run at a constant 50% duty cycle. A logic low on this pin enables the outputs. This terminal may be
used as a quick disable/enable of outputs when changing channels on a television or transitioning between
different audio sources.
The MUTE terminal should never be left floating. For power conservation, the SHUTDOWN terminal should be
used to reduce the quiescent current to the absolute minimum level.

USING LOW-ESR CAPACITORS

Low-ESR capacitors are recommended throughout this application section. A real (as opposed to ideal) capacitor
can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor
minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance,
the more the real capacitor behaves like an ideal capacitor.

SHORT-CIRCUIT PROTECTION
The TPA3123D2 has short-circuit protection circuitry on the outputs that prevents damage to the device during
output-to-output shorts and output-to-GND shorts after the filter and output capacitor (at the speaker terminal.)
Directly at the device terminals, the protection circuitry prevents damage to device during output-to-output,
output-to-ground, and output-to-supply. When a short circuit is detected on the outputs, the part immediately
disables the output drive. This is an unlatched fault. Normal operation is restored when the fault is removed.

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 TPA3123D2
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THERMAL PROTECTION
Thermal protection on the TPA3123D2 prevents damage to the device when the internal die temperature
exceeds 150°C. There is a ±15°C tolerance on this trip point from device to device. Once the die temperature
exceeds the thermal set point, the device enters into the shutdown state and the outputs are disabled. This is not
a latched fault. The thermal fault is cleared once the temperature of the die is reduced by 30°C. The device
begins normal operation at this point with no external system interaction.

PRINTED-CIRCUIT BOARD (PCB) LAYOUT

Because the TPA3123D2 is a class-D amplifier that switches at a high frequency, the layout of the printed-circuit
board (PCB) should be optimized according to the following guidelines for the best possible performance.
• Decoupling capacitors—The high-frequency 0.1-mF decoupling capacitors should be placed as close to the
PVCC (pins 1, 3, 10, and 12) and AVCC (pins 19 and 20) terminals as possible. The VBYP (pin 7) capacitor
and VCLAMP (pin 11) capacitor should also be placed as close to the device as possible. Large (220-mF or
greater) bulk power-supply decoupling capacitors should be placed near the TPA3123D2 on the PVCCL and
PVCCR terminals.
• Grounding—The AVCC (pins 19 and 20) decoupling capacitor and VBYP (pin 7) capacitor should each be
grounded to analog ground (AGND, pins 8 and 9). The PVCCx decoupling capacitors and VCLAMP
capacitors should each be grounded to power ground (PGND, pins 13, 14, 23, and 24). Analog ground and
power ground should be connected at the thermal pad, which should be used as a central ground connection
or star ground for the TPA3123D2.
• Output filter—The reconstruction filter (L1, L2, C9, and C16) should be placed as close to the output terminals
as possible for the best EMI performance. The capacitors should be grounded to power ground.
• Thermal pad—The thermal pad must be soldered to the PCB for proper thermal performance and optimal
reliability. The dimensions of the thermal pad and thermal land are described in the mechanical section at the
back of the data sheet. See TI Technical Briefs SLMA002 and SLOA120 for more information about using the
thermal pad. For recommended PCB footprints, see figures at the end of this data sheet.
For an example layout, see the TPA3123D2 Evaluation Module (TPA3123D2EVM) User Manual, (SLOU189).
Both the EVM user manual and the thermal pad application note are available on the TI Web site at
http://www.ti.com.

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VCC

22 mH
470 mF 470 mF +LOUT
1.0 mF
470 mF

1.0 mF 1 24
PVCCL PGNDL 0.68 mF
Left In 2 SD PGNDL 23
3 PVCCL LOUT 22
4 MUTE BSL 21 -LOUT
5 20 0.22 mF
LIN TPA3123D2 AVCC VCC
6 RIN AVCC 19
7 BYPASS GAIN0 18 -ROUT
8 AGND GAIN1 17
Right In 0.22 mF

THERMAL
9 AGND BSR 16
10 PVCCR ROUT 15
1.0 mF 1.0 mF 11 14
VCLAMP PGNDR
12 PVCCR PGNDR 13
0.68 mF
25
Shutdown 22 mH
Control +ROUT
Mute 470 mF
Control
1.0 mF
1.0 mF
0.1 mF 10 mF

Figure 27. Schematic for Single Ended (SE) Configuration

VCC

22 mH
470 mF 470 mF +OUT
1.0 mF

1.0 mF 1 24
PVCCL PGNDL 0.68 mF
+ In 2 SD PGNDL 23
3 PVCCL LOUT 22
4 MUTE BSL 21
5 20 0.22 mF
LIN TPA3123D2 AVCC VCC
6 RIN AVCC 19
7 BYPASS GAIN0 18
8 AGND GAIN1 17
0.22 mF
THERMAL

- In 9 AGND BSR 16
10 PVCCR ROUT 15
1.0 mF 1.0 mF 11 14
VCLAMP PGNDR
12 PVCCR PGNDR 13
0.68 mF
25
Shutdown 22 mH
Control -OUT
Mute
Control
1.0 mF
1.0 mF
0.1 mF 10 mF

Figure 28. Schematic for Bridge Tied (BTL) Configuration

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 TPA3123D2
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BASIC MEASUREMENT SYSTEM

This application note focuses on methods that use the basic equipment listed below:
• Audio analyzer or spectrum analyzer
• Digital multimeter (DMM)
• Oscilloscope
• Twisted-pair wires
• Signal generator
• Power resistor(s)
• Linear regulated power supply
• Filter components
• EVM or other complete audio circuit
Figure 29 shows the block diagrams of basic measurement systems for class-AB and class-D amplifiers. A sine
wave is normally used as the input signal because it consists of the fundamental frequency only (no other
harmonics are present). An analyzer is then connected to the audio power amplifier (APA) output to measure the
voltage output. The analyzer must be capable of measuring the entire audio bandwidth. A regulated dc power
supply is used to reduce the noise and distortion injected into the APA through the power pins. A System Two™
audio measurement system (AP-II) by Audio Precision™ includes the signal generator and analyzer in one
package.
The generator output and amplifier input must be ac-coupled. However, the EVMs already have the ac-coupling
capacitors, (CIN), so no additional coupling is required. The generator output impedance should be low to avoid
attenuating the test signal, and is important because the input resistance of APAs is not high. Conversely, the
analyzer input impedance should be high. The output resistance, ROUT, of the APA is normally in the hundreds of
milliohms and can be ignored for all but the power-related calculations.
Figure 29(a) shows a class-AB amplifier system. It takes an analog signal input and produces an analog signal
output. This amplifier circuit can be directly connected to the AP-II or other analyzer input.
This is not true of the class-D amplifier system shown in Figure 29(b), which requires low-pass filters in most
cases in order to measure the audio output waveforms. This is because it takes an analog input signal and
converts it into a pulse-width modulated (PWM) output signal that is not accurately processed by some
analyzers.

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Power Supply

Signal APA RL Analyzer

Generator 20 Hz - 20 kHz

(a) Basic Class-AB

Power Supply

Lfilt

Signal Class-D APA Cfilt Analyzer

Generator RL 20 Hz - 20 kHz

(b) Traditional Class-D

Figure 29. Audio Measurement Systems

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SE Input and SE Output (TPA3123D2 Stereo Configuration)

The SE input and output configuration is used with class-AB amplifiers. A block diagram of a fully SE
measurement circuit is shown in Figure 30. SE inputs normally have one input pin per channel. In some cases,
two pins are present; one is the signal and the other is ground. SE outputs have one pin driving a load through
an output ac-coupling capacitor and the other end of the load is tied to ground. SE inputs and outputs are
considered to be unbalanced, meaning one end is tied to ground and the other to an amplifier input/output.
The generator should have unbalanced outputs, and the signal should be referenced to the generator ground for
best results. Unbalanced or balanced outputs can be used when floating, but they may create a ground loop that
affects the measurement accuracy. The analyzer should have balanced inputs to cancel out any common-mode
noise in the measurement.

Evaluation Module
Audio Power
Generator Analyzer
Amplifier
CIN

Lfilt
RGEN RIN CL
VGEN
RANA CANA
Cfilt RL

RANA CANA

Twisted-Pair Wire Twisted-Pair Wire

Figure 30. SE Input—SE Output Measurement Circuit

The following general rules should be followed when connecting to APAs with SE inputs and outputs:
• Use an unbalanced source to supply the input signal.
• Use an analyzer with balanced inputs.
• Use twisted-pair wire for all connections.
• Use shielding when the system environment is noisy.
• Ensure the cables from the power supply to the APA, and from the APA to the load, can handle the large
currents (see Table 5).

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DIFFERENTIAL INPUT AND BTL OUTPUT (TPA3123D2 Mono Configuration)

Many of the class-D APAs and many class-AB APAs have differential inputs and bridge-tied-load (BTL) outputs.
Differential inputs have two input pins per channel and amplify the difference in voltage between the pins.
Differential inputs reduce the common-mode noise and distortion of the input circuit. BTL is a term commonly
used in audio to describe differential outputs. BTL outputs have two output pins providing voltages that are 180°
out of phase. The load is connected between these pins. This has the added benefits of quadrupling the output
power to the load and eliminating a dc-blocking capacitor.
A block diagram of the measurement circuit is shown in Figure 31. The differential input is a balanced input,
meaning the positive (+) and negative (–) pins have the same impedance to ground. Similarly, the SE output
equates to a balanced output.

Evaluation Module
Audio Power
Generator Analyzer
Amplifier
CIN Lfilt

RGEN RIN Cfilt RANA CANA

VGEN RL
CIN Lfilt

RGEN RIN Cfilt RANA CANA

Twisted-Pair Wire Twisted-Pair Wire

Figure 31. Differential Input, BTL Output Measurement Circuit

The generator should have balanced outputs, and the signal should be balanced for best results. An unbalanced
output can be used, but it may create a ground loop that affects the measurement accuracy. The analyzer must
also have balanced inputs for the system to be fully balanced, thereby cancelling out any common-mode noise in
the circuit and providing the most accurate measurement.
The following general rules should be followed when connecting to APAs with differential inputs and BTL outputs:
• Use a balanced source to supply the input signal.
• Use an analyzer with balanced inputs.
• Use twisted-pair wire for all connections.
• Use shielding when the system environment is noisy.
• Ensure that the cables from the power supply to the APA, and from the APA to the load, can handle the large
currents (see Table 5).
Table 5 shows the recommended wire size for the power supply and load cables of the APA system. The real
concern is the dc or ac power loss that occurs as the current flows through the cable. These recommendations
are based on 12-inch (30.5-cm)-long wire with a 20-kHz sine-wave signal at 25°C.

Table 5. Recommended Minimum Wire Size for Power Cables

DC POWER LOSS AC POWER LOSS
POUT (W) RL(Ω) AWG Size
(mW) (mW)
10 4 18 22 16 40 18 42
2 4 18 22 3.2 8 3.7 8.5
1 8 22 28 2 8 2.1 8.1
< 0.75 8 22 28 1.5 6.1 1.6 6.2

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www.ti.com SLOS541C – JULY 2007 – REVISED AUGUST 2010

REVISION HISTORY

Changes from Original (July 2007) to Revision A Page

• Changed the device status From: Product Preview To: Production ..................................................................................... 1

Changes from Revision A (August 2007) to Revision B Page

• Changed the INPUT IMPEDANCE values in Table 2. ........................................................................................................ 13

Changes from Revision B (September 2007) to Revision C Page

• Replaced the Dissipations Ratings Table with the Thermal Information Table .................................................................... 3

Copyright © 2007–2010, Texas Instruments Incorporated Submit Documentation Feedback 23

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 PACKAGE OPTION ADDENDUM

www.ti.com 14-Jul-2025

PACKAGING INFORMATION

Orderable part number Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
(1) (2) (3) Ball material Peak reflow (6)
(4) (5)

TPA3123D2PWP Active Production HTSSOP (PWP) | 24 60 | TUBE Yes NIPDAU Level-3-260C-168 HR -40 to 85 TPA3123D2
TPA3123D2PWP.A Active Production HTSSOP (PWP) | 24 60 | TUBE Yes NIPDAU Level-3-260C-168 HR -40 to 85 TPA3123D2
TPA3123D2PWP.B Active Production HTSSOP (PWP) | 24 60 | TUBE Yes NIPDAU Level-3-260C-168 HR -40 to 85 TPA3123D2
TPA3123D2PWPR Active Production HTSSOP (PWP) | 24 2000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 TPA3123D2
TPA3123D2PWPR.A Active Production HTSSOP (PWP) | 24 2000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 TPA3123D2
TPA3123D2PWPR.B Active Production HTSSOP (PWP) | 24 2000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 TPA3123D2
TPA3123D2PWPRG4 Active Production HTSSOP (PWP) | 24 2000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 TPA3123D2
TPA3123D2PWPRG4.A Active Production HTSSOP (PWP) | 24 2000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 TPA3123D2
TPA3123D2PWPRG4.B Active Production HTSSOP (PWP) | 24 2000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 85 TPA3123D2

(1)
Status: For more details on status, see our product life cycle.

(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance,
reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional
waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.

(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.

(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum
column width.

(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown.
Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.

(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.

Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two
combined represent the entire part marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and
makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 14-Jul-2025

and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers
and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 15-Jul-2025

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPA3123D2PWPR HTSSOP PWP 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
TPA3123D2PWPRG4 HTSSOP PWP 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 15-Jul-2025

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPA3123D2PWPR HTSSOP PWP 24 2000 350.0 350.0 43.0
TPA3123D2PWPRG4 HTSSOP PWP 24 2000 350.0 350.0 43.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 15-Jul-2025

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
TPA3123D2PWP PWP HTSSOP 24 60 530 10.2 3600 3.5
TPA3123D2PWP.A PWP HTSSOP 24 60 530 10.2 3600 3.5
TPA3123D2PWP.B PWP HTSSOP 24 60 530 10.2 3600 3.5

Pack Materials-Page 3
 GENERIC PACKAGE VIEW
TM
PWP 24 PowerPAD TSSOP - 1.2 mm max height
4.4 x 7.6, 0.65 mm pitch PLASTIC SMALL OUTLINE

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4224742/B

www.ti.com
 PACKAGE OUTLINE
PWP0024B SCALE 2.200
PowerPAD TM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE

6.6 SEATING PLANE

TYP C
6.2
PIN 1 ID
A AREA 0.1 C
22X 0.65
24
1

7.9 2X
7.7 7.15
NOTE 3

12
13
0.30
4.5 24X
B 0.19
4.3
0.1 C A B

(0.15) TYP

SEE DETAIL A

4X (0.2) MAX
2X (0.95) MAX NOTE 5
NOTE 5

EXPOSED
THERMAL PAD

0.25
5.16
4.12 GAGE PLANE 1.2 MAX

0.15
0 -8 0.05
0.75
0.50 DETAIL A
(1) TYPICAL
2.40
1.65
4222709/A 02/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may not be present and may vary.

www.ti.com
 EXAMPLE BOARD LAYOUT
PWP0024B PowerPAD TM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE

(3.4)
NOTE 9 SOLDER MASK
(2.4) DEFINED PAD
24X (1.5) SYMM
SEE DETAILS
1
24

24X (0.45)

(R0.05)
TYP

(1.1) (7.8)
SYMM TYP NOTE 9

(5.16)

22X (0.65)

( 0.2) TYP
VIA

12 13

METAL COVERED (1) TYP

BY SOLDER MASK
(5.8)

LAND PATTERN EXAMPLE

SCALE:10X

METAL UNDER SOLDER MASK

SOLDER MASK METAL SOLDER MASK OPENING
OPENING

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

PADS 1-24
4222709/A 02/2016

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.

www.ti.com
 EXAMPLE STENCIL DESIGN
PWP0024B PowerPAD TM TSSOP - 1.2 mm max height
PLASTIC SMALL OUTLINE

(2.4)
BASED ON
24X (1.5) 0.125 THICK
STENCIL
(R0.05) TYP
1
24

24X (0.45)

(5.16)
SYMM BASED ON
0.125 THICK
STENCIL

22X (0.65)

12 13

SYMM
METAL COVERED
BY SOLDER MASK SEE TABLE FOR
DIFFERENT OPENINGS
(5.8) FOR OTHER STENCIL
THICKNESSES

SOLDER PASTE EXAMPLE

EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X

STENCIL SOLDER STENCIL

THICKNESS OPENING
0.1 2.68 X 5.77
0.125 2.4 X 5.16 (SHOWN)
0.15 2.19 X 4.71
0.175 2.03 X 4.36

4222709/A 02/2016

NOTES: (continued)

10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.

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