Module 2

Sequential logic circuits:

✓ Edge triggering
✓ Pulse triggering
✓ SR latch
✓ SR flip flop
✓ JK flip flop
✓ Master slave JK flip flop
✓ D flip flop
✓ T flip flop
Shift register:
✓ Serial in-serial out (SISO) configuration
✓ Serial in-parallel out (SIPO) configuration
✓ Parallel in-serial out (PISO) configuration
✓ Parallel in-parallel out (PIPO) configuration
Counters (asynchronous and synchronous)
✓ Up/down counter
✓ Decade counter
✓ Mod N counter
✓ Ring counter
✓ Johnson’s counter

Introduction to Sequential Logic Circuits

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• A Sequential logic circuits is a form of binary circuit; its design employs one or more inputs an one
or more outputs, whose states are related to some definite rules that depends on previous states.

• Both the inputs and outputs can reach either of the two states:

logic 0 (low) or

logic 1 (high).

• In these circuits their output depends, not only

on the combination of the logic states at its
inputs, but moreover on the logic states that
existed previously.

• In other words their output depends on a

SEQUENCE of the events occurring at the
circuit inputs.

• Examples of such circuits include clocks, flip-

flops, bi-stables, counters, memories, and registers.

• Dissimilar Combinational Logic circuits can change state depending on the real signals that are
applied to their inputs, at the same time, Sequential Logic Circuits include some form of inherent
“Memory” build into them as they are capable of taking into account their previous input state as
well as the individuals really present, a sort
of “before” and “after” effect is involved
with the sequential logic circuits.

Types of Sequential Logic

Circuits
There are three types of sequential
circuits:

• Event Driven
• Clock Driven
• Pulse Driven

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Examples of Sequential Logic Circuits
✓ Clocks
✓ Flip flops
✓ Bi-stable
✓ Counters
✓ Registers
✓ Memories

Clocks

State changes of most sequential circuits occur at times specified by free-running clock signals.
As the name implies, sequential logic circuits require a means by which events can be a sequenced.

• The state changes are controlled by the clocks. A “clock” is a special circuit that sends pulses with
and an accurate pulse width and an accurate interval between the consecutive pulses.
• The interval between consecutive pulses is called as the clock cycle time.
• The Clock speed is a normally measured in Megahertz or Gigahertz.

Flip flops
• The basic building block of combinational circuit has a logic gates, while indeed the basic building
block of a sequential circuit is a flip-flop.
• Flip-flop has a better and greater usage in shift register, counters and memory devices.
• It is a storage device capable of storing one bit data.
• Flip flop has two inputs and two outputs labeled as Q and Q’. It is normal and complement.

Bi-stables
• Bi-stables are of two types latch and flip flop. The bi-stables have two stable states one is SET and
the other one is RESET.

Bi-stable input and output Wave forms

Counters

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• A counter is a register that goes throughout a predetermined sequence of states upon the
application of clock pulses.
• From another viewpoint, a counter is some sort of sequential circuit whose state diagram is a
single cycle.
• In other words, counters are a particular case of a finite state machine. Output is generally a state
value.
• There are two types of counters:
Asynchronous counters (Ripple counter) and the other one is Synchronous counters.
• Asynchronous counter is the clock signal (CLK), which is simply used to clock the first FF.
• Each FF (except the first FF) is clocked by the preceding FF.
• Synchronous counter is the clock signal (CLK) that is functional to all FF, which means that all FF
shares the same clock signal. Thus, the output changes at the same time.
Registers

• Registers are clocked sequential circuits.

• A register is a collection of flip-flops; each flip-flop is capable of storing one bit of information.
• A n-bit register consists of n flip-flops and is capable of storing n bits of information.
• Besides flip-flops, a register usually contains a combinational logic to perform some simple tasks.
• The flip-flops hold binary information.
• Counters are a special type of register
Memories
Memory elements can be anything that create a past value available at some future time-
devices that can behold a binary value. Memory elements are typically flip-flops. Memory output
which is considered as circuit’s “current state” is a numerical label.

Sequential Circuits
• The combinational circuit does not use any memory. Hence the previous state of input does not
have any effect on the present state of the circuit. But sequential circuit has memory so output
can vary based on input. This type of circuits uses previous input, output, clock and a memory
element.

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Block diagram

Combinational Circuits Sequential Circuits

Outputs depend only on present inputs. Outputs depend on both present inputs and present state.

Feedback path is not present. Feedback path is present.

Memory elements are not required. Memory elements are required.

Clock signal is not required. Clock signal is required.

Easy to design. Difficult to design.

Types of Sequential Circuits

Following are the two types of sequential circuits −

• Asynchronous sequential circuits

• Synchronous sequential circuits
Asynchronous sequential circuits
If some or all the outputs of a sequential circuit do not change (affect) with respect to active transition
of clock signal, then that sequential circuit is called as Asynchronous sequential circuit.

Synchronous sequential circuits

If all the outputs of a sequential circuit change (affect) with respect to active transition of clock signal,
then that sequential circuit is called as Synchronous sequential circuit.

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Clock Signal and Triggering
Clock signal
• Clock signal is a periodic signal and its ON time and OFF time need not be the same.
• We can represent the clock signal as a square wave, when both its ON time and OFF time are
same.
• This clock signal is shown in the following figure.

• in the above figure, square wave is considered as clock signal. This signal stays at logic High (5V)
for some time and stays at logic Low (0V) for equal amount of time.
• This pattern repeats with some time period. In this case, the time period will be equal to either
twice of ON time or twice of OFF time.
• We can represent the clock signal as train of pulses, when ON time and OFF time are not same.
This clock signal is shown in the following figure.

Types of Triggering
Following are the two possible types of triggering that are used in sequential circuits.

• Level triggering
• Edge triggering
Level triggering
• There are two levels, namely logic High and logic Low in clock signal. Following are the two types
of level triggering.
✓ Positive level triggering
✓ Negative level triggering
• If the sequential circuit is operated with the clock signal when it is in Logic High, then that type
of triggering is known as Positive level triggering. It is highlighted in below figure.

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• If the sequential circuit is operated with the clock signal when it is in Logic Low, then that
type of triggering is known as Negative level triggering.

• It is highlighted in the following figure.

Edge triggering
• There are two types of transitions that occur in clock signal. That means, the clock signal
transitions either from Logic Low to Logic High or Logic High to Logic Low.
• Following are the two types of edge triggering based on the transitions of clock signal.
✓ Positive edge triggering
✓ Negative edge triggering
• If the sequential circuit is operated with the clock signal that is transitioning from Logic Low to
Logic High, then that type of triggering is known as Positive edge triggering.
• It is also called as rising edge triggering.
• It is shown in the following figure.

• If the sequential circuit is operated with the clock signal that is transitioning from Logic High to
Logic Low, then that type of triggering is known as Negative edge triggering.

• It is also called as falling edge triggering.

• It is shown in the following figure.

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Latches [level triggered] and flip flops [edge triggered]
• There are two types of memory elements based on the type of triggering that is suitable to
operate it.

1)Latches

2)Flip-flops

• Latches operate with enable signal, which is level sensitive. Whereas, flip-flops are edge sensitive.
SR Latch
• SR Latch is also called as Set Reset Latch.
• This latch affects the outputs as long as the enable, E is maintained at ‘1’.
• The circuit diagram of SR Latch is shown in the following figure.

• This circuit has two inputs S & R and two outputs Q(t) & Q(t)’. The upper NOR gate has two inputs
R & complement of present state, Q(t)’ and produces next state, Q(t+1) when enable, E is ‘1’.
• Similarly, the lower NOR gate has two inputs S &
present state, Q(t) and produces complement of
next state, Q(t+1)’ when enable, E is ‘1’.
• We know that a 2-input NOR gate produces an
output, which is the complement of another input
when one of the input is ‘0’. Similarly, it produces ‘0’
output, when one of the input is ‘1’.
o If S = 1, then next state Q(t + 1) will be
equal to ‘1’ irrespective of present
state, Q(t) values.
o If R = 1, then next state Q(t + 1) will be equal to ‘0’ irrespective of present state, Q(t)
values.

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• If both inputs are ‘1’, then the next state Q(t + 1) value is undefined.
state table of SR latch.

S R Q(t + 1)

0 0 Q(t)

0 1 0

1 0 1

1 1 -

• Therefore, SR Latch performs three types of functions such as Hold, Set & Reset based on the
input conditions.
• Logic circuit :

• Logic symbol:

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D Latch
• There is one drawback of SR Latch. That is the next state value can’t be predicted when both the
inputs S & R are one. So, we can overcome this difficulty by D Latch. It is also called as Data Latch.

Flip Flop
• Flip flop is a sequential circuit which generally samples its inputs and changes its outputs only at
particular instants of time and not continuously.
• Flip flop is said to be edge sensitive or edge triggered rather than being level triggered like latches.
• Flip flop is a clocked sequential circuit.

SR flip flop
Graphic symbol

• It has 3 inputs
1. S--→set
2. R--→ reset
3. C--→clock
• It has an output Q and sometimes the flip flop has a complemented output,which is indicated
with a small circle at the other output terminal.
• There is an arrowhead-shaped symbol in front of the letter C to designate a dynamic input.the
dynamic indication symbol in front of the letter C denotes the fact that the flip flops responds
to a positive transition[from 0 to 1] of the input clock signal.

Operation of SR flip flops

If there is no signal at the clock input C , the output of the circuit cannot change irrespective of
the value at input S and R.
• If S=1 and R=0 when c changes from 0 to 1,output Q is set to 1
• if S=0 and R=1 when C changes from O to 1, input Q is Cleared to 0
• It both S=0 and R=0 during the clock transition the output does not changes.
• Only when the clock signal changes from O to 1, can the output be affected according to the
values in input S and R.

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 • When both S=1 and R=1, the output is un predicted or un predictable and may go to either
O or 1 depending on internal tinning delays that occur within the circuit.

Characteristic Table
The operation of SR Flip Flop in tabular form are:-

Here S and R columns gives the binary value of the 2 inputs.

• Q (t) is the binary state of the Q output at a given time (referred to as present state)
• Q (t+1) is the binary state of the Q output after the occurance of a clock transaction (referred to as
nest state)
• If S=R =0, a clock transaction produces no change of state [ie, Q(t+1)= Q(t)]
• If S=0 and R=1, the flip_ flop goes to the 0
[Clear state].state
• If S=1 and R=0 the flip-flop goes to the 1 (set) state.
• The SR flip _ flop should no be pulsed when S=R=1 since it produces an indeterminate next state.
This indeterminate condition makes the S R flip-flop difficult to manage and there for it is seldom
used in practice

D flip-flop
The D (data) flip-flop is a slight modification of the S R flip-flop

• An S R flip-flop is converted to a D flip-flop by inserting an inverter between S and R and

assigning the symbol D to the single input

• sampled during the occurance of a clock transition from 0 to 1

• if D=1, the output of the flip-flop goes to the 1 state, but if D=0,the output of the flip-flop
goes to the 0 state

Grahpic Symbol

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Characteristic Table
• Here represent the next state Q(t+1) is determined the D input

• The relationship can be expressed by a characteristic equation:

Q (t+1) = D

This means that the Q output of the flip-flop recieves it value from the D input every time that the
clock signal goes through a transition from 0 to 1

J K flip-flop
• J K flip-flop is the modified version of S R flip-flop in that the indeterminate condition of the
S R type is defined in the J K flip-flop

• Input J and K behave like input s and R to set and clear the flip-flop respectively

• When input J and K are both equal to 1,a clock transition switches the output of the flip-flop
to their complement state

Graphic symbol

Characteristics Table

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• The j input is equivalent to the S(put of the S R flip-flop, and the K input is equivalent to the R
(clear)input. Insert of the indeterminate condition, the JK flip-flop has a complement condition
Q(t+1)=Q'(t) when both J and K are equal to 1

T flip-flop /Toggle flip-flop

• T flip-flop is the simplified version of JK flip-flop.

• Here from a JK flip-flop when input J and K are connected to provide a single designated by
T. ie, it is obtained by connecting the same input 'T' to both input of JK flip-flop

• The T flip-flop there for has only 2 condition . When T+0(j=k=0) a clock transition does not
change the state of the flip-flop.

• When T=1 (J=K=1) a clock transition complements the state of the flip-flop.

• The condition can be expressed by a characteristic equation.

Q (t+1) =Q(t) (+) T

Graphic symbol

Characteristic Table

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Master Slave J-K flip-flop
The master slave flip-flop eliminates all the timing problem by using 2 JK flip-flops connected
together in a series configuration.

• Out of these one acts as the "master " and other as a slave.

• In "master" circuit, Which triggers on the leading edge of the clock while the other act as the
slave circuit, Which triggers on the falling edge of the clock pulse

J-K flip-flop

• The output from the master flip-flop is connected to the two inputs of the slave flip-flop
whose output is fed back to inputs of the master flip-flop.

• In addition to these 2 flip-flops the circuits also includes an inverter. The inverter is
connected to clock pulse in such a way that the inverted clock pulse is given to the slave flip-
flop.

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Timing diagram of a Master slave flip-flop

1. When the clock pulse is high the output of master is high and remains high till the clock is low
because the state is stored

2. Now the output of master becomes low when the clock pulse becomes high again and remains
low until the clock becomes high again.

3. Thus toggling takes place for a clock cycle.

4. When the clock pulse is high, the master is operational but not the slave thus the output of the
slave remains low till the clock remains high.

5. When the clock is low, the slave becomes operational and remains until the clock again becomes
low.

6. Toggling takes place during the whole process since the output is changing once in a cycle.

Digital logic |counters

• a Counter is a device which stores (and sometimes displays) the number of times a particular
event or process has occurred, often in relationship to a clock signal.
• Counters are used in digital electronics for counting purpose, they can count specific event
happening in the circuit.

Counter Classification
• Counters are broadly divided into two categories:
1) Asynchronous counter
2) Synchronous counter
1. Asynchronous Counter:

• In asynchronous counter we don’t use universal clock, only first flip flop is driven by main clock
and the clock input of rest of the following counters is driven by output of previous flip flops.

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• We can understand it by following diagram-

• It is evident from timing diagram that Q0 is changing as soon as the rising edge of clock pulse is
encountered, Q1 is changing when rising edge of Q0 is encountered(because Q0 is like clock pulse
for second flip flop) and so on.
• In this way ripples are generated through Q0,Q1,Q2,Q3 hence it is also called RIPPLE counter.
2. Synchronous Counter
• Unlike the asynchronous counter, synchronous counter has one global clock which drives each flip
flop so output changes in parallel.
• The one advantage of synchronous counter over asynchronous counter is, it can operate on higher
frequency than asynchronous counter as it does not have cumulative delay because of same clock
is given to each flip flop.

Synchronous counter circuit

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-Timing diagram synchronous counter-
From circuit diagram we see that Q0 bit gives response to each falling edge of clock while Q1 is
dependent on Q0, Q2 is dependent on Q1 and Q0 , Q3 is dependent on Q2,Q1 and Q0.
Decade Counter
• A decade counter counts ten different states and then reset to its initial states.
• A simple decade counter will count from 0 to 9 but we can also make the decade counters which
can go through any ten states between 0 to 15(for 4 bit counter).

Clock pulse Q3 Q2 Q1 Q0

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

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 8 1 0 0 0

9 1 0 0 1

10 0 0 0 0

- Truth table for simple decade counter-

- Decade counter circuit diagram-

Modulus counter [MOD-N counter]

• counters can be designed to count to any number of 2n states in their sequence by cascading
together multiple counting stages to produce a single modulus or MOD-N counter.Therefore, a
“Mod-N” counter will require “N” number of flip-flops connected together to count a single data
bit while providing 2n different output states, (n is the number of bits).
• Note that N is always a whole integer value.
• The we can see that MOD counters have a modulus value that is an integral power of 2, that is, 2,
4, 8, 16 and so on to produce an n-bit counter depending on the number of flip-flops used, and
how they are connected, determining the type and modulus of the counter.

• The 2-bit ripple counter is called as MOD-4 counter and 3 bit ripple counter is called as MOD-8
counter. So in general,an n-bit ripple counter is called as modulo-N-counter.
Where MOD number=2n

• Types of modulus:
-2 bit up or down (MOD-4)
-3 bit up or down (MOD-8)
-4 bit up or down (MOD-16)

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Up and down counter/bidirectional shift register
• The job of a counter is to count by advancing the contents of the counter by one count with each
clock pulse.
• Counters which advance their sequence of numbers or states when activated by a clock input are
said to operate in a “count-up” mode.
• Likewise, counters which decrease their sequence of numbers or states when activated by a clock
input are said to operate in a “count-down” mode.
• Counters that operate in both the UP and DOWN modes, are called bidirectional counters.

• Bidirectional shift registers are the registers which are capable of shifting the data either right or
left depending on the mode selected.
• If the mode selected is 1(high), the data will be shifted towards the right direction and if the mode
selected is 0(low), the data will be shifted towards the left direction.
• The logic circuit given below shows a Bidirectional shift register. The circuit consists of four D flip-
flops which are connected. The input data is connected at two ends of the circuit and depending
on the mode selected only one and gate is in the active state.

Applications of counters
➢ Frequency counters
➢ Digital clock
➢ Time measurement
➢ A to D converter
➢ Frequency divider circuits
➢ Digital triangular wave generator

Digital logic | Shift Registers

• Flip flops can be used to store a single bit of binary data (1or 0). However, in order to store multiple
bits of data, we need multiple flip flops.
• N flip flops are to be connected in an order to store n bits of data.

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• A Register is a device which is used to store such information. It is a group of flip flops connected
in series used to store multiple bits of data.
• The information stored within these registers can be transferred with the help of shift registers.
• Shift Register is a group of flip flops used to store multiple bits of data.
• The bits stored in such registers can be made to move within the registers and in/out of the
registers by applying clock pulses.
• An n-bit shift register can be formed by connecting n flip-flops where each flip flop stores a single
bit of data.
• The registers which will shift the bits to left are called “Shift left registers”.
• The registers which will shift the bits to right are called “Shift right registers”.
• Shift registers are basically of 4 types. These are:

1) Serial In Serial Out shift register

2) Serial In parallel Out shift register
3) Parallel In Serial Out shift register
4) Parallel In parallel Out shift register

Serial-In Serial-Out Shift Register (SISO) –

• The shift register, which allows serial input (one bit after the other through a single data line) and
produces a serial output is known as Serial-In Serial-Out shift register. Since there is only one
output, the data leaves the shift register one bit at a time in a serial pattern, thus the name Serial-
In Serial-Out Shift Register.
• The logic circuit given below shows a serial-in serial-out shift register. The circuit consists of four
D flip-flops which are connected in a serial manner.
• All these flip-flops are synchronous with each other since the same clock signal is applied to each
flip flop.

•
• The above circuit is an example of shift right register, taking the serial data input from the left side
of the flip flop. The main use of a SISO is to act as a delay element.

Serial-In Parallel-Out shift Register (SIPO) –

• The shift register, which allows serial input (one bit after the other through a single data line) and
produces a parallel output is known as Serial-In Parallel-Out shift register.
• The logic circuit given below shows a serial-in-parallel-out shift register. The circuit consists of four
D flip-flops which are connected.

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• The clear (CLR) signal is connected in addition to the clock signal to all the 4 flip flops in order to
RESET them.
• The output of the first flip flop is connected to the input of the next flip flop and so on.
• All these flip-flops are synchronous with each other since the same clock signal is applied to each
flip flop

• The above circuit is an example of shift right register, taking the serial data input from the left side
of the flip flop and producing a parallel output.
• They are used in communication lines where demultiplexing of a data line into several parallel
lines is required because the main use of the SIPO register is to convert serial data into parallel
data.

Parallel-In Serial-Out Shift Register (PISO) –

• The shift register, which allows parallel input (data is given separately to each flip flop and in a
simultaneous manner) and produces a serial output is known as Parallel-In Serial-Out shift
register.
• The logic circuit given below shows a parallel-in-serial-out shift register.
• The circuit consists of four D flip-flops which are connected.
• The clock input is directly connected to all the flip flops but the input data is connected
individually to each flip flop through a multiplexer at the input of every flip flop.
• The output of the previous flip flop and parallel data input are connected to the input of the MUX
and the output of MUX is connected to the next flip flop.
• All these flip-flops are synchronous with each other since the same clock signal is applied to each
flip flop.

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• A Parallel in Serial out (PISO) shift register us used to convert parallel data to serial data.

Parallel-In Parallel-Out Shift Register (PIPO) –

• The shift register, which allows parallel input (data is given separately to each flip flop and in a
simultaneous manner) and also produces a parallel output is known as Parallel-In parallel-Out shift
register.
• The logic circuit given below shows a parallel-in-parallel-out shift register. The circuit consists of
four D flip-flops which are connected.
• The clear (CLR) signal and clock signals are connected to all the 4 flip flops.
• In this type of register, there are no interconnections between the individual flip-flops since no
serial shifting of the data is required.
• Data is given as input separately for each flip flop and in the same way, output also collected
individually from each flip flop.

• A Parallel in Parallel out (PIPO) shift register is used as a temporary storage device and like SISO
Shift register it acts as a delay element.

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Shift Register Counter –

• Shift Register Counters are the shift registers in which the outputs are connected back to the
inputs in order to produce particular sequences. These are basically of two types:
1. Ring Counter
2. Johnson’s counter

1)Ring Counter–
• A ring counter is basically a shift register counter in which the output of the first flip flop is
connected to the next flip flop and so on and the output of the last flip flop is again fed back to
the input of the first flip flop, thus the name ring counter.
• The data pattern within the shift register will circulate as long as clock pulses are applied.
• The logic circuit given below shows a Ring Counter.
• A Ring counter is generally used because it is self-decoding. No extra decoding circuit is needed to
determine what state the counter is in.

• The circuit consists of four D flip-flops which are connected. Since the circuit consists of four flip
flops the data pattern will repeat after every four clock pulses as shown in the truth table below:

2) Johnson Counter –
• A Johnson counter is basically a shift register counter in which the output of the first flip flop is
connected to the next flip flop and so on and the inverted output of the last flip flop is again fed
back to the input of the first flip flop.
• They are also known as twisted ring counters.

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• The logic circuit given below shows a Johnson Counter.

• The circuit consists of four D flip-flops which are connected.

• An n-stage Johnson counter yields a count sequence of 2n different states, thus also known as a
mod-2n counter. Since the circuit consists of four flip flops the data pattern will repeat every eight
clock pulses as shown in the truth table below:

• The main advantage of Johnson counter is that it only needs n number of flip-flops compared
to the ring counter to circulate a given data to generate a sequence of 2n states.

Applications of shift Registers –

• The shift registers are used for temporary data storage.

• The shift registers are also used for data transfer and data manipulation.
• The serial-in serial-out and parallel-in parallel-out shift registers are used to produce time
delay to digital circuits.
• The serial-in parallel-out shift register is used to convert serial data into parallel data thus they
are used in communication lines where demultiplexing of a data line into several parallel line
is required.
• A Parallel in Serial out shift register us used to convert parallel data to serial data.

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