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Course Name: Digital Logics

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CHAPTER 4: A/D AND D/A CONVERTERS

4.1 DIGITAL TO ANALOG CONVERTERS

Introduction
​ ​ Most of the real world physical quantities such as voltage, current, temperature,
Pressure and time etc are available in analog form.
​ ​Even though an analog signal represents a physical parameter with accuracy, it is
difficult to process, store, or transmit the analog signal without introducing
considerable error because of superimposition of noise as in the case of amplitude
modulation.
​ Therefore, for processing, transmission and storage purposes, it is often convenient to
express these variables in digital form. It gives better accuracy and reduces noise.
​ ​The operation of any digital communication system is based upon Analog to Digital
(A/D) and Digital to Analog (D/A) conversion.
​ ​Figure highlights a typical application within which A/D and D/A conversion is used.

​ The analog signal obtained from the transducer is bandlimited by an antialiasing filter.
The signal is then sampled at a frequency rate more than twice the maximum
frequency of the band limited signal.
​ The sampled signal has to be held constant while conversion is taking place in the
A/D converter. This requires that ADC should be preceded by a sample and hold
(S/H) circuit.
​ The ADC output is equal in binary digit. The micro-computer or Digital signal
processor performs the numerical calculations of the desired control algorithm.
​ The D/A converter is to convert digital signal into analog and hence the function of
DAC is exactly opposite to that of ADC. The D/A converter is usually operated at the
same frequency as the ADC.
​ The output of a D/A converter is commonly a staircase. This staircase is like output is
passed through a smoothing filter to reduce the effect of quantization noise.

Applications of A/D and D/A conversion

The scheme given in Figure is used either in full or in part in applications such as digital audio
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recording and playback, computer, music and video synthesis, pulse code modulation transmission,
data acquisition, digital multimeter, direct digital control, digital signal processing, microprocessor
based instrumentation

Basic DAC techniques

The schematic of a DAC is shown in Figure

​ The input is an n-bit binary word D and is combined with a reference voltage VR to give an
analog output signal.
​ The output of a DAC can be either a voltage or current.
Vo=K . Vfs(d1. 2^-1 + d2 .2^-2 + d3. 2^-3+ ----- +dn. 2^-n) -​ (1)
​ Where, V0 = output voltage
Vfs=full scale output voltage
K=scaling factor usually adjusted to unity d1d2d3​
dn=n-bit binary fractional word
d1 = MSB with weight of Vfs/2 dn=LSBwith a weight of Vfs/2n

​ There are various ways to implement eq(1).Here we shall discuss the following
resistive techniques only
✔​ Weighted resistor DAC
✔​ R-2R Ladder DAC
✔​ Inverted R-2R Ladder DAC

4.2 WEIGHTED RESISTOR DAC

​ One of the simplest circuits shown in Figure uses a summing amplifier with a binary
weighted resistor network. It has n-electronic switches d1, d2, d3….dn, controlled by
Binary input words.
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​ These switches are single pole double throw(SPDT)type.

​ If the Binary input to a particular switch is 1, it connects the resistance to the

reference voltage(-V).And if the input bit is zero, the switch connects the resistor
to ground.
​ Comparing Eq. (1) with Eq. (2), it can be seen that if Rf= R then K = 1 and VFS=VR.
The circuit shown in Fig. uses a negative reference voltage. The analog output
voltage is therefore a positive staircase as shown in Fig. For a 3-bitweighted
resistor DAC. It may be noted that
​ Although the op-amp in Fig. is connected in inverting mode, it can also be
connected in non-inverting mode.
​ The op-amp is simply working as a current to voltage converter.

​ The polarity of the reference voltage is chosen in accordance with the type of the
switch used. For example, for TTL compatible switches, the reference voltage
should be + 5 V and the output will be negative.

4.3 R-2R LADDER DAC

​ A wide range of resistors is required in binary weighted resistor type DAC. This
can be avoided by using R-2R ladder type DAC where only two values of resistors
are required. It is well suited for integrated circuit realization. The typical value
of R ranges from 2.5 kΩ to 10 kΩ.
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​ For simplicity, consider a 3-bit DAC as shown in Fig.(a),where the switch position
d1 d2 d3 corresponds to the binary word 100. The circuit can be simplified to the
equivalent form of Fig. (b) and finally to Fig. (c). Then, voltage at node C can be
easily calculated by the set procedure of network analysis as

​ The switch position corresponding to the binary word 001in 3 bit DAC is shown
in Fig.(a). The circuit can be simplified to the equivalent form of Fig.(b). The
voltages at the nodes (A, B, C) formed by resistor branches are easily calculated in
a similar fashion and the output voltage becomes
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​ In a similar fashion, the output voltage for R-2R ladder type DAC corresponding
to other 3-bit binary words can be calculated.

4.4 SAMPLE AND HOLD CIRCUIT

The Sample and Hold circuit is an electronic circuit which creates the samples of
voltage given to it as input, and after that, it holds these samples for the definite time.
The time during which sample and hold circuit generates the sample of the input
signal is called sampling time. Similarly, the time duration of the circuit during which
it holds the sampled value is called holding time.
Sampling time is generally between 1µs to 14 µs while the holding time can assume
any value as required in the application.

The figure below represents the basic circuit for the sample and hold circuit:
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In the sample mode of the circuit, the switch present is closed, and so this charges
capacitor C, with the instantaneous value of the applied input signal. However, in the
hold mode of the circuit, the switch now gets open, and so no further charging is
possible.
But now at the hold mode, the capacitor holds the charge that was initially being
stored at the time of sample mode.

While the question arises why the stored charge is held by capacitor rather than
being dissipated. So, this is because the circuit has no path for the dissipation of the
stored charge through it.

4.5 ANALOG TO DIDGITAL CONVERTER

The block schematic of ADC shown in Fig. 10.9 provides the function just opposite to
that of a DAC. It accepts an analog input voltage Va and produces an output binary
word d1,d2,..dn of functional value D, so that

Where d1 is the most significant bit and dn is the least significant bit. An ADC usually
has two additional control lines: the START input to tell the ADC when to start the
conversion and the EOC (end of conversion) output to announce when the conversion
is complete. Depending upon the type of application, ADCs are designed for
microprocessor interfacing or to directly drive LCD or LED displays.

ADCs are classified broadly into two groups according to their conversion technique.
Direct type ADCs and Integrating type ADCs. Direct types ADCs compare a given
analog signal with the internally generated equivalent signal. This group includes
✔​ Flash(comparator) type converter
✔​ Counter type converter
✔​ Tracking or servo converter
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✔​ Successive approximation type converter

Integrating type ADCs perform conversion in an indirect manner by first changing the
analog input signal to a linear function of time or frequency and then to a digital code.
The two most widely used integrating type converters are:

(i)​Charge balancing ADC

(ii)​ Dual slope ADC

The most commonly used ADCS are successive approximation and the integrator
type. The successive approximation ADCs are used in applications such as data
loggers and instrumentation where conversion speed is important. The successive
approximation and comparator type are faster but generally less accurate than
integrating type converters. The flash (comparator) type is expensive for a high
degree of accuracy. The integrating type converter is used in applications such as
digital meter, panel meter and monitoring systems where the conversion accuracy is
critical.

The Parallel Comparator (Flash) A/D converter

​ Va is the analog voltage that is converted to digital form.

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​ The corresponding full-scale voltage is V, and different reference voltage levels

V1to V7 have been generated with the help of a resistor network from the
full-scale voltage V.
​ The analog voltage Va is simultaneously compared by seven comparators with
reference voltage levels V1 to V7.
​ Each of the outputs of the comparators is digital in nature and has only two
levels.
​ The seven outputs of the comparators are stored in latches.
​ The seven output latches are converted to 3-bit binary format with the use of a
decoder.
​ The comparator outputs and corresponding digital output for each interval of
analog voltage are given in the table in Figure.
​ The concept and principle of parallel comparator A/D conversion is the simplest
as well as the fastest.
​ Digital output with any number of bit systems for an A/D converter can be
realized by this simple concept of operation.
​ However, as the number of bits for digital output increases, the number of
comparator requirements increases.

​ Here lies the main disadvantage of this type of A/D converter, because the
number of comparators increases exponentially, as for N-bit A/D converters the
number of comparators required is 2N-1.
​ Also,thisincreasesthenumberoflatchesandcomplicationsofthedecodercircuit

Digital ramp ADC:

​ The basic idea is to connect the output of a free-running binary counter to the
input of a DAC, then compare the analog output of the DAC with the analog input
signal to be digitized and use the comparator’s output to tell the counter when to
stop counting and reset.
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​ The following schematic shows the basic idea:

​ As the counter counts up with each clock pulse, the DAC outputs as lightly higher
(more positive) voltage.
​ This voltage is compared against the input voltage by the comparator.
​ If the input voltage is greater than the DAC output, the comparator’s output will
be high and the counter will continue counting normally.
​ ​Eventually, though, the DAC output will exceed the input voltage, causing the
comparator’s output to go low.
​ This will cause two things to happen: first, the high-to-low transition of the
comparator’s output will cause the shift register to ”load” whatever binary count
is being output by the counter, thus updating the ADC circuit’s output; secondly,
the counter will receive a low signal on the active-low LOAD input, causing it to
reset to 00000000 on the next clock pulse.
​ The effect of this circuit is to produce a DAC output that ramps up to whatever
level the analog input signal is at, output the binary number corresponding to
that level, and start over again.

Successive approximation ADC:

​ The only change in this design is a very special counter circuit known as a
successive-approximation register.
​ Instead of counting up in binary sequence, this register counts by trying all values
of bits starting with the most-significant bit and finishing at the least-significant
bit.
​ Throughout the count process, the register monitors the comparator’s output to
see if the binary count is less than or greater than the analog signal input,
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adjusting the bit values accordingly.

​ The way the register counts is identical to the ”trial-and-fit” method of
decimal-to- binary conversion, where by different values of bits are tried from
MSB to LSB to get a binary number that equals the original decimal number.
​ The advantage to this counting strategy is much faster results: the DAC output
converges on the analog signal in put in much larger steps thanwiththe0-to-full
count sequence of a regular counter.
​ The SAR is generally capable of outputting the binary number in serial (one bit at
a time) format, thus eliminating the need for a shift register.
​ Without showing the inner workings of the successive-approximation register
(SAR), the circuit looks like this:

Counting A/D Converter:

​ The schematic diagram of a counting A/D converter is shown in Figure.
​ The comparator output and clock are ANDed by an AND gate and applied to the
clear input of the UP counter.
​ The converter converts the counter output to analog voltage. To start the
conversion, the counter is at there set position, i.e, all the counter output bits are
0.
​ So, D/A converter output is 0 and comparator output Vo is high because of the
application of unknown analog input voltage.
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​ Therefore, clock is enabled and the counter starts counting upward. Since the
number of clock pulses counted increases linearly with time, the D/A converter
output voltage Vr increases, as shown in Figure.
​ The counting process will stop when D/A converter output Vr is higher than
analog input voltage Va (Vr>Va), and comparator output Vo is low to disable the
AND gate.
​ Since no clock pulse is now available, the counter will stop counting and at this
instant digital output is available. Offset voltage may be applied at the input of the
comparator for calibration purpose.
​ It may be noted that the conversion time for a counting A/D converter depends
on counting the number of clock pulses.
​ Therefore, the maximum conversion time for an N-bit converter is the time
lapsed by 2N number of clock pulses. Hence this type of A/D converter is slower
than the previous two types of A/D converters.

Dual-Slope A/D Converter

​ Dual-slope A/D converter is one of the most commonly used types of converter.
​ The schematic diagram of a dual-slope A/D converter is illustrated in Figure. It
consists of the following major functional blocks.
An integrator.
A comparator.
A binary counter.
A switch driver
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•​ The principle of operation can be understood with the help of the

timing diagram in above Figure.
•​ ​ Let us consider, the conversion process starts at time t = 0 with the
switch S1 connected to analog input voltage Va and the N-bit counter is
at cleared state, i.e, its output is all 0s.
•​ Analog voltage is passed through an integrator circuit with time
constant ζ = RC. The integrator output

4.6 DAC/ADC SPECIFICATIONS

​ Both D/A and A/D converters are available with a wide range of specifications.
​ The various important specifications of converters generally specified by the
manufacturers are analyzed.
​ The specifications are Resolution, Linearity, Accuracy, Monotonicity, settling time
and stability.

Resolution:
​ The resolution of a converter is the smallest change in voltage which may be
produced at the output (or input) of the converter.
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​ For example, an 8-bit D/A converter has 28-1 =255 equal intervals. Hence the
smallest change in output voltage is 1/255 of the full scale output range. In short,
the resolution is the value of the LSB.
​ Resolution(in volts)=1LSB increment

Linearity:
​ The linearity of an A/D or D/A converter is an important measure of its accuracy
and tells us how close the converter output is to its ideal transfer characteristics.
​ In an ideal DAC, equal increment in the digital input should produce equal
increment in the analog output and the transfer curve should be linear.

Accuracy:
​ Absolute accuracy is the maximum deviation between the actual converter
output and the ideal converter output.
​ Relative accuracy is the maximum deviation after gain and offset errors have
been removed.

Monotonicity:
​A monotonic DAC is the one whose analog output increases for an increase in
digital input.
A monotonic characteristic is essential in control applications, otherwise
oscillations can result.

Settling time:
​ The most important dynamic parameter is the settling time.
​ It represents the time it takes for the output to settle within a specified band
+or–
½ LSB of its final value following a code change at the input (usually a full scale
change).
​ Settling time ranges from 100ns to10μs depending on word length and type of
circuit used.

Stability:
​ The performance of the converter changes with temperature, age and power
supply variations.
​ So all the relevant parameters such as offset, gain, linearity error and
monotonicity must be specified over the full temperature and power supply
ranges.