Addressing Modes:
The term addressing modes refers to the way in which the operand of an instruction is specified. The addressing mode
specifies a rule for interpreting or modifying the address field of the instruction before the operand is actually executed.
1. Implied mode: In implied addressing the operand is specified in the instruction itself.
2. Immediate addressing mode: In this mode data is present in address field of instruction.
3. Register mode: In register addressing the operand is placed in one of general purpose registers. This register is
specified by the instruction.
4. Register Indirect mode: In this addressing the operand’s offset address is placed in any one of the registers that is
specified in the instruction.
5. Auto Indexed (increment mode/decrement mode): Effective address of the operand is the contents of a register
specified in the instruction.
In increment mode, After accessing the operand, the content of this register is automatically incremented to point to the
next consecutive memory location.
In decrement mode, Before accessing the operand, the contents of this register are automatically decremented to point to
the previous consecutive memory location.
6. Direct addressing/ Absolute addressing Mode: In this addressing mode the 16 bit effective address of the data is
the part of the instruction.
7. Indirect addressing Mode:In this mode address field of instruction contains the address of effective address from
which operand is to be fetched.
8. PC relative addressing mode: In this mode effective address is obtained by adding displacement to PC.
EA = PC + Address field value
9.Indexed addressing mode: The operand’s offset address is the sum of the content of an index register and
displacement specified in the instruction.
10. Base register addressing mode: In this mode effective address is obtained by adding base register value to address
field value.
EA = Base register + Address field value.
Micro-operations are the functional, or atomic,
operations of a processor.
Each micro-operation involves the movement of
data into or out of a register. So long as these
movements do not interfere with one another,
several of them can take place during one step,
saving time.
The notation (t1, t2, t3) represents successive time
units.
Consists of three steps and four micro-operations.
Sequence of events are:
t1: MAR (PC)
t2: MBR Memory
PC (PC) + I
t3: IR (MBR)
where I is the instruction length.
In words, First time unit: Move contents of PC to MAR.
Second time unit: Move contents of memory location
specified by MAR to MBR. Increment by I the contents of the
PC. Third time unit: Move contents of MBR to IR.
Consists of three steps and four micro-operations.
Sequence of events are:
t1: MBR (PC)
t2: MAR Save_Address
PC Routine_Address
t3: Memory (MBR)
In the first step, the contents of the PC are transferred to the
MBR, so that they can be saved for return from the interrupt.
Then the MAR is loaded with the address at which the
contents of the PC are to be saved, and the PC is loaded with
the address of the start of the interrupt-processing routine.
The final step is to store the MBR, which contains the old
value of the PC, into memory.
First, consider an add instruction:
ADD R1, X which adds the contents of the location X to register R1.
Sequence of events are:
t1: MAR (IR(address))
t2: MBR Memory
t3: R1 (R1) + (MBR)
Second, A common instruction is increment and skip if zero:
ISZ X
The content of location X is incremented by 1. If the result is 0, the next
instruction is skipped.
Sequence of events are:
t1: MAR (IR(address))
t2: MBR Memory
t3: MBR (MBR) + 1
t4: Memory (MBR)
If ((MBR) = 0) then (PC (PC) + I)
Note: The new feature introduced here is the conditional action. This test
and action can be implemented as one micro-operation.
Third, consider a branch- and-save-address instruction:
BSA X
The address of the instruction that follows the BSA instruction
is saved in location X, and execution continues at location X +
I. The saved address will later be used for return.
Sequence of events are:
t1: MAR (IR(address))
MBR (PC)
t2: PC (IR(address))
Memory (MBR)
t3: PC (PC) + I
The address in the PC at the start of the instruction is the
address of the next instruction in sequence. This is saved at
the address designated in the IR. The latter address is also
incremented to provide the address of the instruction for the
next instruction cycle.
COA Notes
Q. Microinstruction Sequencing and Execution:
Dual-field:
Single-field:
Compiled by Prof. Anas Dange #9022873433 Mail to: [email protected] Page 1
