31/05/2023

Chihuahua Technological Institute 1

Subject: Digital Design

Teacher: José Luis Guillermo Bañuelos
Unit 5 sequential logic
Integrantes
Bryan Isaac Aquino Trejo (18060053)
Luis Ángel Martínez Leon (19061000)
 Index
Introduction. 3
Sequential Logic. 3
Fundamentals of sequential elements.............................................................................4
Block diagram of a sequential circuit..........................................................4
Asynchronous. 4
Asynchronous systems of thetby gates..........................................................................5
Synchronous
Flip-Flop's. 6
NAND and NOR Latch
Basic circuits with NOR gates..............................................................7
Basic circuit with NAND gate............................................................8
Flip Flop R-S, J-K, D and T. 9
R-S:.................................................................................................................................... 9
J-K:................................................................................................................................... 10
. 10
Counters and registers.11
Registration:........................................................................................................................... 11
Counter:........................................................................................................................ 12
Analysis of Synchronous Sequential Circuits..................................................13
Design of Synchronous Sequential Circuits.........................................................................13
Bibliographic References...........................................................................................14
Okay happy, S., Caballero, A. H., Pérez MartNez, J., Castro Gil, M. (2006) Electronics
Digital: Introduction to digital logic...............................................................................14
Introduction
Sequential Logic is the method of ordering actions,
reasoning, and expression of machinery, equipment, and automation
processes. And their interrelation with man. This consequently gives us the
binomials, man-machine, man-process.

Every digital system must have combinational circuits, most of

the systems also include memory elements, which require
that the system is described in terms of sequential logic.

Memory elements are capable of storing binary information.

within them. The binary information stored in the elements of
memory at a given time defines the state of the sequential circuit. The
sequential circuit receives the binary information from the external inputs.

Sequential Logic.
A timed sequential circuit consists of a group of FF (flip-flops) and a circuit
combinational connected to each other with feedback.
An MSI circuit that has storage cells within it and is classified by the
functions they perform, and there are mainly three: records, counters, and units of
memory.
Fundamentals of sequential elements.
A sequential logic circuit is one whose outputs depend not only on its inputs.
current ones, but also of their position or current state, stored in elements of
memory.
Block diagram of a sequential circuit.
It consists of a combined circuit and storage elements that together
They form a feedback system
Storage elements are devices that can store
binary information inside it (1's and 0's).
The stored binary information defines the state of the sequential circuit.
The sequential circuit receives external binary input information, which
together with the current state stored in memory determines the binary value
of the outputs, as well as the condition to change the state of the circuit.

Asynchronous.
An asynchronous sequential circuit is one whose state can be affected at any time.
Instantly when changing the value of the inputs.

Its storage elements are devices with time delay, in which the
The storage capacity is due to the fact that the signal takes a finite time to propagate.
through the device.
Asynchronous systems of the gate type.
The storage elements consist of logic gates where the time of
signal propagation provides the required storage space.
Therefore, an asynchronous sequential circuit can be considered as a circuit
combinational with feedback.
Due to the feedback between logic gates, the system can operate on
unpredictable manner and sometimes even become unstable, which is why they are used in
very few occasions.
Synchronous

The outputs of the storage elements change only when there is a

watch pulse
The asynchronous sequential circuits that use clock pulses at the input of
storage elements are called sequential circuits
clock-controlled and sontpos that are found more frequently in the
practice as they rarely present instability issues.

Flip-Flops
The storage elements used in asynchronous sequential circuits
They are called bistables to latch (locks, safes or bolts), which are
storage devices of a bit that can change its value independently of
a clock signal.
NAND and NOR latch
A Flip-Flop circuit can be built with two NAND gates or two NOR gates.
The connection and cross coupling through the output of a gate to the input
Another constitutes a feedback trajectory.
For this reason, the circuits are classified as asynchronous sequential. Each FLIP-Flop
It has two outputs Q and Q', and two inputs SET to adjust and RESET to restore. To this
The Flip-Flop type is called directly coupled or secure RS.
Basic circuits with NOR gates.

Invalid state.
When a 1 is applied to both inputs of the flip-flop, both the output Q and Q' will go to 0.
This condition violates the fact that the outputs are complementary. This means 0 that the
outputs will no longer be the generation of one another.
Initial state:
Assuming: S=0, R=0, Q=0 and Q´=1. If at a certain moment we change the
Input S from 0 to 1, the output of gates 1 (Q') will change from 1 to 0. How is this output?
also one of the inputs of gate 2, having a 0 and a 0 as input, its
output (Q) will go from 0 to 1. As before, now the output of gate 2 (Q) is one of the
gate inputs 1. As there was a change from 0 to 1 we must see what effect
keep this at the output of gate 1. The inputs are 1 and 1 to which the gate
NOR will respond with a 0 at the output (Q´).

Basic circuit with NAND gate

R-S, J-K, D, and T Flip Flops
R-S:
The RS Flip Flop is considered one of the most basic sequential logic circuits.
The Flip flop is a bistable memory device of one bit. It has two inputs, one is
Call Set that configures the device (output = 1) and is labeled as S and is known
how to restart that will reset the device (output = 0) labeled as R. The RS
means SET/RESET.
The Flip-Flop resets to its original state with the help of the RESET input and the output.
It is Q, which will be at logical level 1 or at logical level 0. It depends on the condition.
established/reestablished of the flip flop. The word flip flop means that it can be Jumped in
a logical state or Flopped again in another.
A basic NAND RS flip-flop circuit is used to store data and, for
thus, it provides feedback from both outputs back to their inputs. The
The RS flip flop actually has three inputs: SET, RESET, and its current output Q in relation to
its current state.

Truth table
J-K:
A JK flip-flop is a sequential memory device of two states of a single bit that
it is named after its inventor Jack Kil. In general, it has a clock input pin.
(CLK), two data input pins (J and K) and two output pins (Q and Q'). The JK flip-flop
it can be activated at the leading edge of the clock or at its trailing edge and therefore
They can be activated by positive or negative edge respectively.

D:
The flip flop D is a memory element that can store information in the form
of a logical 1 or 0. This flip-flop has a D input and two outputs Q and Q'. It also has
a clock input that in this case indicates that it is a dispersed FF by the edge or
descending edge. If the flip flop is triggered by the rising edge it would only appear the
triangle.
The flip flop additionally has two asynchronous inputs that allow you to set the
output Q of the flip flop, a desired output regardless of the D input and the clock state.
These entries are:
PRESET (put) and
CLEAR
It is important to note that these are active entries at a low level. Being active at a low level.
means that:
To set a 1 on the output Q, a 0 must be placed on the PRESET input.
Counters and registers
Registered:
Sets of bistables that function in unison by sharing their signals.
control.
Typically, registers formed by D-type flip-flops are used, or with
S-R or J-K flip-flops functioning as D flip-flops.
The registers need a level (latch) or edge synchronization signal.
Unlike counters, they do not have a specific sequence of states.

Applications: storage and movement of data

Types of records

Most common lines in the records:

Parallel input: each flip-flop has its own input bit.
Parallel output: each flip-flop provides its own output bit.
Input series: the input occurs bit by bit, always through the same flip-flop.
Output series: the output occurs bit by bit, always through the same bistable.
Clock: it can be active by white or by level.
Clock inhibition/enabling: blocks/enables the register inputs. (CE)
Clear (reset to 0): asynchronous input (usually) common to all
biestables.
Preset (set to 1): asynchronous input (usually) common to all
biestables.
Inhibition/enabling of the output: disconnect/enable the output of the register. (OE)
Counter:
A counter is a sequential circuit that generates an ordered sequence of outputs that
It repeats in the tempo. The output matches the state of its bistables. The counters
they are sequential circuits that count clock edges.
Types of counters
Synchronous: all flip-flops share the same clock signal
Asynchronous: not all flip-flops share the same clock signal.
Ascending: the count is increasing.
Descending: the count is decreasing
Reversible: the account can be ascending or descending depending on a
control entry.
Counter module 2n: it has n flip-flops and counts from 0 to 2n-1.
Counter A-B: counts from A to B, where A can be different from 0 and B can
to be different from 2n-1.
Frequency divider: from a clock with a given frequency, it returns a bit.
which is worth 1 in one out of every N cycles and 0 in the remaining ones.

Asynchronous counters
They are also called propagation counters or ripple counters. A signal is applied.
external to the clock input of the first flip-flop and to the following ones it is applied as
clock signal from the previous bistable. The bistables do not trigger at the same time.
due to the delay of the gates, spurious states with values can occur
incorrect, and the clock frequency of the counter is limited.

Synchronous counters
In them all the bi-stables share the same clock and switch at the same time. Registers and
standard synchronous counter entry types: Clock signal (C)
Account activation (CE)
End of account (TC, RCO or CEO): it is set to 1 when the counter reaches the end of the
accounts.
If the count is ascending, the end is 2n-1.
If the count is descending, the end is 0.
CEO (RCO) is activated only if CE is active.
Reset (CLEAR): synchronous or asynchronous.
Parallel load enable (L, LOAD): enables the loading of an n-bit data
the counter to count from it (usually synchronous load).
 Parallel load inputs (Di): are used to introduce an n-bit value if LOAD
is activated.
Ascending/descending count (UP/DOWN): in reversible counters.

Analysis of Synchronous Sequential Circuits

The analysis of a synchronous sequential circuit consists of the transition from a description
structural of a circuit using flip-flops and logic gates to a functional description
from an FSM, mainly a state table, and from there a state diagram or a
VHDL description.

Design of Synchronous Sequential Circuits

When starting the design of any digital circuit, it must be treated as
a 'black box' and its inputs and outputs must be defined. In the case of circuits
synchronous sequential must add two additional inputs such as the clock input
(CLK) and the system startup one. The latter allows the system to be restarted as soon as it is
actvada.

Once all the input and output variables have been specified, it can be further specified in
detail the design, representing them in the corresponding Block Diagram of the
General Structure of synchronous sequential circuits based on two blocks.
One composed of a combinational circuit and another by a memory circuit connected together.
both through a feedback. The memory block is composed of flip-flops,
how could JK-type flip-flops be.
The study of the procedure for designing synchronous sequential circuits is conducted
through the application to a simple example. The points to develop are:
Reading the problem and defining variables.
Construction of the table diagram and states.
Minimization of states and obtaining the equivalent table that contains the
minimum number of states.
Determination of the number of FFs needed and complete the excitation maps
of the selected FF.
Assignment of states and generation of state transition and output tables.
Derivation of the equations for combinational circuits. Implementation
of the sequential circuit.
All steps are completely automatable as they are exact algorithms.
except for the second one which requires some intuition from the logical designer. Thus,
special effort must be invested in understanding the problem so that it becomes clearer
the realization of the corresponding state diagram is simple.

Bibliographic References
Acha Alegre, S., Caballero, A. H., Pérez Martnez, J., Castro Gil, M. (2000) Digital Electronics:
Introduction to digital logic.