EXPERIMENT 4
REGISTERS AND MEMORY BLOCKS
N J AJMAL
1. Register file
AIM
32 element 32-bit register file holding registers x0 -x31. Register x0 is hardwired to 0. The
register file has two read port and one write port. Read ports have 5-bit address inputs A1
and A2. The 32-bit values in the specified registers are read out of the output port RD1 and
RD2. If the WE3 is asserted the register file writes the data ( WD3) into the specified register
(A3) on the rising edge of the clock.
PROCEDURE
• Make a folder named as “Register_File” and open a terminal in that folder then open
test editor using "gedit" command.
• Write verilog code in behavioural modal & testbench in text editor with file name as
regfile.v & regfile_str _tb.v especially and save codes.
• Select "multiple steps" In NCLaunch tab window.
• Click on "Create cds.lib file".
• Name the file ( choose default name cds.lib ) and save.
• Select " Don't include any libraries (verilog design)" Then click "Ok".NCL launch
simulation tab window will be open.
• Select and compile regfile.v and regfile _tb.v using Launch Complier.
• On the right tab, Select the testbench under worklib and select the elaborate button
on the top Tab and launch Elaboration.
• On the Right Window, select testbench module under Snapshots and click on the
Launch Simulator.
• Design Browser-1 Window will open then select testbench then select the required
inputs to be added to the wave form then Select Add waveform, a wave form
window appears.
• Click on testbench then click on “add waveform”, then waveform window will be
open.
• Click on “Run Simulation” them obtain the waveform.
• To obtain schematic diagram Select schematic button from Design browser-1
window to view the schematic.
CODES
Verilog code
Testbench
OBSERVATIONS
Output
Waveform
RESULT
The 32 × 32-bit register file was successfully designed, implemented, and verified through
simulation. The two asynchronous read ports correctly provided the contents of the
addressed registers. The synchronous write port accurately updated the selected register on
the rising clock edge when WE3 was asserted. Attempts to write into register x0 were
ignored, confirming that it remains hardwired to zero. The simulation results validate that
the register file performs all read and write operations as expected.
2. Instruction Register
AIM
32 bit instruction address input A that reads 32 bit data on to from the address onto the
read data output
PROCEDURE
• Make a folder named as “Instruction_Memory” and open a terminal in that folder
then open test editor using "gedit" command.
• Write verilog code in behavioural modal & testbench in text editor with file name as
instr_reg.v instr_reg _tb.v especially and save codes.
• Select "multiple steps" In NCLaunch tab window.
• Click on "Create cds.lib file".
• Name the file ( choose default name cds.lib) and save.
• Select " Don't include any libraries (verilog design)" Then click "Ok".NCL launch
simulation tab window will be open.
• Select and compile instr_reg.v and instr_reg _tb.v using Launch Complier.
• On the right tab, Select the testbench under worklib and select the elaborate button
on the top Tab and launch Elaboration.
• On the Right Window, select testbench module under Snapshots and click on the
Launch Simulator.
• Design Browser-1 Window will open then select testbench then select the required
inputs to be added to the wave form then Select Add waveform, a wave form
window appears.
• Click on testbench then click on “add waveform”, then waveform window will be
open.
• Click on “Run Simulation” them obtain the waveform.
• To obtain schematic diagram Select schematic button from Design browser-1
window to view the schematic.
CODES
Verilog code
Testbench
OBSERVATIONS
Output
Waveform
RESULT
The 32-bit wide instruction memory was successfully implemented and tested. The memory
returned the correct instruction corresponding to the supplied word-aligned address. The
simulation confirmed that the initialized instructions were fetched properly, including the
custom test values, while unused addresses returned zero. The instruction memory behaves
as a ROM, providing correct read-only access at all valid addresses.
3. Data Memory
AIM
A data memory has a single read/write port. If Write Enable (WE) is asserted, then it write
WD into address A on rising edge of the clock. If WE is 0, then, then it reads from address A
onto the read data bus RD.
PROCEDURE
• Make a folder named as “Data_Memory” and open a terminal in that folder then
open test editor using "gedit" command.
• Write verilog code in behavioural modal & testbench in text editor with file name as
data_mem.v & data_mem _tb.v especially and save codes.
• Select "multiple steps" In NCLaunch tab window.
• Click on "Create cds.lib file".
• Name the file ( choose default name cds.lib )and save.
• Select " Don't include any libraries (verilog design)" Then click "Ok".NCL launch
simulation tab window will be open.
• Select and compile data_mem.v and regfile data_mem _tb.v using Launch Complier.
• On the right tab, Select the testbench under worklib and select the elaborate button
on the top Tab and launch Elaboration.
• On the Right Window, select testbench module under Snapshots and click on the
Launch Simulator.
• Design Browser-1 Window will open then select testbench then select the required
inputs to be added to the wave form then Select Add waveform, a wave form
window appears.
• Click on testbench then click on “add waveform”, then waveform window will be
open.
• Click on “Run Simulation” them obtain the waveform.
• To obtain schematic diagram Select schematic button from Design browser-1
window to view the schematic.
CODES
Verilog code
Testbench
OBSERVATIONS
Output
Waveform
RESULT
The 32-bit wide single-port data memory was successfully designed and verified. The
simulation confirmed that data was correctly written into the specified address on the rising
edge of the clock when the write enable signal was asserted. Subsequent read operations
provided the expected data values. Locations that were not explicitly written remained at
zero. The results confirm that the data memory performs correct read and write operations.
4. Synchronous FIFO
AIM
Synchronous FIFO with width of M=16 bytes and depth N=32. FIFO will have the following
signals.
• wr_en: write enable
• wr_data: write data
• full: FIFO is full
• empty: FIFO is empty
• rd_en: read enable
• rd_data: read data
• rst_n: reset
M and N should be parameters that can be changed.
PROCEDURE
• Make a folder named as “Synchronous_FIFO” and open a terminal in that folder then
open test editor using "gedit" command.
• Write verilog code in behavioural modal & testbench in text editor with file name as
sync_fifo.v & sync_fifo _tb.v especially and save codes.
• Select "multiple steps" In NCLaunch tab window.
• Click on "Create cds.lib file".
• Name the file ( choose default name cds.lib) and save.
• Select " Don't include any libraries (verilog design)" Then click "Ok".NCL launch
simulation tab window will be open.
• Select and compile sync_fifo.v and sync_fifo _tb.v using Launch Complier.
• On the right tab, Select the testbench under worklib and select the elaborate button
on the top Tab and launch Elaboration.
• On the Right Window, select testbench module under Snapshots and click on the
Launch Simulator.
• Design Browser-1 Window will open then select testbench then select the required
inputs to be added to the wave form then Select Add waveform, a wave form
window appears.
• Click on testbench then click on “add waveform”, then waveform window will be
open.
• Click on “Run Simulation” them obtain the waveform.
• To obtain schematic diagram Select schematic button from Design browser-1
window to view the schematic.
CODES
Verilog code
Testbench
OBSERVATIONS
Output
Waveform
RESULT
The parameterized synchronous FIFO (16-bit width, 32-depth) was successfully
implemented and tested. The simulation showed that data was written into the FIFO when
wr_en was asserted and correctly read out in the same order when rd_en was enabled,
demonstrating first-in first-out behavior. The full and empty status flags operated correctly,
preventing invalid writes and reads. The results confirm that the FIFO design functions
properly with correct enqueue and dequeue operations.
