Shweta K.

Borse

1. Evolution of Intel Microprocessors

1.1 Introduction

Intel has been a pioneer in microprocessor development since 1971. The evolution
of Intel’s microprocessors shows how performance, complexity, and integration

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have increased over time, from 4-bit processors to multi-core hybrid
architectures.

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1.2 Timeline of Intel Microprocessors

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Year Microprocessor Features

1971 Intel 4004 4-bit, first commercial

microprocessor, 740 KHz, used in
calculators
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1974 Intel 8080 8-bit, clocked at 2 MHz, used in early
computers
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1978 Intel 8086 16-bit, beginning of x86 architecture

1982 Intel 80286 Introduced protected mode and

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memory management

1985 Intel 80386 32-bit, virtual memory, multitasking

support
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1989 Intel 80486 Integrated FPU, pipelining

1993 Pentium (P5) Superscalar architecture, dual

pipelines, MMX instructions

1995–200 Pentium Pro to Pentium 4 Transition to 64-bit, increased clock

5 speeds

Shweta K. Borse​
R. H. Sapat College Of ENGG. Management Studies and Research, Nashik
Shweta K. Borse

2006 Core Architecture (Core Multi-core CPUs, improved

Duo, Core 2 Duo) performance per watt

2010s Core i3/i5/i7/i9 Hyper-threading, Turbo Boost,

integrated GPU

2021 Hybrid Architecture Mix of performance and efficiency

onwards (Alder Lake) cores (big.LITTLE)

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1.3 Key Trends in Evolution

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●​ Increase in word size (from 4-bit to 64-bit)​

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●​ Integration of multiple cores​

●​ Improved power efficiency​

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●​ Addition of specialized instructions (SSE, AVX)​

●​ On-chip GPUs and AI accelerators

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2. Microprocessor vs Microcontroller
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2.1 Microprocessor

●​ A microprocessor is a general-purpose CPU.​

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●​ It performs computing tasks and needs external components (RAM, ROM,

I/O) to function.​

●​ Used in desktops, laptops, and servers.​

2.2 Microcontroller
Shweta K. Borse​
R. H. Sapat College Of ENGG. Management Studies and Research, Nashik
Shweta K. Borse

●​ A microcontroller is a compact integrated circuit that includes a CPU, RAM,

ROM, and I/O ports in a single chip.​

●​ Designed for specific control applications.​

●​ Used in embedded systems like home appliances, IoT devices, robots.

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2.3 Comparative Table

Feature Microprocessor Microcontroller

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Components CPU only CPU + RAM + ROM + I/O

Cost High Low

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Size Larger (requires more Small (single chip)

components)
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Power High Low

Consumption

Performance High for complex tasks Sufficient for simple control

tasks

Application PCs, servers, smartphones Embedded systems,

automation, IoT

Shweta K. Borse​
R. H. Sapat College Of ENGG. Management Studies and Research, Nashik
Shweta K. Borse

3. Intel x86 (Pentium) Architecture

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3.1 Overview

Pentium processors belong to Intel’s x86 family and are based on CISC (Complex
Instruction Set Computing). They are known for their high performance due to
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complex instruction sets, pipelining, and superscalar execution.

3.2 Architecture Features

●​ Superscalar: Multiple instructions executed per cycle​

Shweta K. Borse​
R. H. Sapat College Of ENGG. Management Studies and Research, Nashik
Shweta K. Borse

●​ Instruction Pipelining: Overlapping instruction stages (fetch, decode,

execute)​

●​ Integrated FPU (Floating Point Unit)​

●​ MMX, SSE instructions for multimedia processing​

●​ 32-bit and later 64-bit addressing (with x86_64)​

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3.3 Key Registers

Register Purpose

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EAX, EBX, ECX, EDX General-purpose

EIP Instruction Pointer (points to next instruction)

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ESP Stack Pointer

EBP Base Pointer

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EFLAGS Status flags (Zero, Carry, Overflow, etc.)

CS, DS, SS, ES, FS, GS Segment registers (memory segmentation)

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3.4 Instruction Types

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Shweta K. Borse​
R. H. Sapat College Of ENGG. Management Studies and Research, Nashik
Shweta K. Borse

●​ Data Movement: MOV, PUSH, POP, XCHG​

●​ Arithmetic: ADD, SUB, MUL, DIV, INC, DEC​

●​ Logical: AND, OR, XOR, NOT, TEST​

●​ Control Flow: JMP, CALL, RET, JZ, JNZ, LOOP​

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●​ String Operations: MOVS, LODS, STOS

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1. Data Movement Instructions

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These instructions are used to transfer data between registers, memory, or I/O
ports. They do not modify the data but move it from one place to another.

MOV – Move data

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Syntax:

MOV destination, source

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Description:​
Transfers data from the source operand to the destination operand.
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Example:

MOV AX, BX ; Copies contents of BX into AX

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Diagram:

Before: AX = ???? BX = 1234h

MOV AX, BX

After: AX = 1234h BX = 1234h

PUSH – Push to Stack

Shweta K. Borse​
R. H. Sapat College Of ENGG. Management Studies and Research, Nashik
Shweta K. Borse

Syntax:

PUSH source

Description:​
Decreases the stack pointer (SP) by 2 (in 16-bit mode) and stores the source
operand at the new top of the stack.

Example:

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PUSH AX

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Diagram:

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Stack grows downward

Before:
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SP -> 1000h

[1000h] = ????
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PUSH AX:

SP = SP - 2 = 0FFEh
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[0FFEh] = AX

POP – Pop from Stack

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Syntax:

POP destination

Description:​
Reads the 16-bit value from the top of the stack into the destination, and then
increments SP by 2.

Shweta K. Borse​
R. H. Sapat College Of ENGG. Management Studies and Research, Nashik
Shweta K. Borse

Example:

POP BX

Diagram:

[SP] = value

POP BX:

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BX = [SP]

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SP = SP + 2

XCHG – Exchange values

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Syntax:

XCHG operand1, operand2

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Description:​
Exchanges the values of two operands (either both registers or one register and
one memory location).
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Example:

XCHG AX, BX
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Diagram:

Before: AX = 1234h, BX = 5678h

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After: AX = 5678h, BX = 1234h

2. Arithmetic Instructions
These instructions perform mathematical operations on data.

ADD – Addition
Shweta K. Borse​
R. H. Sapat College Of ENGG. Management Studies and Research, Nashik
Shweta K. Borse

Syntax:

ADD destination, source

Description:​
Adds source to destination, and stores the result in destination.

Example:

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ADD AX, BX

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Diagram:

AX = 0005h, BX = 0003h

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ADD AX, BX

Result: AX = 0008h
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SUB – Subtraction

Syntax:
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SUB destination, source

Description:​
Subtracts source from destination, and stores the result in destination.
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Example:

SUB AX, BX
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MUL – Unsigned Multiplication

Syntax:

MUL source

Description:​
Multiplies AL or AX by source. Result is stored in AX or DX:AX.
Shweta K. Borse​
R. H. Sapat College Of ENGG. Management Studies and Research, Nashik
Shweta K. Borse

Example (8-bit):

AL = 02h, source = 03h

MUL BL

Result: AX = 0006h

DIV – Unsigned Division

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Syntax:

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DIV source

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Description:​
Divides AX by source. Stores the quotient in AL, and the remainder in AH.

Example:
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AX = 0006h, source = 02h

DIV BL
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Result: AL = 03h, AH = 00h

INC / DEC – Increment / Decrement

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Syntax:

INC AX ; AX = AX + 1
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DEC BX ; BX = BX - 1

These affect the flags except the Carry flag.

3. Logical Instructions

Shweta K. Borse​
R. H. Sapat College Of ENGG. Management Studies and Research, Nashik
Shweta K. Borse

These operate at the bit level and are often used in conditions, masking, or
testing.

AND – Bitwise AND

Syntax:

AND destination, source

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Description:​
Performs logical AND operation between each bit of destination and source.

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Example:

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AX = 1100 0001b

BX = 1010 1100b

AND AX, BX
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Result: AX = 1000 0000b

OR – Bitwise OR
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Syntax:
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OR destination, source

Performs logical OR operation between the bits.

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XOR – Bitwise Exclusive OR

Syntax:

XOR destination, source

Performs logical XOR operation between the bits.

Shweta K. Borse​
R. H. Sapat College Of ENGG. Management Studies and Research, Nashik
Shweta K. Borse

NOT – Bitwise Inversion

Syntax:

NOT destination

Description:​
Inverts all bits of the operand.

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TEST – Logical AND (no result stored)

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Syntax:

TEST destination, source

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Description:​
Performs a bitwise AND like AND, but does not store the result — only affects
flags.
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Used for condition checks.

4. Control Flow Instructions

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These manage how instructions are executed — sequentially or conditionally.

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JMP – Unconditional Jump

Syntax:
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JMP label

Description:​
Changes instruction pointer to label, causing a jump.

CALL – Call Procedure

Syntax:

Shweta K. Borse​
R. H. Sapat College Of ENGG. Management Studies and Research, Nashik
Shweta K. Borse

CALL label

Description:​
Pushes return address on the stack, then jumps to the procedure at label.

RET – Return from Procedure

Syntax:

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RET

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Description:​
Pops return address from the stack and jumps back to that address.

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JZ / JNZ – Conditional Jumps

JZ: Jump if Zero (ZF = 1)​

JNZ: Jump if Not Zero (ZF = 0)
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Usage:

CMP AX, BX
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JZ EqualLabel

Explanation:
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●​ CMP subtracts operands and sets flags.​

●​ JZ checks if Zero Flag is set (meaning AX == BX).

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LOOP – Loop with Counter

Syntax:

LOOP label

Shweta K. Borse​
R. H. Sapat College Of ENGG. Management Studies and Research, Nashik
Shweta K. Borse

Description:​
Decrements CX, and jumps to label if CX is not zero.

Example:

MOV CX, 5

LOOP_START:

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; Some instructions

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LOOP LOOP_START

5. String Operation Instructions

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Used for handling blocks of data stored in memory, typically for string or buffer
processing. They use implicit registers: SI, DI, AX, CX, etc.
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MOVS / MOVSB / MOVSW – Move String

Syntax:
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MOVSB ; Move byte from [SI] to [DI]

MOVSW ; Move word

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Description:​
Moves data from [DS:SI] to [ES:DI], then increments or decrements SI and DI
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based on Direction Flag.

LODS / LODSB / LODSW – Load String

Syntax:

LODSB

Shweta K. Borse​
R. H. Sapat College Of ENGG. Management Studies and Research, Nashik
Shweta K. Borse

Description:​
Loads byte at [SI] into AL, and adjusts SI.

STOS / STOSB / STOSW – Store String

Syntax:

STOSB

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Description:​
Stores value from AL to [DI], then adjusts DI.

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Note on REP prefix:

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Many of the string instructions are used with REP, which repeats the instruction
CX times.

Example:
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MOV CX, 10

REP MOVSB ; Move 10 bytes from [DS:SI] to [ES:DI]

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4. ARM Cortex Architecture

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4.1 Overview

ARM (Advanced RISC Machine) is based on RISC (Reduced Instruction Set

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Computing) principles. It offers high performance with low power consumption,

ideal for mobile and embedded applications.

4.2 RISC Principles

●​ Simple, fixed-length instructions​

Shweta K. Borse​
R. H. Sapat College Of ENGG. Management Studies and Research, Nashik
Shweta K. Borse

●​ Load/store architecture (only load and store access memory)​

●​ Fewer addressing modes​

●​ One clock cycle per instruction (ideally)​

4.3 ARM Cortex Families

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●​ Cortex-A: Application processors (smartphones, tablets)​

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●​ Cortex-M: Microcontrollers (IoT, automotive, industrial)​

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●​ Cortex-R: Real-time systems (safety-critical devices)​

4.4 Use in Mobile AI

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●​ Supports NEON for SIMD operations​

●​ Efficient for running TensorFlow Lite, ONNX​

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●​ Widely used in edge AI applications: object detection, speech processing,

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face recognition​

4.5 Instruction Set

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●​ ARM (32-bit), Thumb (16-bit), Thumb-2 (mixed)​

●​ Common instructions: MOV, ADD, SUB, CMP, B, LDR, STR​

Diagram:

●​ ARM pipeline stages (Fetch → Decode → Execute → Memory → Write-back)

Shweta K. Borse​
R. H. Sapat College Of ENGG. Management Studies and Research, Nashik
Shweta K. Borse

●​ Comparison between ARM and x86 (RISC vs CISC)

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5. NVIDIA Jetson Platform

5.1 Overview
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NVIDIA Jetson is a family of embedded computing platforms built for AI at the

edge, combining CPU, GPU, and AI accelerators on a single board.

5.2 Architecture

●​ GPU-based parallel processing​

Shweta K. Borse​
R. H. Sapat College Of ENGG. Management Studies and Research, Nashik
Shweta K. Borse

●​ ARM Cortex-A cores as CPUs​

●​ CUDA cores for running deep learning models​

●​ Tensor Cores for accelerated matrix operations​

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5.3 Popular Jetson Boards
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Model Use Case Specs

Jetson Nano Entry-level AI education Quad-core ARM, 128-core GPU

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Jetson Robotics, drones 6-core ARM, 384-core Volta GPU

Xavier NX

Jetson AGX Advanced robotics, Up to 12-core ARM, 2048-core

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Orin autonomous systems GPU, Tensor cores

5.4 Applications in Robotics & Edge AI

●​ Real-time inference: object detection, path planning​

●​ Supports ROS (Robot Operating System)​

Shweta K. Borse​
R. H. Sapat College Of ENGG. Management Studies and Research, Nashik
Shweta K. Borse

●​ Integration with AI frameworks: TensorFlow, PyTorch, ONNX, OpenCV

6. Simple Code Examples

6.1 Intel x86 Assembly (NASM Syntax)
section .text
global _start

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_start:
mov eax, 5 ; Load 5 into EAX
add eax, 3 ; Add 3

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mov ebx, eax ; Copy result to EBX
; Exit
mov eax, 1
int 0x80
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6.2 ARM Assembly (Keil / GCC)
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.global _start

_start:
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MOV R0, #5 ; Load 5 into R0

ADD R0, R0, #3 ; Add 3
; Exit (platform-dependent)
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6.3 C Code (Cross-platform)

#include <stdio.h>

int main() {
int a = 5, b = 3;
int result = a + b;

Shweta K. Borse​
R. H. Sapat College Of ENGG. Management Studies and Research, Nashik
Shweta K. Borse

printf("Result: %d\n", result);

return 0;
}

Summary
Topic Core Concepts

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Evolution of Intel Progression from simple CPUs to hybrid,

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Microprocessors multi-core designs

Microprocessor vs CPU-centric vs system-on-chip, cost and power

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Microcontroller tradeoffs

Intel x86 (Pentium) CISC design, complex instructions, multitasking

ARM Cortex RISC design, energy-efficient, optimized for

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mobile/embedded AI

NVIDIA Jetson AI edge platform, GPU-based processing for

robotics
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Assembly/C Examples Show how

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Shweta K. Borse​
R. H. Sapat College Of ENGG. Management Studies and Research, Nashik