System Design Using FPGA
Uploaded by
akshat28 mittalSystem Design Using FPGA
Uploaded by
akshat28 mittalSystem Design using FPGA:
Introduction to course
Course Instructor:
Dr. Rituparna Choudhury
Course Details
Credits: 4 (3-0-1)
Offered by: ECE
Eligible programs: iM.Tech, M.Tech, Ph.D.
Pre-requisites:
• Digital Electronics/ Digital Circuit Design
• Verilog HDL
• VLSI Design (optional)
Assessment Plan
MidTerm exam 20%
Assignments or Projects 40%
4 Assignments
EndTerm exam 30%
Attendance 10%
Assignment Guidelines
• Number of assignments: 4
• Distributed over 4 months
• Mostly Verilog HDL codes
• Submission time: at least 2 weeks
• Late submission penalty: 50% of the assignment marks
Classroom Guidelines
• Attendance proxy will lead to strict action: marks penalty or grade
demotion.
• Carry laptops in all classes: Xilinx Vivado (licensed) should be installed
• Attendance weightage: (1 Mark to be deducted for each proxy)
• 80-100% - 10
• 70-79%-8
• 60-69%-6
• 50-59%-4
• <50- 0
Course Focus
• Primary: Enabling learners to implement digital circuit design on FPGA.
• Enabling learners to design power efficient/ area efficient/ high-speed
architectures.
• Hands on experience with Basys-3 board.
• Efficient HDL coding for error-free design sign-off.
Overview of contents
1. Introduction to HDL
2. Design of Arithmetic architectures
3. Multiplier-less Design: Distributed Arithmetic and Offset Binary Coding
4. Architecture design techniques: Serial, parallel and pipeline
5. Folding architectures
6. Unfolding architectures
7. Systolic Array design: Processing Element
8. Retiming techniques
9. CORDIC Architecture (if time permits)
10. CSD and high radix operations (if time permits)
11. Timing in Digital design
12. Introduction to FPGA Architecture
13. Introduction to High Level Synthesis
References:
• VLSI Digital Signal Processing Systems: Design and Implementation- Keshab K. Parhi
• FPGA Based System Design- Wayne Wolf
• A Verilog Primer- J. Bhasker
• Advanced Digital Design with the Verilog HDL- Michael D. Ciletti
Course TAs:
• A. Nishith : [email protected]
