Standard Cell VLSI Design: A Tutorial

A. J. Kessler and A. Ganesan

ABSTRACT will be meaningful for all levels of design, and specific

Many of today's high technology products require low-cost implementation information concerning standard cell design is in­
and short development times. Designers are faced with the dilemma of
tended to show specific points.
cranking out designs quickly that are inexpensive and work the first time.
Careful economic trade-offs will have to be made between the level of inte­ A word or two of definition is in order. The word
gration, choice of technology, packaging or lack thereof (i.e., surface gate array is used in the industry to reconfigure a
mount), and the ability to meet a market window. preprocessed wafer using only a few mask levels.
The standard cell approach to VLSI design fits into the overall custom The word standard cell is used to imply the inter­
VLSI family as a cheaper/timely alternative to gate arrays and fully custom
connection of predefined and pre-laid out function
approaches. Although it had its origins in the trouble-free design of medium-
speed digital circuitry, advances in routing techniques have made this tech­ blocks using a routing program. The fully custom ap­
nology easily extendable to the analog realm, making it relatively painless proach involves the interconnection of devices at the
to implement the analog and digital VLSI circuitry of the present. In addi­ transistor level in a random manner to achieve maxi­
tion, the use of standard cells provide an easy method of utilizing earlier mum packing density. Both standard cells and fully
wisdom and avoids reinventing the "wheel." The slight penalty in area
custom approaches involve the prove-in of an entirely
suffered compared to fully custom approaches is increasingly diminishing
with finer line-width technologies and smarter routing programs. As com­ new set of masks at fabrication time.
pared with a full custom implementation, standard cells offer shorter sched­ This tutorial should also serve as a road map for
ules and usually work on the first turnaround. The authors believe that in VLSI design aid developers. Many excellent design
the very near future, design costs will force most IC designs to go this route aids do exist at the present time, but there are gaps in
with the exception of a few high volume runners. This tutorial will cover
the design aspects and methodology from concept to manufacture of stan­
the process and always a need for new tools to assist
dard cell VLSI circuits. It will attempt to provide a broad brush treatment designers. Hopefully, this tutorial will show exactly
of the subject and show what design aids are available to help designers get what is required in the standard cell VLSI design pro­
their jobs done efficiently and reliably. This tutorial will intentionally not cess and spark some ideas in design aid developers to
be overly technical and will instead be directed toward the new VLSI de­
produce tools for this specific job.
signer and hopefully be a starting base of knowledge to be expanded with
experience.
An attempt will be made to present a unified meth­
odology that is applicable for analog and digital cir­
Introduction cuitry. However, distinctly different methodologies
One excellent solution to today's low-cost, tightly are in current practice for digital and analog cells,
scheduled, proprietary product-design scenario is a particularly in the area of simulation and testing. Un­
VLSI circuit implementation. The advantages to this less otherwise mentioned, the main flow of this paper
solution are many, including lower parts count, will be for digital circuitry. Where applicable, men­
smaller boards, nonreverse engineerable designs, and tion will be made of the extension of these time-
lower power. The disadvantages, however, include a proven techniques to the analog realm.
certain amount of design inflexibility and an ever-
reducing excess area penalty. Requirements
This tutorial will attempt to highlight to the practic­ The first major step in the design of a VLSI device is
ing engineer the methodology and constraints to be to decide that you need one. All factors should be
learned for VLSI design. It will also attempt to stamp weighed including speed requirements, parts cost,
out the myth that VLSI design is difficult and only development cost, cost to use, pin count, packaging
attemptable by those few and mightly VLSI design cost, schedule, and board space. For example, de­
gurus. This tutorial will take the engineer through the signer zeal for reduction of external components very
entire design process and show what the steps are, often convert a simple design task into multisilicon
what pitfalls might be encountered at each step, and iterations with poor manufacturing yields. Higher
what is required for smooth transition between steps. levels of integration do not always produce the most
In addition, a discussion is included of what design cost-effective systems; higher functionality IC's very
aids are available to assist the designer along the way. often imply higher pin count (part of which may re­
VLSI design is obviously not a paper and pencil pro­ sult from testability), and the packaging costs could
cess, and many powerful computer aids are available. be prohibitive.
If the correct ones are chosen, it will shorten design Surface mount alternatives, that in the long term
times and help prove-in the correctness of the final may be cost-effective, could involve significant capital
design before large-volume manufacture. investment and inflexible automation in the factory.
The particular level of VLSI design to be focused on Designer enthusiasm may again involve using finer
is standard cell design. This level represents a grow­ line-width technologies inappropriately for the de­
ing trend in the industry of custom VLSI parts and sign under consideration, causing considerable de­
falls in between gate array implementation and full lays in producing a manufacturable part. The tech­
custom designs. Much of the methodology discussed nology and implementation chosen also depend on

JANUARY 1985 8755-3996/85/0100-0017$!.00 © 1985 IEEE 17

these factors. The CMOS technology seems to be odology could be as much as 70 percent of the total
taking a stronghold in the industry because of its development cost.
strengths in power consumption and speed. Other
Internal Requirements
technologies such as NMOS and bipolar are good al­
Now that the system designers have stated what
ternatives depending on the application and should
they need, the VLSI designer must churn out what
not be discarded without careful thought.
will be inside the device. The system designer and the
System Requirements VLSI designer are not necessarily different people,
The system that the device will ultimately reside in but throughout the text of this paper, a differentiation
will usually dictate the requirements. It is important is made to highlight today's problems. A good under­
that a complete understanding of what is needed be standing of the internal requirements can make the
reached between the VLSI designer and the system subsequent design process much easier. All functions
people early in the game to avoid later disaster. The should be specified and blocked out. All timing con­
system requirements should spell out the pin level siderations and critical sections should be stated. A
interactions, the functionality needed from the de­ back and forth communication, at this point, is vital
vice, and some idea of speed of operation. Other fac­ for a successful outcome. Very often, what the system
tors such as pull-ups on inputs and specific signals on designer wants is not what was written down. Alter­
a selected pin should also be stated. nately, improper understanding could result in costly
In the case of analog circuitry, EMI (electro mag­ overdesigns and nonfunctional circuitry.
netic interference) performance, power supply rejec­ Partitioning: The functionality of the device should
tion (PSRR), noise levels, reliability, predefined fail­ be partitioned into subfunctions and those subfunc-
ure modes, etc., are hard to design for, and a clearer tions into sub- subfunctions until the designer is sat­
understanding of their importance in the perfor­ isfied that the design can be reasonably handled. This
mance of the system could go a long way in produc­ partitioning into functions with predefined interac­
ing useful circuits. tions between them will simplify the design. It also
Another important consideration is an overall test­ allows the design process to be split up over a few
ing strategy. If the board is to be tested with an in- designers. Each of the functions and subfunctions
circuit testing machine, certain precautions, such as can be designed and proven-in separately, giving the
tristating all outputs, will be required. If some sort of designer small design jobs before the entire design is
scan chain testing is to be used in the system, this put together. Testing a single counter by itself is much
needs to be stated. If functional trimming is required easier than debugging that same counter when it re­
on the chip, either at the wafer or at the package level sides in a complex function that does not seem to
in some high-precision applications, appropriate trim­ work. Similarly, testing a biquad is a lot easier than
ming procedures should be thought of well ahead of testing a complex filter.
time.
Hierarchical design: The direct fallout of a good par­
Testing should not be considered as an after­ titioning job is that the design can be implemented
thought. Auxiliary test points at the internal nodes of hierarchically. This means certain functions used
a chip, particularly, in the analog sections, with their
over and over can be designed once and used as often
associated openings in the passivation layer, could
as needed. As we will see in a later section, the design
ease the prove-in of a prototype and would help avoid
can be captured into a data base in a hierarchical man­
considerable pain in solving yield problems that may
ner, so a good partitioning up front is important.
later arise in manufacturing. Care should be exer­
Cascaded filter design has a lot going for it in terms
cised that the provision of these test points do not
of this methodology and has over the years proven its
degrade performance noticeably, do not increase lay­
ability to produce parts that work the first time.
out time significantly, and does not cause reliability
problems. A careful and well-thought-out standard Standard Cells
cell design strategy will automatically incorporate A standard cell is nothing more than a digital logic
these test points as part of the cells and will not need element—or an analog block such as an opamp, com­
manual "meddling" or extraordinary design atten­ parator, etc.—performing a specified function and
tion at a later time. In fact, if your design incorporated laid out in a predefined area with power and I/O sig­
unproven circuit ideas and unproven cells, it is a nals set up at regular pitches. Figure 1 shows the dif­
worthwhile practice to incorporate them as a few test ferent aspects of a sample cell. The designer specifies
sites on the silicon wafer, thus helping in the evalua­ the circuit in terms of these standard cells. The de­
tion of their performance in an unencumbered man­ signer states what cells are needed and what signals
ner. It can not be stressed enough that testing plans are to be connected to implement the design func­
be thought out from the start, giving the designer tionally. After the design is simulated and proven to
ample time to make the device testable both at manu­ function correctly, other design aids, such as auto­
facture and on board. It should be noted that the costs matic layout and routing generation software, is run
associated with developing an adequate test meth­ on the circuit to generate masks for fabrication. The
18 IEEE CIRCUITS A N D DEVICES MAGAZINE
 What are Standard Cells
CIRCUIT SCHEMATIC
VDD

CELL LAYOUT
A1 A2 B2 B1 C1

LOGIC SYMBOL

A1 A2 B2 B1 C1 C2

Types
NAND NOR AND-OR-INVERT
OR-AND-INVERT FULL ADDER
INVERT XOR XNOR
STATIC AND DYNAMIC FLIP-FLOP
TRANSMISSION GATE I/O PADS

Figure 1

designer may at his discretion place a high penalty Analog Cells:

on the length, resistance, or capacitance of certain Opamps
interconnects. Comparators
AGCs
A/D and D/A
Types of Cells Available Biquads
The different types of standard cells that are PLL
prevalent today include: Voltage References
Bias Circuitry
Random Logic Cells:
Some aggressive cell blocks implemented today and
Inverters and buffers
to be seen in the near future include:
2, 3, and 4 input NAND, NOR, AND, OR
XOR and XNOR 4-bit counter slices
OR-AND-INVERT and AND-OR-INVERT in 1-bit ALU slices
many combinations of inputs PLAs multiplexors
data selectors
Storage Cells: registers
Static and Dynamic types shift registers
Master-Slave types multipliers
D flip-flops CODECS
J-K flip-flops Echo Cancellers
R-S latches Tone Generators
clocked R-S latches Prior Analog LSI
Sample and Hold latches
Standard Cells vs. Gate Arrays and Full Custom
I/O Pads: The main advantage of using standard cells versus
tri-state output pads gate arrays is the savings in area. A standard cell de­
Input pads with internal pull-up resistor sign does not have predefined sites for the cells as
Schmit Trigger input do gate arrays, and the layout and routing can be op­
TTL input and output timized for the given design. The penalty is the turn-

JANUARY 1985 19
 BLOCK DIAGRAM

Schematic Capture Κ Functional

Connectivity Vectors Vectors
File Stimulus
Vectors
Logic and Fault
- a
Simulation Digital
Tester
True Values

Virtual Vector Display True Values

4 Place and Route

XY

Cap (pf) Cap Extraction

Figure 2

around time from design to samples. A gate array design rules that are applied to this specific type of
manufacturer has gate array wafers premade and need circuit implementation. This is especially important
only add a few mask levels to implement the circuit. for designers coming from the discrete and TTL world
A standard cell requires a complete set of new masks of design. The rules are by no means difficult to adhere
and fabrication from scratch. However, the trend has to but must be kept in mind from the word go for the
been for shorter and shorter turnaround schedules design to work the first time and be manufacturable.
for standard cells designs.
Synchronous Design
The area to route signals in a standard cell design
The most important rule in standard cell design
is usually 50-80 percent of the chip size. One way to
and probably in all levels of VLSI implementation is
determine the size of the chip before layout is done is
that the design be synchronous. This means that all
to take the combined area of the standard cells and
storage devices (i.e., flip-flops) have the same clock.
multiply by 3-5. This routing penalty is the main dis­
In silicon, there is no guarantee of how long signals
advantage over a full custom implementation of the
will take to propagate through gates and down paths.
circuit. However, by using automated layout and rout­
Design tricks that are used in TTL designs, such as
ing tools, the confidence level that the circuit will work
clocking off of glitches and adding extra stages of in­
the first time is much higher. A full custom imple­
verters to slow down a signal, just don't work in VLSI
mentation is crucial for a microprocessor or memory
design and should be avoided.
that is a very cost conscious effort. Other designs that
A synchronous design will clock all data at the same
are in the 1000-6000 gate range are better candidates
time on the same edge of the clock. This allows all
for standard cell design because the cost penalty will
signals to propagate from the output of one flip-flop
not be that great, yet the turnaround will be shorter,
to the input of the next (through whatever random
and the likelihood that the first samples of the circuit
logic is in between them) have the signal settle down
work will be high. On the other hand, a 100-parts-a-
to its correct value, and be latched up. This design
year application involving a 1000 gate circuitry may be
method is robust, as the system clock can be set to
an ideal candidate for a gate array.
work over a wide range of processing, operating con­
ditions, and skew and can have the circuit work
Design Rules correctly.
Before embarking on a VLSI design project, it is Another design constraint is for all clears on flip-
important that the designer understand a few basic flops to be synchronous as well (i.e., have the clear
20 IEEE CIRCUITS AND DEVICES MAGAZINE
 Graphical Schematic Capture

NOR1

DN Di D D D D
SP SP I SP

MCK
MCKN
SCK SCK SCK
SCKN SCKN SCKN

N0R6

Figure 3

signal be presented to the D input of the flip-flop). between flip-flops. This is an important design con­
The asynchronous PRESET and CLEAR leads on flip- sideration but not insurmountable as extra flip-flops
flop standard cells should be saved for a master clear can be added to break up propagations with large
or power on clear when timing is not critical at all. gate counts. As an example, imagine a device with an
The clock inputs to all flip-flop standard cells should input clock of 8 Mhz. Accounting for some clock skew,
come from the same clock signal that is as close to a this gives a maximum time between stages of about
circuit input as possible. It is possible to boost this 110 ns. Also assuming a maximum gate delay of 7 ns
signal with buffers or have a count-down circuit on and a worst-case routing delay of 3 ns, this allows for
the input clock, but care should be taken when laying about 11 gate delays between the output of one flip-
out these functions. The clock input to the standard flop to the input of the next.
cell should never be gated with some other signal, as Analog Worries
this may cause strange clock skews that could cause Good analog design practice is something that is
the circuit to malfunction. achieved over a period of years. The novice designer
Limited I/O would go a long way by understanding the critical
Another design rule that should be noted when the parameters of his functional blocks carefully and the
circuit is partitioned: VLSI circuits are normally pin interactions with their neighbors. If your design in­
limited. That is, if you have 40 pins, someone will volves crucial matching, isothermal design or ultra­
come up with an implementation that requires 41. high performance, an hour or two spent with an expe­
Both inputs and outputs to the device may be multi­ rienced designer is worth its weight in gold. Analog
plexed, but this may cause the system implementa­ circuitry tend to be more sensitive to parsitic coupling
tion to be complex. Pins are considered a valuable and hostile digital transitions from other circuitry on
resource and should be assigned and used wisely. the same chip. Sampled data systems that have other
It is advised that the pin assignments be formulated on-chip asynchronous clocks should be avoided as
early in the design process with little chance of chang­ much as possible in noninsulator based bulk-CMOS
ing. In the event of extra pins being available, use them technologies.
to enhance the testability of the circuit. Overall Methodology
Finite Gate Delays Figure 2 gives an overall idea of what the standard
If the clock input to the VLSI device is fixed, it is cell VLSI design process is. The different steps in the
important to know how many levels of gates can exist methodology include:

JANUARY 1985 21
 • Schematic Capture of Design Intent blocks exists freeing the designer from this level of
• Functional Vector Generation design.
• Logic Simulation For each of the blocks, there can be an internal and
• Viewing and Interpreting Simulation Results an external view of the function. The design can be
• Model Generation and Functional Testing of the entered from the top down, the bottom up, or, more
Model practically, from the middle sideways! To enter a cir­
• Manufacturing Test Generation cuit from the top down, the designer may use the fol­
• Place and Route Activities lowing methodology:
Once these designer-intensive steps are complete, • Enter an external view of the chip, basically a box
the design is ready for completing the mask genera­ with all the I/O pins labeled and numbered.
tion, fabrication, and device testing steps. • Enter an internal view of the next level of hierar­
chy, for example, four blocks connected together
Schematic Capture of Design Intent as well as the external I/O pins connected to the
Once the internal requirements and the pin outs of blocks. This also requires entering the external
the circuit are decided upon, and the correct design views of the four functional blocks.
rules are understood, it is time to specify the actual • Repeat the above steps for each of the functional
design itself. This requires getting the design into a blocks, replacing the connection of the external
machine-readable data base so that CAD tools can op­ I/O pins with the input and output nodes of the
erate on the design for simulation, layout, etc. In the function block. The steps are repeated until the
past, this meant producing hand-drawn schematics design is down to the lowest level specifiable, i.e.,
and entering a file (or even a card deck) that describes the standard cells or predesigned subnetworks
the design into a computer system. This was a cum­ such as counters, shift registers, biquads, etc.
bersome and error-prone job. Functional Design of Elements in Hierarchy
Today a designer can sit down at a graphics termi­ The subnetworks mentioned above allow a de­
nal or a CAE workstation and use a graphical sche­ signer to operate at a somewhat higher level than
matic capture program that allows one to enter the standard cells. Much design time is wasted on re­
design electronically and automatically produce the designing a 4-bit synchronous counter with low clear
necessary files used by later programs. In standard and load. If one does not exist in a library of subnet­
cell design, the designer calls to the screen the cells to works, the designer must come up with one. Pro­
be used and connects them together with "wires/' grams are available to do functional design of
Figure 3 shows an example of a graphically entered counters, shift registers, adders, and random logic.
schematic. The designer is prompted for the necessary param­
The advantages to this approach are as follows: eters of the subnetwork, and the function is designed
• The design is stored in a data base, and changes from the library of standard cells. These programs
are very easy to implement. can also be interfaced to the schematic capture tools,
• The graphic capture programs are usually human creating both the internal and external views of the
engineered and quite easy to use. functionally designed elements for the designers use.
• Design partitioning between designers can be im­ In our opinion, the complexity of today's IC's can no
plemented because each designer can enter their longer support the luxury of doing it "my way be­
own section of the circuit and combine designs cause it is the right way" type of attitude.
later in the process.
• The fact that the design is in a graphical data base Creation of Functional Vectors for
can be utilized by sophisticated design aids to Design Prove-In
perform advanced functions. At this point of the design process, it is assumed
• Very often, since circuit extraction for simulation that a connectivity file exists describing the connec­
is derived from such schematic capture tools, it is tion of the standard cells comprising the circuit or sub­
difficult to change the circuit description without network. This is required input to a logic simulator.
changing the schematic appropriately. The other entity needed by the logic simulator is a set
of input stimulus called vectors to exercise the circuit.
More Thoughts on Hierarchical Design For each of the inputs to the circuit, a logic state needs
Most schematic capture tools enable a user to enter to be specified for each time step. The simulator takes
designs hierarchically. This allows for designs to be this information and returns the state of internal
entered as connected functions, such as counters, ad­ nodes and circuit outputs.
ders, biquads, references, memory, and even micro­ Manual Input
processor blocks. The user enters these blocks once The simplest method of entering vectors is to man­
and can add them to different sections of the design. ually create a file containing logic states that get
On many systems, not only library of standard cells mapped to the input pins. A vector is a line of logic
exists, but a rather extensive collection of functional values, and each pin would have its state specified in
22 IEEE CIRCUITS A N D DEVICES MAGAZINE
a column of Ts and 0's. The vectors do not have a unit form various degrees of simulation at different levels,
of time but are applied to the input pins by the but the designers needn't concern themselves with
simulator at some given vector period, for example, the details of logic simulators. The designer's concern
every 50 ns. The following is an example of a vector is with feeding in the correct information and inter­
file: preting the results. The rest of this section will be a
brief description of the kinds of logic simulators that
Column 1: CLOCK
are important to standard cell-logic designers. More
Column 2: CLEAR
feature-rich simulators are not as important at this
Column 3: START
stage of the game, as they are more meaningful for
Column 4: MODE
post layout simulation.
Column 5: TEST
1—00110 Simulation Level
2—10110 There are three basic levels of logic simulation:
3—01010 functional, gates, and transistor level. Each level is a
4—11010 finer detail of simulation, requiring more information
from the user and more computer time. The user can
Another method of specifying vectors is with clock
start at the highest level and run finer and finer sim­
formats. Each input is specified in terms of state tran­
ulations as needed to prove the functionality and
sitions and when they occur. Fancier clock specifica­
later some worst-case simulations of the design.
tion formats allow for repeating patterns and repeat­
ing clock definitions. The following is an example: Functional level: Circuits simulated at the functional
level return logic values at the inputs and outputs of
CLOCK: I L 1H Repeat
the function blocks. What is required is library of
CLEAR: 2L 1H
function block models usually written in a higher
START: 2H 100L 25H 15L
level language. The logic simulator supplies the in­
MODE: 10 (10H 5L) 35H
puts to the block, and the model supplies the out­
TEST: 50L 65H
puts. The user can not look inside at the internal
Higher Level Vector Compilers nodes of the function block because they do not exist.
Compilers exist that allow a user to specify vec­ Functional simulations are usually very fast, as the
tors in a higher level language instead of Ts and 0's simulator does not have to keep track of much infor­
and clock definitions. Functions for count up, count mation.
down, pattern generation, walking l's and 0's, etc., are Gate level: At the gate level, a circuit is described as a
available. Bus definitions allow signals to be grouped collection of NAND, NOR, AND, OR, INVERTER,
together, and programming constructs such as loops and other simple logic gate functions. The standard
and subroutines may be added to allow for some com­ cells are comprised of these gates, so gate-level simula­
plex vectors to be written with ease. An example: tion is a reasonable choice for simulating standard cell
Bus (ABUS, [A0:A7]); designs. A library must exist describing the standard
Clock_Def (CLOCK, start_time=0, period=50, cells in terms of these gates, and, usually, other infor­
duty_cycle=40% ); mation is given in these libraries such as input capaci­
Count (ABUS, direction=UP, start_value=lF, tances and other parameters useful for multiple delay
count_period=100); and timing simulation (see the next section). Gate-
Walk (ABUS, f u n c = l THRU0, start_value=00, level simultion returns logic values for internal nodes
of the circuit including some nodes internal to the
walk_period=200);
standard cells, obviously only down to the gate level.
Analog Stimuli This should give the designer plenty of information
Analog circuits usually have stimuli that are repre­ as to the functionality of the circuit.
sented either by a frequency-domain response, as is
Transistor level: When detailed simulations are re­
the case with filters, or by a time-domain require­
quired of critical paths in the circuit, as well as sim­
ment, as is the case with the acquisition time of a
ulation of special cells, a transistor-level simulation is
PLL. Some criteria like PSRR and noise are simulated
required. This type of simulation takes as input the
and then analyzed to find out whether they are within
connection of the circuit at the device level, tran­
design margins.
sistors, metal paths, poly paths, etc., and constructs a
Logic Simulation model of the circuit in terms of resistance and capaci­
With a connectivity file describing the circuit and a tance. The simulator returns timing waveforms de­
set of functional vectors to exercise the circuit de­ scribing the characteristics of the circuit. For large
scription, the next step is to feed this information into collections of standard cells, this level of simulation is
a black box called a logic simulator. The logic simulator impractical, as the designer should not care about the
simulates the logic states of all the nodes of the cir­ characteristics of every node, only those that are
cuit. Many varieties of logic simulators exist that per- deemed critical. Transistor-level simulations usually

JANUARY 1985 23
 Logic Simulation Viewing of Simulation Results

• Unit Delay • Transistor Level •Display Modes

Each gate has set Logic Values on CRT Screen
delay of one unit j. 0,1, and 3's under node name
Color Waveforms on Graphics Terminals
Scope-like output
Schematic Interaction
> Multiple Delay
Logic values on node in schematic
Each gate has finite
rise and fall time

»Logic Analysis Features

> Timing
Search for changes
t2
Pattern Search
V = 1/C Jl dt Triggers
t2

• Functional Level
» Gate Level

Π Ι I 1 11
Figure 4 Figure 5

Simulation Output
fl s s s s s s s s s s s s s s s s s s s s s s s s s s s s s s
Ε H H H H H M M H H H H H H H Η Η Η Η Η H H H H H H H H H H H
F 5 2 2 T B Β R C A A F F F F F F F F F F F F F F S F F F F F S F F F F F S F F F F F F F F F F F
R β 5 S T G A C S T 0 0 1 1 1 1 1 1 1 I 1 1 I I 1 1 H 1 1 1 1 1 H l 1 » 2 2 2 2 2 2 2 2
F M S S K Ï e T T M C C CCCLTCCI I
R t P P M 2 K A L G L L 2 A A A A F AF F F F F F F F I F F F F F F F F F F
D P D D O G M B D L K K F F F F F
0 0 0 0 0 F F F F F F F F F F F F F F
C 2 0 1 2 0 2 3 4 C C C K C Z Z 1 2 2 2 2 B 2 3 3 3 3 C 3 4 4 4 4 0 4 V '

I-1 0 t t 1 1 1 1 1 0 0 0 3 3 1 3 3 3 3 3
2-1 0 1 1 13 3 3 1 0 0 1 1 3 3 3 3 3 1 3 3 3 3 3 1 3 3 3 3 1 0 3 3 3 3 0 3 1 3 -
3-0 0 1 1 0 0 1 1 1 0 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 1 0 3 3 3 3 1 3 3 3 -
4-0 0 1 1 ο ι 1 0 1
ί σ ο ι
0 1 1 0 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 1 0 3 3 3 3 1 3 3 3 -
10 0 1
5-0 0 1 1 0 1 10 0 1 1 0 3 3 1 10 1 0 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 1 0 3 3 3 3 1 3 3 3 -
10 0 1
6-0 0 1 1 0 1 0 1 1 0 0 0 1 0 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 0 3 3 3 3 1 3 3 3
10 0 1
7-0 0 1 0 0 0 0 0 10 0 10 0 1 0 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 0 3 3 3 3 1 3 3 3
0 0 0 1
8-0 0 1 0 0 0 0 0 0 1 1 0 0 0 3 3 0 1 0 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 1 0 3 3 3 3 1 3 3 3
0 0 0 1
9-0 0 1 0 0 0 0 0 10 0 1 0 0 3 3 1 0 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 1 0 3 3 3 3 1 3 3 3
0 0 0 1
10-0 0 1 0 0 0 0 0 0 1 1 0 0 0 3 3 1 0 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 1 0 3 3 3 3 1 3 3 3
0 0 0 1
11-0 0 » 0 0 0 0 0 î o o i o 0 0 0 1 0 3 3 1 0 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 1 0 3 3 3 3 1 3 3 3
12-0 0 1 0 0 0 0 t 1 0 0 0 3 3 0 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 1 0 3 3 3 3 1 3 3 3
0 0 0 1
13-0 0 1 0 0 0 10 0 1 0 0 3 3 0 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 1 0 3 3 3 3 1 3 3 3
0 0 0 1
14-0 0 1 0 0 0 0 1 1 0 0 0 3 3 1 10 1 0 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 1 0 3 3 3 3 1 3 3 3
0 0 0 1
15-0 0 1 0 0 0 l o o t o 0 0 0 1 1 1 0 3 3 1 1 0 1 0 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 0 3 3 3 3
16-0 0 1 0 0 0 0 1 1 0 0 0 3 3 1 0 1 0 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 0 3 3 3 3 1 3
0 0 0 1
17-0 0 I 0 0 0 1 0 0 I 0 0 1 0 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 1 0 3 3 3 3 1 3 3 3
0 0 0 1
18-0 0 1 0 0 0 0 1 1 0 0 0 0 0 1 1 1 1 0 3 3 1 1 0 0 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 0 3 3 3 3 1 3 3 3
19-0 0 1 0 0 0 10 0 1 0 0 0 0 1 1 1 1 0 3 3 1 1 0 1 0 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 0 3 3 3 3 1 3 3 3
zo-o ο ι 0 0 0 0 1 0 0 0 0 0 1 1 1 1 0 3 3 1 1 0 1 0 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 0 3 3 3 3 1 3 3 3 -
t 0 0 0 0 0 1 0 0 1 1 1 0 3 3 1 1 0 1 0 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 1 0 3 3 3 3 1 3 3 3 -
21-0 0 1 0 0 0 1
1 0 0 10 0 0 0 1 1 0 0 1 » 1 0 3 3 1 10 1 0 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 1 0 3 3 3 3 1 3 3 3
22-0 0 I 0 0 0 1
23-0 0 1 1 0 0 10 0 0 10 0 1 0 1 1 1 0 3 3 1 1 0 1 0 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 1 0 3 3 3 3 1 3 3 3
0 0 0 1
24-0 0 I I 0 0 10 0 0 0 1 1 0 0 1 1 1 0 3 3 1 1 0 1 0 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 1 0 3 3 3 3 1 3 3 3
0 0 0 1
25-0 0 1 1 0 0 10 0 0 10 0 10 0 0 0 1 0 3 3 1 1 0 1 0 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 1 0 3 3 3 3 1 3 3 3
26-0 0 1 1 0 0 10 0 0 0 1 1 0 0 0 0 0 1 1 1 1 0 3 3 1 1 0 1 0 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 1 0 3 3 3 3 1 3
27-0 0 1 1 0 0 10 0 0 1 0 0 I 0 0 0 0 1 1 1 1 0 3 3 1 1 0 1 0 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 1 0 3 3 3 3 3 3
?8-0 0 1 1 0 0 10 0 0 0 1 1 0 0 0 0 0 1 1 1 1 0 3 3 1 1 0 1 0 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 1 0 3 3 3 3 3 3
29-0 0 I t 0 0 10 0 0 10 0 10 0 0 0 1 1 1 1 0 3 3 1 1 0 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 1 0 3 3 3 3 1 3 3 3 -
30-0 0 1 1 0 0 10 0 0 0 1 1 0 0 0 0 0 1 1 1 1 0 3 3 1 1 0 0 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 1 0 3 3 3 3 1 3 3 3 -
31-0 0 I 1 0 0 10 0 0 10 0 10 0 0 0 1 1 1 1 0 3 3 1 1 0 0 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 1 0 3 3 3 3 1 3 3 3 -
32-0 0 1 1 0 0 10 0 0 0 1 1 0 0 0 0 0 1 1 1 1 0 3 3 1 1 0 0 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 1 0 3 3 3 3 1 3 3 3 -
33-0 0 1 1 0 0 10 0 0 10 0 10 0 0 0 1 1 1 1 0 3 3 1 1 0 0 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 1 0 3 3 3 3 1 3 3 3
34-0 0 1 10 0 0 0 1 1 0 0 0 0 0 1 0 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 0 3 3 3 3 1 3 3 3 -
35-0 0 1 10 0 0 10 0 1 0 1 1 1 0 3 3 1 0 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
ό σ ο ι 0 3 3 3 3 1 3 3 3 -
10 0 0 0 1 1 0 0
36-0 0 1 0 0 0 1 1 1 1 0 3 3 1 0 1 0 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 0 3
10 0 0 10 0 1 0
37-0 0 1 0 0 0 1 1 1 1 0 3 3 1 0 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 1 0 3 3 3 3 1 3 3 3
38 0 0 I 10 0 0 0 1 1 0 0 0 3 3 1 1 0 1 0 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 1 0 3 3 3 3 1 3 3 3
0 0 0 1
39-0 0 1 ι 0 0 10 0 0 10 0 10
0 0 0 1 0 3 3 1 1 0 « 0 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 1 0 3 3 3 3 1 3 3 3
40-0 ι 0 0 10 0 0 O 3 3 1 1 0 I 0 O 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 1 O 3 3 3 3 1 3 3 3
1-0 0 10 0 0 0 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 1 0 3 3 3 3 1 3 3 3
0 0 0 1
42-0 0 ι ο ο 10 0 0 10 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 1 0 3 3 3 3 1 3 3 3
43-0 0 0 0 0 1 0 3 3 1 1 0 10 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
I 0 0 1 0 3 3 3 3 1 3 3 3
0 0 0 1
44-0 0 1 0 0 10 0 0
0 0 0 1
0 3 3 1 10 10 0 3 3 3 3 3 3 3 1 3 3 3 3 3 3 3 3 3 3 0 3 3 3 3 1 3 3 3 -
45-0 0 10 0 0 0 3 3 1 1 0 10 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 0 3 3 3 3 1 3 3 3 -
46-0 0 0 0 10 0 0 0 1 0 3 3 1 1 0 10 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
0 0 1 3 3 1 3 3 3 -
47-0 0 0 0 10 0 0
ό σ ο ι 10 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 1 ,
o o o i . . , . _ _
48-0 0 0 0 10 0 0 I I 1 10 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 1 0 3 3 3 3 1 3 3 3
49-0 0 0 0 10 0 0 0 1
0 0 0 3 3 1 1 0 ' 0 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 1 0 3 3 3 3 1 3 3 3
50 0 0 0 0 0 1
10 0 0 1 t 1 1 0 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 1 0 3 3 3 3
0 0 0 1
10 0 0 0 0 0 1
10 0 0
0 0 0 1
Figure 6

24 IEEE CIRCUITS AND DEVICES MAGAZINE

take a very large amount of computer time and are centering on subcircuit blocks over a wide range of
really only needed at the final stages of the design temperature/process limits and the extremes of oper­
process after layout has been performed. ating conditions. Because of the rather extremely de­
tailed nature of these results, these simulators are
Analog simulation: System-level concepts for analog
usually restricted to prove-in functional blocks such
systems are very often verified, using large functional
as opamps, comparators, VCOs, PLLs, etc.
simulators and breadboards. The complexity of ana­
log circuitry can very often be translated into solving Simulation Mode
large-order differential/difference equation systems, In addition to the levels of simulation, there are
which can be nonlinear, time vriant, or cyclically time several modes of simulation depending on how accu­
variant, as is the case with sampled data systems. rate the simulation is to be run in terms of time. Unit
Functional simulation very often allows overall per­ delay, multiple delay, and timing are usually the three
formance evaluations, system verification, and the basic modes of simulation, as stated in Fig. 4.
study of specific impairments.
Unit delay: In unit delay mode, every gate has a set
Network-level simulation is often used in the case
delay of 1 unit; no actual time is associated to gate
of large passive element circuitry, frequency-domain
delays. This is the simplest mode of simulation be­
analysis of complex active RC structures, sampled
cause most'factors such as input capacitance and gate
data networks such as switched-capacitor filters, and
fanout are ignored. The only factor considered is the
for studying distributed parameter effects such as
number of units of delay a signal must propagate
transmission lines. Though limited in their ability to
through.
help in the analysis of practical impairments on cir­
cuit performance, very often these tools form the Multiple delay: In standard cell design, the timing of
backbone of a design synthesis procedure and enable many signals is very important, especially signals
one to build from the wealth of information about that go through many levels of combinational cir­
passive networks in the realization of their active cuitry between latches. In multiple-delay simulation
counterparts. In addition, they play a vital role in the mode, each gate has a finite rise and fall time that is
model building task of the small signal behavior of used to calculate how long it takes for a signal to
many active circuits. propagate through gates. This level of simulation
Circuit-level simulation is very often used to per­ does not add that much overhead with respect to unit
form exhaustive performance analysis and design delay, but gives a fairly accurate timing description of

Graphical Simulation Output

1111 ; 11111111111111111111111111111111111111111111111111111111111111111111111 I Il|11111
START I Π
CLOCK ruTJUiTLnnjuuiJir^^
CLEAR 1 I
QO ι π π π π π π π
Q1 ι π π π π π π η_
Q2 ι π π π π π π η
Q3 I Π Π Π Π TL Π Γ
04 I Π Π Π Π Π Π
05 I Π Π Π Π Π Π

XL I III I IIII I III I I II I II III I I III I I I IIII III I I I III IIIII III I I I I I I I I I I I I I I I I I I I il I I I I
I I I I

10 20 30 40 50 60 70 80

Figure 7

JANUARY 1985 25
the circuit. This mode used in conjunction with a fea­ the most computer intensive because it must break up
ture to list high fanout gates should be adequate for the simulation into very small time steps and do a
standard cell design. See the section on capacitance large number of calculations at each of these steps.
extraction for more discussion on this subject. Mixing simulation modes: A useful feature of a logic
simulator is to allow for use of the various modes for
Timing simulation: The formula for voltage is
different nodes of the circuit. This way, a critical sec­
v = 1/C integral from tl to t2 of i dt tion can be run in full timing simulation and the rest
in multiple delay mode, therefore not slowing down
The amount of current that a MOS can supply is finite,
the execution time of the simulation appreciably. In
so the voltage of nodes is inversely proportional to the
our opinion, this may be the most cost-effective tech­
capacitance. The capcitance of nodes in VLSI devices
nique for verifying large mixed mode analog/digital
is the sum of the input capacitances of all the gates in
circuits.
the fanout list plus the parasitic routing capacitances
for all the routing paths. The libraries from which the Viewing and Interpretation of
simulations are run should list all the input capaci­ Simulation Output
tances of gates. The routing capacitances are not really Once a simulation of the circuit has been run, it is
known until layout time, so prelayout simulations re­ the responsibility of the designer to interpret the re­
quire a guess at the routing capacitance. Once this sults and figure out what it all means. Verification that
information is at hand, the simulator merely applies the circuit is functionally correct is critical. It is im­
the above formula in finite time steps and produces portant that the vectors exercise as much of circuit as
an accurate representation of the node voltages for possible. Alternately, all performance aspects that are
the circuit. For example, the simulator can spit out directly and indirectly specified should be verified.
voltages between zero and five volts in a tenth of volt The simulator will spit out the states of the circuit out­
increments and construct a waveform from these puts and internal nodes for each time step. A me­
numbers. dium size circuit could have a few thousand internal
Timing simulation is very important for critical path nodes and be simulated for tens of thousands of vec­
analysis. A signal may not have enough time to reach tors. This is a lot of information and can be very baf­
logic level before a latching clock comes along. The fling when trying to figure out what the circuit is
designer can easily determine this by looking at full really doing. Figure 5 covers some of today's modes of
timing waveforms for the node. Timing simulation is viewing simulation results.

Schematic Simulation Output

0 Output

START I—t>CK Q N f - r - p c K QN f—f>CK QNf— |—PCK QNf— H>CK Q N f -

CD CD CD CD CD
CD
FD153D FD153D FD153D

•CLOCK 1
CLEAR 1 χ. inv2
φ a)>0-
^ IMDD

Figure 8

26 IEEE CIRCUITS AND DEVICES MAGAZINE

 TTL Model Verification

Connectivity
File

MOS Expected
Simulation Outputs

Functional
Vectors
*
Compare
TN—
Digital Actual
Test Outputs

TTL Model
of Device

Figure 9

Vs and 0's signer entered the design graphically is useful, and a

Logic simulators will save results in logic states: value added function can be added easily to the design
logic 1, logic 0, unknown, and high impedance. More aids. By accessing both the schematic and simulation-
sophisticated simulators save more states, but these results data base, the logic values may be displayed on
are the basics. In the past, when simulations were run the actual node in the schematic. Figure 8 is a simple
on large mainframes in batch, a designer would have example of a shift register with the simulated values
the laborious job of picking up a listing (usually sev­ displayed on the schematic. This removes a level of
eral pounds) and drooling through pages and pages mapping from the designer and allows for detailed
of Ys and 0's and 3's trying to determine if the design probing into the circuit. A large collection of gates can
worked. Today, with interactive and workstation sim­ be displayed simultaneously, and the designer can see
ulation, all the results are saved in a data base, and immediately how they interact and determine why
post simulation tools are available that allow virtual the circuit works/doesn't work. The schematic interac­
access to the simulation results. Logic analysis fea­ tion can be applied to any level of the hierarchy, and
tures are sometimes available to assist the designer in the designer can note how data moves between the
functional verification. An interactive CRT can be larger functional blocks or go inside these blocks and
used to display node names and values, and the user probe deeper. In other words, one can do almost
can peruse the results at will, see Fig. 6. everything that can be done with the final parts with­
out ever having made it!
Waveforms
With the use of a graphics terminals, the output Model Generation and Testing
values can be displayed as waveforms on the screens At this point in the design process, it is assumed
as in Fig. 7. This allows a VLSI designer to "probe" that the designer has a complete MOS design that has
the circuit just as a TTL designer would probe a board been simulated and proven to some reasonable level
of parts. The oscilliscope-like waveforms can be dis­ of confidence to be functionally correct. The next im­
played with various time bases, and triggers can be portant step is to construct a TTL or discrete compo­
used to start the display when a node reaches a given nent model of the VLSI circuit. There are many rea­
value or a given slope. sons for this. The most important reason is to plug in
Schematic Interaction a model of the circuit into the actual board/system;
An additional mode of displaying simulation results the chip will be functioning in to prove-in the design.
is to interact with the schematic. The fact that the de- Because actual chips could be months away, the peo-

JANUARY 1985 27
pie in the system area will be very appreciative to get amount of time to the design cycle, which should, of
a model or models of the device to prove-in some of course, be avoided.
their own designs as well. Another important reason Because standard cells are being used, and a data
to generate a model of the circuit is for testing pur­ base exists describing what cells have been used and
poses. The model can be tested with the same vectors how they are connected, it should not be too much
that simulated the MOS standard cell circuit and dif­ trouble to access this data base and do a conversion of
ferences noted. In addition, when the production test the design from MOS to TTL. Each standard cell
of the device is being generated on the big-chip test­ should have a fairly straightforward functional sub­
ers off the fab line, having a model of the circuit will stitution in a TTL part. More complex cells may re­
save many hours of test prove-in time. quire more than one TTL dip. The conversion process
Analog circuitry is very rarely breadboarded, ex­ can be semiautomatic in that the user may have a sub­
cept for functional verification, because of the in­ network that is functionally equivalent to a TTL part.
ability to accurately emulate their hostile integrated For example, the designer has a counter subnetwork
environment. Predefined integrated blocks are very that is a 74xx; the program doing the conversion is
rarely used for this purpose, since they usually lack seeded with this information, and that subnetwork is
the capability to drive the parasitic loading resulting always replaced with that one dip. This method of
from a breadboard implementation. conversion almost guarantees an exact functional
mapping between M O S and TTL. A perfect conver­
sion may not be possible, depending on the design,
Methods of Model Generation
and the user may have to cheat the conversion pro­
There are many ways to generate a model of a VLSI
gram to get the TTL model to functionally match.
device. Someone can take the schematics of the stan­
This is better in the long run than doing the whole
dard cell design and convert them on paper to a TTL
conversion by hand.
design. The designer can re-enter the design with a
schematic capture program, generate a connectivity
Functional Testing
list, and filter this list to generate a wire wrap or a
printed circuit board. This method is very tedious, Pass/fail of model: Once the model is constructed
especially for larger designs, and is also very error and stuffed with parts, it must be tested. If a digital
prone as there is no guarantee that the TTL design tester is available, the same vectors used to simulate
will match the MOS design. This could add a large the M O S circuit can be used. Comparisons can be

Model Generation and Testing

Conversion of Design
from Standard Cells
to TTL

Digital Functional
Tester Vectors
Wire Wrap Machine

1 PASS/FAIL

I wmrn ι
Ί . O D j

Figure 10

2 8 IEEE CIRCUITS A N D DEVICES MAGAZINE

made at the circuit outputs and at selected internal the model can work in real time, plugged into the sys­
nodes to determine if the model passes or fails the tem and taken through the extreme boundary condi­
test. On failure, the tester will usually note the failing tions of use that the digital test could not begin to
node or nodes and the vector where the test fails. muster, then the designer can be more assured the
This may or may not be enough information to help design is correct.
debug the model. Figure 9 shows the methodology of
generating a model and running a pass/fail test.
Test Generation
Signal comparison—actual vs. simulation: Another Now that the design has been proven functionally
mode of testing is to run all the vectors run on the correct through simulation and TTL model testing,
model and have the tester "capture" the values of the the last step before layout is to generate a chip test.
outputs and internal nodes for each of these vectors. Without going into too much detail, the wafers that
A one-to-one signal comparison can be performed be­ come off a fabrication line have a set number of chip
tween the MOS simulation and the actual run on the sites on them. The yield of silicon facilities varies any­
TTL model. Any discrepancies can be noted imme­ where from 20-90 percent. This means, on a wafer of
diately, and the designer has a much better head start 40 chip sites, only between 8 and 36 of these chips
in debugging the model than with simply a pass/fail will work. A test must be developed to find these
indication. Figure 10 is an example of an actual signal number of working parts and, more importantly, to
comparison, and Fig. 11 shows the methodology to identify, with high confidence, the parts that don't
produce such a display. function correctly.
It has been found that this method of comparing
Manual Methods
the MOS simulations and the TTL implementations
The quickest way to generate a test is to generate Ts
has uncovered unexpected bugs in the MOS circuit,
and 0's by hand as with the functional vectors. Unfor­
the TTL model, and, sometimes, in the functional
tunately, this method does not produce the best test
test. This type of testing raises the level of confidence
possible. A quick discussion is needed on fault grad­
that the design implementation in silicon will work
ing to understand what a good test is and may shed
the first time.
some light on how to generate a good test.
Test of Model in System Fault simulation: Classical fault theory for VLSI de­
The last use of the model is for system testing. If vices says that each node has two faults: the node

Graphical Signal Comparison

RDEC.PXMON ι Ui Ο L
RDEC.RXM1N ι u-i «-j uJ"
RDEC.PXM2N ι ι_ι i~j t-J—
RDEC.PXM3 I Π , Π
RDEC.PXMO I η , η
RDEC.PXM2 I Π ΓΧ
NOS ι
CMIN »
BSDO t — ,· ι r
RDI ι
RDN ι
RD I
LL2 i i —

RTI re j L—
RTIN lJt ι »
NDB I
PDB Π
LU I

Figure 11

JANUARY 1985 29
 PLACE and ROUTE Activities

Place and Route Save Optimized Variables

Correct by Construction

Capacitance
Extraction
I
Simulation
(Timing) Functional Vectors

Compare Pre and Post -1 PASS Go to Mask 1

Layout Simulation

FAIL—Buffer up Critical Paths

Redo Place and Route

Figure 12

PLACE and ROUTE Example

Figure 13

30 IEEE CIRCUITS AND DEVICES MAGAZINE

stuck at a logic 0 and the node stuck at a logic 1. These the circuit will be very high. The advantages to this
are called stuck-at faults. The theory goes on to say method is that the tests can be generated automat­
that if you can detect a high percentage of these ically, yielding tests in the 90-95 percent fault coverage
stuck-at faults (greater than 90 percent, for example), range. The disadvantges are that an I/O pin is taken
then you will detect a very high percentage of all the for the test mode selection, and there is an area pen­
real faults, such as opens, shorts, etc. alty for multiplexing the flip-flops and routing the
A fault simulator is a design aid that will tell you scan chain. The area penalty is from 10-25 percent, de­
how many faults a given set of vectors may detect. pending on implementation, and this amounts to real
The fault simulator first determines how many pos­ cost penalties because area is "money."
sible stuck-at faults exist within the circuit. A fault col­
Self-test: Certain regular circuits may be tested with
lapse is then performed. This is nothing more than
built-in self-test circuitry. This requires some extra
removing faults that are identical. Nodes that are tied
hardware on the chip. Self-test circuits are usually re­
together only represent one fault. A NAND gate with
served for full custom implementations that contain a
the input stuck at a 0 is the same fault as the output
microprogrammed processor. Part of the ROM code is
stuck at a 1.
used to test the circuit and returns a pass/fail indica­
Now the simulation is run, and at the end of each tion on the internal circuitry.
time step, it is determined how many of the faults can
be detected at the outputs of the circuit. These are Layout and Mask Generation
then considered caught faults, dropped from the fault Once the designer has the circuit verified, that is,
list, and the simulation continues. What the designer enough simulations have been run to satisfy the de­
gets from all this intensive computational activity is a signer that the circuit as designed will operate cor­
fault grading. The simulator will say that for the vec­ rectly, and the model of the circuit works in the sys­
tors just simulated, 81.4 percent of the faults can be tem, and a set of test vectors have been developed to
detected, and will give a list of those still to be de­ catch a good percentage ( > 7 0 percent) of the stuck-at
tected. It is up to the designer to determine if this is a faults, then it is probably a good time to lay out the
high enough level öf confidence for the test to find circuit and get the fabrication process rolling. The ma­
faulty chips. A number in the 90-95 percent range is jor design aids used in this step of the design process
usually sufficient. are place and route tools. Figure 12 summarizes the
Automatic Methods methodology of the place and route activities.
Designers could possibly slave for many weeks and Cell Placement
months developing a test that covers 90-95 percent of A placement program is run to divide up the stan­
the stuck-at faults. Using a fault simulator, designers dard cells into rows and place the cells in the proper
learn that the first several hundred vectors find 80 rows such that the interconnections between nodes of
percent of the faults, and the next several thousand cells that are to be connected are as short as possible.
are needed to increase the coverage to 90 percent. The This is a nontrivial problem and the better the place­
job is very tedious and usually not looked forward to. ment, the smaller the chip will probably be, and,
One solution to this problem is to build testability therefore, the cheaper the piece part cost.
into the design. The keywords in testability are con­ The more information that is given to a place pro­
trollability and observability (C&O). A design is consid­ gram, the better placement it will produce. The hier­
ered easy to test if most of the nodes have high C&O. archical information available in the connectivity file
If testability was thought about early in the design is a great starting point for a placement program. For
process, this will probably be the case. example, if a subnetwork in the hierarchy is a coun­
ter, the cells in the counter will obviously be con­
Scan chains and combinational test generation: What
nected together and should be placed in close prox­
can be done near the end of the design process with a
imity to each other.
circuit that is hard to test? One solution to the testa­
The placement process is also interactive, that is, a
bility problem is to use scan chains. The fact that it is
placement is done and then optimized and then the
easy to automatically generate tests for combinational
circuits and difficult to generate tests for sequential possible routing is analyzed and the placement is op­
circuits led to this solution. timized again. The optimization is usually transpos­
ing cells and also reflecting them and making them
The circuit is basically altered so that in a test mode,
easier to route to. A good placement program will
all the flip-flops are tied together in a chain. The input
save a set of variables that describe how good the
of each flip-flop is multiplexed between the normal
circuit operation input and a test mode input that is placement was so that when the next optimization is
the output of the previous flip-flop in the scan chain. done, there is a good starting point from which to
In test mode, a serial stream of bits is clocked into the begin.
flip-flops, the circuit is run in normal mode for one Signal Routing
clock cycle, and then the bits are shifted out. It is Once a good placement of cells has been done, the
obvious that the controllability and observability of nodes of the cells are connected via routing lines.

JANUARY 1985 31
This is usually done in poly-silicon in one direction However, if the pre- and post-layout simulations
(horizontal or vertical) and in metal in the other; Fig. disagree, the circuit should be looked at in detail. The
13 gives a subset of a finished placed-and-routed cir­ usual cause for disagreement is that a signal did not
cuit. Routing is also a nontrivial problem as the size have time to reach its desired logic level before the
of the device is directly affected on how good of latching edge of the system clock. The extra delay due
a routing job is done. Many algorithms are imple­ to the routing capacitance or large fanout causes the
mented in different routers, and this is not the place signal propagation time to increase to an unaccept­
for analysis of different schemes. able level. The cure for this problem is to either redo
The routing task is also interactive in that a shot at the layout, paying particular attention to these failing
routing is done and then can be optimized or the nodes, or to replace the cell, sourcing the signal with
placement can be optimized and then the router can a higher powered version of the cell. If this second
run again. The goal is to reduce dead space on the method is chosen, the circuit will have to be replaced
silicon. A typical routing job will cause the routing as well as rerouted with the new high-powered cells.
area to be less than four times the area that the stan­ If the place and route programs are sophisticated
dard cells require. enough, they will store their optimized placement
and routing variables so that the addition of high
Correct by Construction powered cells will not cause too many problems when
This mode of place and route via design aids not the programs are run again.
only yields a fairly optimized silicon design but
Clock Skew
should also yield a mask set that is "correct by con­
Another concern at layout time is that the system
struction." The router should not cross any wires; nor
clock be given precedence at routing time. The system
should he route any signals to the wrong place. This
clock will be routed to every flip-flop in the circuit,
is a very important aspect of the layout process as a
and the idea of a synchronous design is that all out­
lot of time need not be wasted verifying the layout
puts change at the same time. The routing and fanout
with design rule checkers because of the assumption
capacitance of the clock signal will obviously be very
that the cells are correct and the routing is correct. It
high, and the clock signal should be boosted with
was done without the intervention of human hands,
high powered buffers. Care should be taken to ensure
and if the design aid is bug free, the layout should be
that minimal skew be introduced by the layout. Too
correct.
much clock skew could cause the circuit to mis­
Capacitance Extraction behave, especially in a circuit with a fast clock and
Once the layout is complete, the circuit should be very short time between latching edges. A transistor-
resimulated. The delay of every node has several com­ level simulation is best run on the system clock node
ponents: the delay of the rise of fall time of the gate, to ensure that it will not be delayed by any great ex­
the delay due to the sum of the input capacitances of tent. Cures for this problem are to boost the clock sig­
all the gates fanned out to, and the delay due to the nal and further optimize the clock signal routing.
routing capacitance. The first two delays are table
Fabrication
lookups, as these numbers should be part of the stan­
The verified layout that includes line-width control
dard cell library. There are two methods of extracting
and alignment features is compensated on the appro­
the routing capacitance. One is to run an extractor on
priate mask levels for alignment tolerances, process­
the routing layout and produce a number for the ca­
ing, etc., and is best done by the foundry that is going
pacitance of each routing path. The other, simpler
to produce the device. If several designs are being
method is to keep track of the capacitance as the rout­
proven in at the same time, it is usually a good idea to
ing paths are "laid down." Again, because the routing
put them on the same wafer in a multiproject fashion.
is done automatically, the router should have all the
Even though this may mean some wasted silicon area,
information in hand to produce the capacitance lists
ultimately it could result in lesser developmental cost
for each node.
and faster turnaround time. Once the designs are
proven-in, an individual mask set can be ordered for
Identify Cells with Large Fanout and each chip. The process cycle is normally a 6-to-10-
High Routing Capacitances week time period. On a prove-in lot, it is usually good
The capacitance information from the layout should practice to hold a few wafers out of the lot at each
be fed back to the simulator for a finer detailed sim­ mask step. This enables one to quickly recover if the
ulation. Some sort of multiple delay or timing simula­ first parts were less than fully functional and needed
tion is run on the circuit taking into account all the a one or two mask level change. It is also a good idea,
possible sources of capacitance. This simulation is if the first parts work, to go and exercise the other
then compared to the original simulations of the cir­ wafers for the extremes of process spread.
cuit. If the simulations match, the circuit is in good
shape and it's time to order a mask set and start pop­ Device Testing
ping out chips. The foundry will usually provide tested wafers or
32 IEEE CIRCUITS A N D DEVICES MAGAZINE
tested prototypes. It is very important that the de­ References
signer test the part in the system for proper operation [I] L. A. Fajardo, C. C. Liaw, and M. Tong, "A System for High
and exercise it thoroughly for its functionality. Very Level Design Capture and Synthesis/' AT&T Bell Labora­
tories Technical Journal, to appear.
often, comparison of the measured data with simu­
[2] B. R. Chawla, H. K. Gummel, and P. Kozak, "MOTIS—An
lated results point out clearly the robustness of the MOS Timing Simulator," IEEE Trans. Circuits and Systems, vol.
simulation/modeling techniques and is very often a CAS-22, no. 12, pp. 9 0 1 - 9 1 0 , Dec. 1975.
good metric for future designs. Extremes of tempera­ [3] E. Frey, "ESIM: A Functional Level Simulation Tool," Proc.
tures and power supply should be carefully studied 1984 International Conference on Computer-Aided Design,
Santa Clara, Calif., Nov. 1 2 - 1 5 , 1984.
for compliance with the specifications. Contrary to
[4] A. K. Bose, "A System of Computer Aids for LSI Design,"
popular claims, even the simplest of designs that The 3rd International Conference on Semi-Custom IC's, Lon­
produce perfectly functional prototypes go through don, England, Nov. 1 - 3 , 1983.
at least one mask iteration in manufacture, and it is a [5] V. D. Agrawal, A. K. Bose, P. Kozak, H. N. Nham, and E.
good idea to ensure that all of your changes be dis­ Pacas-Skewes, "A Mixed-Mode Simulator," Proc. 17th Design
Automation Conference, Minneapolis, Minn., June 2 3 - 2 5 ,
cussed carefully with your foundry, before the final
1980.
design is approved for large volume production. In [6] J. Dussault, C. C. Liaw, M. M. Tong, "A High Level Synthesis
the case of mixed analog/digital circuitry, a week or so Tool for MOS Chip Design," Proc. 21st Design Automation
spent in reviewing the test program and ensuring all Conference, Albuquerque, New Mexico, June 2 5 - 2 7 , 1984.
aspects of performance are adequately tested is es­ [7] L. W. Nagel, "SPICE2: A Computer Program to Simulate
Semiconductor Circuits," University of California, Berkeley,
sential to the ultimate success of the program. Early
ERL Memo no. ERL-M520, May 1975.
lot-test statistics should be carefully reviewed with [8] A. E. Dunlop, "SLIM—The Translation of Symbolic Layouts
the foundry for reordering the test sequence to en­ into Mask Data," Proc. 17th Design Automation Conference,
sure that the test time (this could be more than half pp. 5 9 5 - 6 0 2 , June 1980.
the cost of the final product) is minimized. Our expe­ [9] A. Kessler, "SIMULYZER: A Design through Testing CAE
Workstation," 1983 Bell System Conference on Electronic
rience indicates inadequate review of testing with the
Testing, Princeton, NJ, Oct. 4 - 6 , 1983.
foundry is the dominant cause of yield problems in [10] T. Yoshimura, "An Efficient Channel Router," Proc. 21st De­
large-volume manufacture. It is our feeling that mak­ sign Automation Conference, Albuquerque, New Mexico,
ing one of a kind is usually a much easier task than to June 2 5 - 2 7 , 1984.
be able to make several of them in large volume; [II] M. Burstein and R. Pela vin, "Hierarchical Wire Routing,"
IEEE Trans Computer-Aided Des. of ICS, vol. CAD-2, no. 4,
hence, we would like to repeat that the test data be
pp. 2 2 3 - 2 3 4 , 1983.
carefully reviewed for any design sensitivities that
[12] Ε. I. Muehldorf and A. D. Savkar, "LSI Logic Testing—An
were overlooked. Overview," IEEE Trans on Electronic Computers, vol. C-30,
no. 1, pp. 1 - 1 7 , Jan. 1981.
Concluding Remarks [13] S. DasGupta, P. Goel, R. G. Walther, and T. W. Williams, "A
Variation of LSSD and Its Implication on Design and Test
In this paper, we have attempted to expose the
Generation," 1982 International Test Conf., pp. 6 3 - 6 6 , Nov.
practicing engineer to the process of designing an in­ 1982.
tegrated circuit and getting it into large-volume man­ [14] M. S. Abadir and H. K. Reghbati, "Test Generation for LSI:
ufacture. No claim is made that all the issues have A Case Study," Proc. 21st Design Automation Conference,
been covered exhaustively; the issues are complex Albuquerque, New Mexico, June 2 5 - 2 7 , 1984.
[15] N. H. J. Weste, "MULGA—An Interactive Symbolic Layout
and numerous to cover in any single work like this
System for the Design of Integrated Circuits," Bell System
one. In fact, everyday we learn a few more ways of Technical Journal, July-Aug., 1981.
making our design tasks a little less painful. It is our [16] S. Y. H. Su and T. Lin, "Functional Testing Techniques for
hope that after reading this work, at least some of you Digital LSI/VLSI Systems," Proc. 21st Design Automation
would say: "Gee. . . It isn't that bad after all." Conference, Albuquerque, New Mexico, June 2 5 - 2 7 , 1984.
[17] B. D. Richard, "A Standard Cell Initial Placement Strategy,"
Included is a list of valuable references that helped
Proc. 21st Design Automation Conference, Albuquerque,
in the writing of this tutorial. We would like to thank New Mexico, June 2 5 - 2 7 , 1984.
the reviewers for pointing out that the methodology [18] M. Palczewski, "Performance of Algorithms for Initial Place­
suggested may not always be economically viable, ment," Proc. 21st Design Automation Conference, Albuquer­
particularly in a "small company" environment. que, New Mexico, June 2 5 - 2 7 , 1984.

Acknowledgments

We apologize to the many whose works have not period of ten years. We would like to thank K. R.
been referenced. The material in this paper is the sum­ Laker and A. S. Sedra for giving us this opportunity
mary of the design experiences of many a contributor and T. M. Dennis for his support.
with whom the authors have been associated over a
33
JANUARY 1985
 Andy Kessler has been working in the area of computer-aided en­
gineering and VLSI design for the past four years. He graduated
from Cornell University in 1980 with a B.S.E.E. and the University
of Illinois in 1981 with an M.S.E.E. Mr. Kessler has presented pa­
pers at the 1982 International Conference of Circuits and Comput­
ers and at 1983 Bell System Conference on Electronic Testing. He is
a member of the Eta Kappa Nu and Tau Beta Pi honor societies, and
his interests include music, sports, and Siberian Huskies. Dr. Kes­
sler is currently with AT&T Information Systems.

A. Ganesan graduated from the Indian Institute of Technology,

Madras, with a Bachelor's degree in electrical engineering in 1975
and with a Master's degree in electrical engineering from the State
University of New York at Stonybrook in 1976. He joined General
Instrument Corporation in August 1977. In January 1980, he left GI
A. J. Kessler as a CAD manager and joined Bell Labs at Holmdel. After a short
break in 1981 as a Group Leader in RCA corporation, he rejoined
AT&T in 1982 where he is currently a supervisor for an Integrated
Circuit Design group. He has served as an adjunct faculty at
several universities and is the author of several papers in the analog
signal processing area. His current interests are in the area of
computer-aided design, data communication, and integrated cir­
cuits and systems.

A. Ganesan

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