STD9NM50N

Datasheet

Automotive-grade N-channel 500 V, 730 mΩ typ., 11 A MDmesh II

Power MOSFET in a DPAK package

Features
TAB
Order code VDS RDS(on) max. ID

2 3 STD9NM50N 500 V 790 mΩ 5A

1

DPAK
• AEC-Q101 qualified
D(2, TAB) • 100% avalanche tested
• Low input capacitance and gate charge
• Low gate input resistance

Applications
G(1)

• Switching applications

S(3)
Description
AM01475v1_noZen

This device is an N-channel Power MOSFET developed using the second generation
of MDmesh technology. This revolutionary Power MOSFET associates a vertical
structure to the company’s strip layout to yield one of the world’s lowest on-resistance
and gate charge. It is therefore suitable for the most demanding high efficiency
converters.

Product status link

STD9NM50N

Product summary

Order code STD9NM50N

Marking 9NM50N
Package DPAK
Packing Tape and reel

DS8666 - Rev 2 - May 2023 www.st.com

For further information contact your local STMicroelectronics sales office.
 STD9NM50N
Electrical ratings

1 Electrical ratings

Table 1. Absolute maximum ratings

Symbol Parameter Value Unit

VGS Gate-source voltage ±25 V

Drain current (continuous) at TC = 25 °C 5

ID A
Drain current (continuous) at TC = 100 °C 3

IDM (1) Drain current (pulsed) 20 A

PTOT Total power dissipation at TC = 25 °C 45 W

IAR Avalanche current, repetitive or non-repetitive (pulse width limited by TJ max) 2 A

EAS Single pulse avalanche energy (starting TJ = 25 °C, ID = IAR, VDD = 50 V) 140 mJ

dv/dt (2) Peak diode recovery voltage slope 15 V/ns

Tstg Storage temperature range °C

-55 to 150
TJ Operating junction temperature range °C

1. Pulse width limited by safe operating area.

2. ISD ≤ 5 A, di/dt ≤ 400 A/µs, VDS (peak) ≤ V(BR)DSS, VDS = 80% V(BR)DSS.

Table 2. Thermal data

Symbol Parameter Value Unit

RthJC Thermal resistance, junction-to-case 2.78 °C/W

RthJA (1)
Thermal resistance, junction-to-ambient 50 °C/W

1. When mounted on 1 inch² FR-4, 2 Oz copper board.

DS8666 - Rev 2 page 2/15

 STD9NM50N
Electrical characteristics

2 Electrical characteristics

TC = 25 °C unless otherwise specified.

Table 3. On/off states

Symbol Parameter Test conditions Min. Typ. Max. Unit

V(BR)DSS Drain-source breakdown voltage ID = 1 mA, VGS = 0 V 500 V

VGS = 0 V, VDS = 500 V 1

IDSS Zero gate voltage drain current µA
VGS = 0 V, VDS = 500 V, TC = 125 °C (1)
100

IGSS Gate body leakage current VGS = ±25 V, VDS = 0 V ±100 nA

VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 2 3 4 V

Static drain-source on-

RDS(on) VGS = 10 V, ID = 2.5 A 730 790 mΩ
resistance

1. Specified by design, not tested in production.

Table 4. Dynamic

Symbol Parameter Test conditions Min. Typ. Max. Unit

Ciss Input capacitance - 364 - pF

Coss Output capacitance VDS = 50 V, f = 1 MHz,VGS = 0 V - 33 - pF

Crss Reverse transfer capacitance - 1.2 - pF

Coss eq. (1) Equivalent output capacitance VGS = 0 V, VDS = 0 to 50 V - 147.5 - pF

Rg Intrinsic gate resistance f = 1 MHz, ID = 0 A - 5.4 - Ω

Qg Total gate charge - 14 - nC

VDD = 400 V, ID = 5 A, VGS = 0 to 10 V
Qgs Gate-source charge (see Figure 12. Test circuit for gate charge - 3 - nC
behavior)
Qgd Gate-drain charge - 7 - nC

1. Coss eq. is a constant capacitance value that gives the same charging time as Coss while VDS is rising from 0 V to the stated
value.

Table 5. Switching times

Symbol Parameter Test conditions Min. Typ. Max. Unit

td(on) Turn-on delay time - 7 - ns

VDD = 250 V, ID = 5 A, RG = 4.7 Ω,
tr Rise time - 4.4 - ns
VGS = 10 V (see Figure 11. Test circuit
td(off) Turn-off delay time for resistive load switching times and - 25 - ns
Figure 16. Switching time waveform)
tf Fall time - 8.8 - ns

DS8666 - Rev 2 page 3/15

 STD9NM50N
Electrical characteristics

Table 6. Source-drain diode

Symbol Parameter Test conditions Min. Typ. Max. Unit

ISD Source-drain current - 5 A

ISDM (1) Source-drain current (pulsed) - 20 A

VSD (2) Forward on voltage ISD = 5 A, VGS = 0 V - 1.5 V

trr Reverse recovery time - 187 ns

ISD = 5 A, di/dt = 100 A/µs, VDD = 60 V
Qrr Reverse recovery charge (see Figure 13. Test circuit for inductive - 1.3 μC

IRRM load switching and diode recovery times)

Reverse recovery current - 14 A

trr Reverse recovery time ISD = 5 A, di/dt = 100 A/µs, VDD = 60 V, - 224 ns

Qrr Reverse recovery charge TJ = 150 °C (see Figure 13. Test circuit for - 1.5 μC
inductive load switching and diode recovery
IRRM Reverse recovery current times) - 13 A

1. Pulse width limited by safe operating area.

2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%.

DS8666 - Rev 2 page 4/15

 STD9NM50N
Electrical characteristics (curves)

2.1 Electrical characteristics (curves)

Figure 1. Safe operating area Figure 2. Normalized transient thermal impedance

AM07915v1
ID
(A)

10
is

10µs
R re a
)
on
ax a
S(
m th is

D
by n

100µs
d ni

1
ite io
m at
Li p e r
O

1ms
10ms
0.1 Tj=150°C
Tc=25°C
S ingle
puls e
0.01
0.1 1 10 100 VDS (V)

Figure 3. Typical output characteristics Figure 4. Typical transfer characteristics

AM07917v1 AM07918v1
ID ID
(A) (A)
VGS =10V VDS = 20 V
10 10
7V

8 8
6V

6 6

4 4

5V
2 2

0 0
0 10 20 30 VDS (V) 0 2 4 6 8 VGS (V)

Figure 5. Typical gate charge characteristics

Figure 6. Typical drain-source on-resistance
AM03195v2
VGS VDS AM07919v1
R DS (on)
(V) (V) (mΩ)
VDS VDD = 400V VGS
12 770
ID = 5 A 500 VGS =10V
760
10 750
400
740
8
300 730
6 720
200 710
4
700
2 100
690
680
0 0 0 1 2 3 4 5 ID(A)
0 5 10 15 Q g (nC)

DS8666 - Rev 2 page 5/15

 STD9NM50N
Electrical characteristics (curves)

Figure 7. Typical capacitance characteristics Figure 8. Normalized gate threshold vs temperature

AM07921v1 AM07923v1
C VGS (th)
(pF) (norm)

ID = 250 µA
1000
Cis s
1.00

100
0.90
Cos s

10
0.80
Crs s

1 0.70
0 1 10 100 VDS (V) -50 -25 0 25 50 75 100 TJ (°C)

Figure 9. Normalized on-resistance vs temperature Figure 10. Normalized breakdown voltage vs temperature
AM07924v1 AM07925v1
R DS (on) V(BR)DSS
(norm) (norm)
2.1
ID = 2.5 A ID = 1 mA
1.05
1.7
1.03

1.01
1.3
0.99

0.97
0.9
0.95

0.5 0.93
-50 -25 0 25 50 75 100 TJ (°C) -50 -25 0 25 50 75 100 TJ (°C)

DS8666 - Rev 2 page 6/15

 STD9NM50N
Test circuits

3 Test circuits

Figure 11. Test circuit for resistive load switching times Figure 12. Test circuit for gate charge behavior

VDD

12 V 47 kΩ
1 kΩ
100 nF
RL
2200 3.3
+ μF μF VDD
VD IG= CONST
VGS 100 Ω D.U.T.

VGS
RG D.U.T. pulse width +
2.7 kΩ
2200 VG
pulse width μF
47 kΩ

1 kΩ

AM01468v1 AM01469v1

Figure 13. Test circuit for inductive load switching and Figure 14. Unclamped inductive load test circuit
diode recovery times

A A A
D L
fast 100 µH VD
G D.U.T. diode
S B 3.3 1000 2200 3.3
B B + µF
25 Ω D
µF + µF VDD µF VDD
ID
G D.U.T.
+ RG S

_ Vi D.U.T.

pulse width

AM01470v1
AM01471v1

Figure 15. Unclamped inductive waveform Figure 16. Switching time waveform

ton toff
V(BR)DSS
td(on) tr td(off) tf
VD

90% 90%
IDM

10% VDS 10%

ID 0

VDD VDD
VGS 90%

0 10%

AM01472v1 AM01473v1

DS8666 - Rev 2 page 7/15

 STD9NM50N
Package information

4 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.

4.1 DPAK (TO-252) type A2 package information

Figure 17. DPAK (TO-252) type A2 package outline

0068772_type-A2_rev34

DS8666 - Rev 2 page 8/15

 STD9NM50N
DPAK (TO-252) type A2 package information

Table 7. DPAK (TO-252) type A2 mechanical data

mm
Dim.
Min. Typ. Max.

A 2.20 2.40
A1 0.90 1.10
A2 0.03 0.23
b 0.64 0.90
b4 5.20 5.40
c 0.45 0.60
c2 0.48 0.60
D 6.00 6.20
D1 4.95 5.10 5.25
E 6.40 6.60
E1 5.10 5.20 5.30
e 2.159 2.286 2.413
e1 4.445 4.572 4.699
H 9.35 10.10
L 1.00 1.50
L1 2.60 2.80 3.00
L2 0.65 0.80 0.95
L4 0.60 1.00
R 0.20
V2 0° 8°

DS8666 - Rev 2 page 9/15

 STD9NM50N
DPAK (TO-252) type A2 package information

Figure 18. DPAK (TO-252) recommended footprint (dimensions are in mm)

FP_0068772_34
FP_0068772_34

DS8666 - Rev 2 page 10/15

 STD9NM50N
DPAK (TO-252) packing information

4.2 DPAK (TO-252) packing information

Figure 19. DPAK (TO-252) tape outline

10 pitches cumulative
tolerance on tape +/- 0.2 mm

Top cover P0 D P2
T tape
E

F
K0 W
B1 B0

For machine ref. only A0 P1 D1

including draft and
radii concentric around B0
User direction of feed

Bending radius
User direction of feed

AM08852v1

DS8666 - Rev 2 page 11/15

 STD9NM50N
DPAK (TO-252) packing information

Figure 20. DPAK (TO-252) reel outline

40mm min.
access hole
at slot location
B

D C

N
A

Tape slot G measured

in core for at hub
Full radius tape start
2.5mm min.width

AM06038v1

Table 8. DPAK (TO-252) tape and reel mechanical data

Tape Reel

mm mm
Dim. Dim.
Min. Max. Min. Max.

A0 6.8 7 A 330
B0 10.4 10.6 B 1.5
B1 12.1 C 12.8 13.2
D 1.5 1.6 D 20.2
D1 1.5 G 16.4 18.4
E 1.65 1.85 N 50
F 7.4 7.6 T 22.4
K0 2.55 2.75
P0 3.9 4.1 Base qty. 2500
P1 7.9 8.1 Bulk qty. 2500
P2 1.9 2.1
R 40
T 0.25 0.35
W 15.7 16.3

DS8666 - Rev 2 page 12/15

 STD9NM50N

Revision history
Table 9. Document revision history

Date Version Changes

21-Sep-2011 1 First release.

Updated Section 4.1 DPAK (TO-252) type A2 package information.
08-May-2023 2
Minor text changes.

DS8666 - Rev 2 page 13/15

 STD9NM50N
Contents

Contents
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4.1 DPAK (TO-252) type A2 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2 DPAK (TO-252) packing information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

DS8666 - Rev 2 page 14/15

 STD9NM50N

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© 2023 STMicroelectronics – All rights reserved

DS8666 - Rev 2 page 15/15