IC OVERVIEW

RTL DESIGN AND VERIFICATION

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 COURSE INTRODUCTION

Khóa Học Thiết Kế Vi Mạch Cơ Bản - Trung Tâm Đào Tạo Thiết Kế Vi Mạch ICTC

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 SYMBOL LEGEND

SUMMARY

HOMEWORK

QUESTION

SELF-LEARNING

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Session 08: Verilog
Fundamental - Part 5 - 1. Parameter

Parameter & FSM 2. Compiler directive (self-learning)

3. Function
.
4. Generate

5. FSM

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1. Parameter

2. Compier directive (self-learning)

3. Function

4. Generate

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 WHY NEED TO USE PARAMETER?
▪ Below is our counter example. What if we want to change to 16-bit?
module counter( module counter(
input wire clk, input wire clk,
input wire rst_n, input wire rst_n,
output wire overflow, output wire overflow,
output reg [7:0] count output reg [15:0] count
) )

//Combination logic //Combination logic

always @ (posedge clk or negedge rst_n) begin always @ (posedge clk or negedge rst_n) begin
if( !rst_n) if( !rst_n)
count <= 8’h00; count <= 16’h00;
else else
count <= count + 1’b1; count <= count + 1’b1;
end end

assign overflow = (count == 8’hff); assign overflow = (count == 16’hff_ff);

endmodule endmodule
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 PARAMETER

▪ Parameter can be used to improve the readability and reusability.

▪ Syntax: parameter <P_NAME> = <VALUE>;
▪ 2 most popular usages of parameter
//signal declaraion parameter CNT_W = 8;
wire [7:0] cnt_pre; //signal declaration
reg [7:0] cnt; wire [CNT_W-1:0] cnt_pre; Later on, just need
reg [CNT_W-1:0] cnt; to change the
parameter if any
design changes (bit-
parameter CNT_MAX = 8’hff;
width changes or
//constant max value changes
if( cnt == 8’hff ) begin
… //constant
if( cnt == CNT_MAX) begin
end
…
end

TRY TO USE PARAMETER FOR SENSITIVE BIT-WIDTHS OR CONSTANTS !!! 7

 PARAMETER

▪ Parameter must be declared inside module.

▪ Other modules can have same parameter name, but has different value.
▪ The parameter only takes effect inside its module
module aaa ;
parameter CNT_W = 8;
cnt is 8 bit-width
…
in aaa module reg [CNT_W-1:0] cnt;
endmodule These 2 modules has
same parameter name
but different value.
module bbb ;
parameter CNT_W = 16;
cnt is 16 bit-width ….
in bbb module reg [CNT_W-1:0] cnt;

endmodule

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 PARAMETER DECLARATION
▪ Parameter can be declared as below
module aaa ( <port_list> ); module aaa #(parameter PAR1 = VAL_PAR1,
//parameter list parameter PAR2 = VAL_PAR2)
parameter PAR1 = VAL_PAR1; (<port_list>);
parameter PAR2 = VAL_PAR2;
… //port & data type declaration
//ports & data type declaration //logic description
//logic description endmodule
endmodule

▪ The second way is useful if the port declaration is inside the port list
module counter module counter #(parameter CNT_W=8)
( input wire clk , ( input wire clk , Compiler can
Compiler can input wire rst_n, input wire rst_n, understand
not understand the CNT_W
the CNT_W output reg [CNT_W-1:0] cnt output reg [CNT_W-1:0] cnt
); );
parameter CNT_W = 8; …
endmodule endmodule
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 PARAMETER OVERRIDE
▪ Parameters can be overridden with new values during module instantiation
module top #(parameter ADDR_W=8, module tb;
parameter DATA_W=16) //module instantiation override: override by position
( top #(16, 32) u_dut ( <port_list>);
input wire [ADDR_W-1:0] addr, endmodule
output wire [DATA_W-1:0] data
module tb;
);
//module instantiation override: override by name
… This way is
top #(.DATA_W(32), .ADDR_W(16)) u_dut ( <port_list>);
recommended
endmodule
endmodule
module tb;
//module instantiation
top u_dut ( <port_list>);
//Override using defparam
defparam dut.ADDR_W = 16;
defparam dut.DATA_W = 32;
endmodule

If parameters are not overriden the during module instantiation, they will keep the
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default values declared the module.
 PARAMETER PASSING
▪ Parameters can be passed from upper hierarchy.

module tb;
module top #(parameter ADDR_W=8,
parameter TB_ADDR_W = 16;
parameter DATA_W=16)
parameter DATA_W = 32;
(
//passing the parameter to module
input wire [ADDR_W-1:0] addr,
top #(.ADDR_W (TB_ADDR_W, .DATA_W(DATA_W)) u_dut ( <port_list>);
output wire [DATA_W-1:0] data
…
);
endmodule
…

endmodule

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1. Parameter

2. Compier directive (self-learning)

3. Function

4. Generate

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 DEFINE (SELF-LEARNING)
▪ “define” is a compiler directive used to define macros, which are essentially text substitutions.
▪ “define” can be used similar to parameter, but it is global, means all the module in the file will be
affected by this define

`define ADDR_W 8
`define DATA_W 16
module top (
input wire [`ADDR_W-1:0] addr,
input wire [`DATA_W-1:0] data
);
…
Both top and sub
endmodule
module use same define
module sub (
input wire [`ADDR_W-1:0] sub_addr,
input wire [`DATA_W-1:0] sub_data
);
…
endmodule
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 DEFINE (SELF-LEARNING)
▪ When using “define”, it is recommended to create a file as shown below

def.v
`define ADDR_A 8’h00
`define ADDR_B 8’h04
module top;
`include “def.v”
…
endmodule

▪ Since “define” is a global compiler directive, it’s recommended to use `undef to

limit the effective scope.
module top;
`include “def.v”
…
`undef ADDR_A
`undef ADDR_B
endmodule 14
 DEFINE (SELF-LEARNING)
▪ “define” can be used to replace text to simplified common logic
`define ff_nrst always @(posedge clk or negedge rst_n) begin

module counter(
input wire clk,
always @ (posedge clk or negedge rst_n) begin
input wire rst_n,
if( !rst_n)
output wire overflow,
count <= 8’h00;
output reg [7:0] count
else
)
count <= count + 1’b1;
`ff_nrst
end
if( !rst_n)
count <= 8’h00;
else
count <= count + 1’b1;
end

assign overflow = (count == 8’hff);

endmodule
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 CONDITIONAL COMPILATION (SELF-LEARNING)
▪ Compiler directive `ifdef and `endif can be used for conditional compilation

module test (
input wire a ,
input wire b , test
`ifdef EXTD
input wire c, a
z
`endif b
output wire z
c
);

`ifndef EXTD //EXTD is not defined

assign z = a | b; The red highlighted only available when
`else macro “EXTD” is defined by `ifdef directive
assign z = (a | b) & c;
`endif
endmodule

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1. Parameter

2. Compier directive (self-learning)

3. Function

4. Generate

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 FUNCTION
▪ Function is a procedural block to create combinational logic.
▪ Function can be used to split the code to smaller parts that can be reused.

//How to define a function with 2 arguments

function <range> function_name;
At least 1 input.
input <range> argument1;
Must not have
output or inout type input <range> argument2;

//internal variable declaration

begin
Blocking assignment function_name = expression;
must be used
end
endfunction

Calling a function:
LHS = function_name( argument1, argument2)
Note: this can be a continuous assignment or procedural assignment 18
 FUNCTION RULE

▪ Function can be synthesizable.

▪ No delay or timing control (# or @) can be used inside function.
▪ Non-blocking assignment is not allowed inside function.
▪ Function can not have multiple outputs. The return value of function is returned
via function_name.
▪ Function must be written inside module.

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 FUNCTION EXAMPLE
module top (
input wire in1,
input wire in2,
input wire in3,
input wire in4, u_and_gate_00 top
output wire out and_gate
); in1 out12 u_and_gate_02
wire out12; in2 and_gate
wire out34;
assign out12 = and_gate( in1, in2); u_and_gate_01 out
assign out34 = and_gate( in3, in4);
and_gate
assign out = and_gate( out12, out34);
in3
in4 out34
function and_gate;
input a;
input b;

begin
and_gate = a & b;
end
Instead of using module as in previous
endfunction sessions, we can use function (only for
endmodule combinational logic)
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1. Parameter

2. Compiler directive (self-learning)

3. Function

4. Generate

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 LOOP GENERATE

Loop generate constructs allow for moudules with repetitive structure to be described in more
simple way.
The loop index must be declared by
“genvar”. This index is just for the synthesis
tool to know this is generate loop index. It
should not be used outside the loop
generate

genvar i;
assign c[0] = a[0] & b[0];
assign c[1] = a[1] & b[1]; generate
assign c[2] = a[2] & b[2]; for( i=0; i<5; i=i+1) begin :<name> //(name is optional)
assign c[3] = a[3] & b[3]; assign c[i] = a[i] & b[i];
assign c[4] = a[4] & b[4]; end
These are
equivalent
endgenerate

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 CONDITIONAL GENERATE

▪ Conditional generate construct can be used to select which code is active based on parameter.
▪ The simulation and synthesis tool only process with the codes corresponding to the parameter value.

parameter BIT_DEPTH = 8; Only process_8b logic is parameter BIT_DEPTH = 8;

active, no logic for others
generate function (process_10b, generate
if( BIT_DEPTH == 8 ) begin process_12b) case ( BIT_DEPTH )
process_8b u_proc (…); 8:
end else if( BIT_DEPTH == 10 ) begin begin
process_10b u_proc (…); process_8b u_proc (…);
end else begin end
process_12b u_proc (…); 10:
end begin
endgenerate process_10b u_proc (…);
end
These are default:
equivalent begin
process_12b u_proc (…);
end
endcase
endgenerate

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 FSM OVERVIEW
❑ FSM stands for Finite-State Machine.
❑ FSM is used to describe:
❖ The behavior of a digital system with a finite number of states.
❖ Transitions between these states.
❖ Actions taken in response to these transitions.
❑ The FSM has advantages:
❖ It makes it easy to control the operating sequence.
❖ It simplifies the debugging process for the design.
FSM is crucial for modeling and controlling sequential logic in digital circuits.

For example
AB: state ▪ State = 00, x = 0 -> next state = 00, y = 0
x: input ▪ State = 00, x = 1 -> next state = 01, y = 0
▪ State = 01, x = 0 -> next state = 00 , y = 0
y: output
….
▪ State = 11, x = 1 -> next state = 00, y = 1
 FSM COMPONENTS

❑An FSM consists of 3 fundamental components:

❖ Next State Logic: This is a combinational circuit that depends on the inputs of the FSM and
the current state from the state memory. It determines the next state based on the current
state and inputs.
❖ State memory: This component stores the current state of the FSM. It can be implemented
using flip-flops or latches and receives inputs from the next state logic.
❖ Output logic: this is another combinational circuit that generates outputs corresponding to
the current state. In the case of a Mealy FSM, this block can also take inputs directly from
the FSM's inputs, influencing the outputs based on both the current state and inputs.
 FSM CLASSIFICATION

❑FSM is divided into 2 types:

❖ Moore FSM is a type with a circuit that generates outputs that do not directly
depend on the FSM inputs
❖ Mealy FSM is a type with a circuit that generates outputs directly depending on
the FSM inputs.
 FSM COMPONENTS
FSM is just an application of our very basic FF circuit with
combinational logic and feedback path

FSM general diagram

Feedback path
General diagram of FF
and combinational logic input Combinaitonal
output
Combinaitonal
with feedback path that logic State logic

we learned before FFs

clk

rst_n
 FSM CLASSIFICATION
Comparison

Num Mealy FSM Moore FSM

Output Outputs are determined by both the current Outputs are determined by current state.
state and current inputs.
Complexity More complex because outputs depend on both More simple because the outputs are state-dependent and do
states and inputs, but this can lead to fewer not change with inputs within the same state. Moore FSM can
states than an equivalent Moore machine. have more states than Mealy FSM.
Timing Worse. Outputs can change in response to input Better. Outputs change only at state transitions (output of Flip-
changes even within the same clock cycle. Critical Flop)
path is from input to output.
Use cases Suitable for applications where immediate Suitable for applications where stable outputs are required,
reaction to input changes is critical. and the reaction time to input changes is not critical.
 EXAMPLE OF FSM DESIGN

A game machine has 2 states: locked or unlocked. Normally, it is in the locked state; when a coin is
inserted, it unlocks. When the start button is pressed, it locks again. Design FSM to control this game
machine.

clk

rst_n

fsm_ctrl lock
coin

start
 EXAMPLE OF FSM DESIGN

coin=1
coin=0 LOCK UNLOCK start=0
start=1

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 FSM TIMING DIAGRAM

Code wavedrom for FSM

{signal: [
{name: 'clk', wave: 'p..........'},
{name: 'rst_n', wave: '01.........'},
{name: 'coin', wave: '0...1.0....'},
{name: 'start', wave: '0......1.0.'},,
{name: 'state', wave: '=....=..=..',data:["LOCK","UNLOCK","LOCK"]},
{name: 'lock (mealy)', wave: '1...0..1...'},
{name: 'lock (moore)', wave: '1....0..1..'},
]}

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 LOGIC DIAGRAM

0
UNLOCK 1
LOCK
state_pre D ==
coin Q
state LOCK
UNLOCK D F.F lock (moore)
0 CK

LOCK 1 rst_n
==
lock (mealy)
start LOCK

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 FSM PRACTICE

▪ Create 08_ss8 folder in your home directory

▪ Copy /ictc/student_data/share/ico_final/08_ss8/fsm_ctrl to your 08_ss8
▪ Write the RTL to fsm_ctrl.v follows above diagram, you can choose either Mealy or Moore output
▪ Run simulation
▪ % make drc: check DRC
▪ % make all : run simulation with Moore FSM (your design is Moore FSM output)
▪ % make all MEALY_FSM=1 : run simulation with MEALY_FSM (your design is Mealy FSM output)
▪ Open the waveform to check if it is same with the sample waveform?

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 FSM CLASSIFICATION

Every Moore machine can be converted to a Mealy machine

and every Mealy machine can be converted to a Moore
machine. Moore machine and Mealy machine are equivalent.
 CONGRATULATIONS !!!
WE FINISHED ALL THE BASIC VERILOG FOR RTL DESIGN !!!

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 RTL DESIGN FLOW RECAP

Let’s review again the RTL Design Flow and see how we can apply into this course

Design Requirement Analyze design requirement from the

Analysis practice or homework
- Draw block diagram
- Draw waveform Create Design Specification
Write Verilog code follows design spec
- Draw logic diagram
- Synthesizable
Write RTL code
- Good coding style
Compilation and self- - Simple and clean
testing Compile, DRC and self-test

Synthesis and Design

Constraint (optional)

Design Review Review and feedback by lecturer

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 DESIGN SPECIFICATION EXAMPLE

Let’s see again our previous example of counter module.

The later projects in this course need to follow this style.

Part 1: describe feature and requirement:

▪ 8-bit counter using D-FF, low active async reset.
▪ When counter reach max value, it overflowed (overflow = 1) and count again.
▪ “overflow” is assert only when counter is overflowed and negate after that
▪ Counter only start counting when input “count_en” is High. Otherwise, keep current value.
▪ Counter’s value is initialized when “count_clr” is High regardless of count_en.

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 DESIGN SPECIFICATION EXAMPLE

Part 2: describe block diagram

clk

rst_n overflow

count_en counter
count[7:0]

count_clr

Block diagram

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 DESIGN SPECIFICATION EXAMPLE

Part 3: describe IO table

Signal Direction Bit-width Description

clk Input 1 Input clock

rst_n Input 1 Active low asynchronous reset

0: counter is in reset state
1: counter is in non-reset state
count_en Input 1 Counter enable
0: counter does not count
1: counter counts
count_clr Input 1 Counter clear
0: counter value is not reset
1: counter value is reset
overflow Output 1 Counter overflow
0: counter is not overflowed
1: counter is overflowed
count Output 8 Counter value output 0..255

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Input-Output description
 DESIGN SPECIFICATION EXAMPLE

Part 4: describe waveform (use excel, powerpoint, wavedrom)

Waveform (by wavedrom)

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 DESIGN SPECIFICATION EXAMPLE

Part 5: describe logic diagram (can use excel, power point, xcircuit)

0
0 count[7:0]
+1 1
8’h00 1
overflow
clk ==
count_en 8’hff ?
count_clr
rst_n

Logic diagram (by powerpoint)

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 SESSION 8
SUMMARY

SUMMARY:
❑ Parameter can be used to improve the readability and reusability.
❑ “define” can be used as macro or to replace text to simplified common logic.
❑ Function is a procedural block to create combinational logic and can be used to split
the code to smaller parts that can be reused.
❑ There are 2 types of generate: loop generate of conditional generate.
❑ FSM is an application of flip-flop feedback loop. The feedback loop is used to derive
next state.
❑ Need to follow the RTL design flow, do specification making before RTL coding !!!

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 Homework

Homework1.1 (5p): create a configurable counter module

▪ Copy /ictc/student_data/share/ico/08_ss8/counter_param to your 08_ss8
▪ Make the counter’s bit-width configurable by using a parameter CNT_W (counter bit-width)
▪ Default CNT_W is 8
▪ Run simulation with (1 <= CNT_W <= 16). The parameter value can be specified in the Makefile by adding -G<parameter> =
<value> in vsim command. See next slide
Example
o CNT_W=1, counter is configured as 1-bit counter and your testbench can check it.
o CNT_W=4, counter is configured as 4-bit counter and your testbench can check it.
o …
Note: don’t verify with CNT_W > 16 because the simulation will run very long.

clk count[CNT_W-1:0]

rst_n counter
overflow

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 TIP

▪ Parameter can be specified in the Makefile and pass to the testbench.

▪ When running simulation using make, we can configure the parameter via command line.

WIDTH ?= 8 //declare a variable. If user don’t type it in the command line, default value is 8

run:
vsim […] -GCNT_W=$(WIDTH) //assign CNT_W parameter = WIDTH variable

Run command:
>make build
>make run WIDTH=16 //run the simulation with CNT_W = 16

or simply type
> make all WIDTH = 16
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 Homework

Homework1.2 (5p): Make the full_adder become configurable

▪ Copy /ictc/student_data/share/ico/08_ss8/full_adder_param to your 08_ss8
▪ Make the full adder become configurable by using a parameter FA_BIT
▪ Default FA_BIT is 16 (full adder 16bit)
▪ Run simulation with (1 <= FA_BIT <= 32). The parameter value can be specified in the Makefile by
adding -G<parameter> = <value> in vsim command.
▪ Example
o FA_BIT = 1: full adder 1 bit
o FA_BIT = 20: full adder 20 bit

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 FSM PRACTICE
Homework2(*): Design an FSM to detect a sequence of “1011” in a given bit stream.
Note: the left most bit come first.
▪ “match” flag is asserted only when it detects the correct sequence
▪ Copy /ictc/student_data/share/ico/08_ss8/detect_string to your 08_ss8
▪ Draw state transition diagram and logic diagram (can choose either Moore or Mealy FSM) [4p]
▪ Write code in the detect_string.v [3p]
▪ Write simple testbench to drive the stream to DUT [3p]
clk

rst_n match
detect_string
stream

Given bit stream: match

110011001011001010101101101011111
Bit order match match match