Data Representation
• Fixed point representation
• Floating point representation
Fixed point representation
• It have limited range of values and have
relatively simple hardware.
Unsigned Numbers
Unsigned Representation
• Concept: All bits are used to represent the
magnitude of the number.
• Range:0 to 2n - 1.
• Example (n=8): The range is 0 to 28 - 1, which
is 0 to 255.
Signed Numbers
• Need to be able to represent both positive
and negative numbers
Following 3 representations
• Signed magnitude representation
• Signed 1's complement representation
• Signed 2's complement representation
Signed Magnitude Representation
• Concept: The most significant bit (MSB) is a
sign bit, and the remaining bits represent the
magnitude of the number.
• Range:- (2(n-1) - 1) to +(2(n-1) - 1).
• Zero Representation: Has two representations
for zero: a positive zero and a negative zero.
• Example (n=8): The range is - (2(8-1) - 1) to
+(2(8-1) - 1), which is -127 to +127.
1’s Complement Representation
• Concept: Signed number representation where
the MSB indicates the sign (0 = positive, 1 =
negative). Negative numbers are represented by
taking the bitwise complement of their positive
value.
• Range:- (2(n-1) - 1) to +(2(n-1) - 1).
• Zero Representation: Has two representations
for zero: a positive zero and a negative zero.
• Example (n=8): The range is - (2(8-1) - 1) to +(2(8-1) -
1), which is -127 to +127.
Two's Complement Representation
• Concept: The most efficient way to represent
signed numbers, where the MSB indicates the
sign.
• Range:-2(n-1) to +(2(n-1) - 1).
• Zero Representation: Has a single, unique
representation for zero.
• Example (n=8): The range is -2(8-1) to +(2(8-1) -
1), which is -128 to +127.
Addition and Subtraction of signed
magnitude numbers
Hardware for signed magnitude
addition and subtraction
• AVF- add overflow flip flop
BS B Register
AVF Complementer M (Mode Control)
Output
E Parallel adder Input carry
carry
S
AS A Register Load Sum
Flow chart for add and subtract operations
Subtract operation Add operation
Minuend in A Augend in A
Subtrahend in B Addend in B
=0 =1 =1 AS + B S =0
AS + BS
AS ≠ B S
AS = B S AS ≠ B S AS = B S
EA ← A + B + 1
AVF ← 0 EA ← A + B
=0 =1
A<B E A≥B AVF ← E
≠0 =0
A←A A
A←A+1 AS ← 0
AS ← AS
END
(Result in A and AS)
Signed 2’s complement addition and
subtraction
Flow chart
Multiplication Algorithms
Hardware Implementation for Signed-
Magnitude Multiplication
Flow Chart
Description
• Q multiplier
• B multiplicand
• A 0
• SC number of bits in multiplier
• E overflow bit for A
• Do SC times
– If low-order bit of Q is 1
• A←A+B
• Shift right EAQ
– If low-order bit of Q is 0
• Shift right EAQ
• Product is in AQ
Signed 2’s Complement Multiplication
• Booth Multiplication/Algorithm
Hardware for Booth Multiplication
Description
• QR multiplier
• Qn least significant bit of QR
• Qn+1 previous least significant bit of QR
• BR multiplicand
• AC 0
• SC number of bits in multiplier
Algorithm
Do SC times
QnQn+1 = 10
AC ← AC + BR + 1
QnQn+1 = 01
AC ← AC + BR
Arithmetic shift right AC& QR
SC ← SC – 1
Binary division
Hardware Algorithm –
Restoring Method
