8051 ARCHITECTURE

The following subsections summarize the 8051 architecture in brief. A reader may refer to a
standard text for details.
8051 Microcontroller Architecture
Figure 2.1 shows the architecture of the classic 8051 microcontroller. Classic means the original
version, based upon which new enhancements and versions are provided. The classic version
consists of following hardware:
1. A 12 MHz clock. Processor instruction cycle time is 1 us.
2. An 8-bit ALU. The internal bus width is 8-bit.
3. CISC (Complex Instruction Set Computer) architecture. [CISC provides many modes for
addressing operands in arithmetic, logical and other instructions. Several complex instructions
take more than one cycle time. Complex instructions implement in hardware not by separate
hardwired logic circuits for each instruction but by a microprogram control circuit.]
4. Special bit manipulation instructions.
5. A program counter, in which the initial default reset value defined by the processor is 0x0000.
6. A stack pointer, in which the initial default value defined by the processor is 0x07.
7. A simple architecture, with no floating-point processor, no cache, no memory management
unit, no atomic operations unit, no pipeline and no instruction level parallelism. There is no
DMA controller in the classic and most other versions.
8. A Harvard memory architecture.The program memory and data memory have separate address
spaces from 0x0000 and separate control signal(s).
9. On-chip RAM of 128 bytes. The 8052 version provides for RAM of 256 bytes; 32 bytes of
RAM are also used as four banks (sets) of registers. Each register-set (bank) thus has eight
registers. The external data/stack memory can be added upto 64 kB in most versions. In certain
8051 enhancements, this limit has been enhanced to 16 MB.
10. There are special function registers (SFRS). These are PSW (processor status word), A
(accumulator), B register, SP (stack pointer) and registers for serial IOs, timers, ports and
interrupt handler.
11. 8351 version has on-chip ROM; 8751 version EPROM; 8951 version has on-chip EEPROM
or flash memory of 4 KB. Several versions provide for higher capacity ROM. Additional
program memory can be added externally upto 64 KB. In extended 8051 and unified address
space versions (8051 EX and MX versions), this limit has been extended to 16 MB.
12. Two external interrupt pins, INTO and INT1.
13. Four ports P0, P1, P2 and P3 of 8 bits each in single chip modeThere are two and a serial
interface (SI). It can be programmed for three full duplex UART modes for a serial IO. [IO with
each bit of a word successive transmitted on the data line for a time interval.] The SI can also be
programmed for half duplex synchronous IO.
14. Classic version has no pulse width modulator and provides on support to DAC. (Section
1.3.7) It has no modem, no watchdog timer, no ADC. Certain versions support watchdog timer
and ADC. Siemens SAB 80535-N supports ADC with programmable reference voltage.
Advanced versions support these features and choice of version depends on system requirement.
Instruction Set
Figure 2.2 shows instruction types in the 8051 set. There are seven types of instructions.
Full instruction set and instructions in detail can be referred to from a microcontroller text or
manual. The important instructions are as follows:
Data Transfer Instructions Data transfer instructions move (copy) one source operand to
another destination. MOV A, R, and MOV R, A are for moving (copying) the data into A from
R, and to R. R, is the nth register in a set of 8 registers. PSW bits RSO and RS1 predefine the set.
Data transfer instructions MOV A, @R, and MOV @R, A are for moving (copying) the data into
A from @R, and to @R. R, is the i th register in a set of 8 registers. PSW bits RS0 and RS1
predefine the set. @R, means data transfer to an 8-bit address pointed by the contents of the i th
register in the set.
Four data transfer instructions are MOV direct, #data, MOV A, #data, MOV R, #data and MOV
@R, #data for moving 8-bit data into direct or A or R, or @R, Direct means data transfer to an 8-
bit address of internal 128B RAM or SFR address. @R, means data transfer to an 8-bit address
pointed by the contents of the ith register in the set (i = 0 or i).
Seven data transfer instructions are MOV direct, direct, MOV A, direct, MOV direct, A, MOV
direct, R, MOV R, direct, MOV direct, @R1, and MOV @R,, direct are for moving data between
the 8-bit direct address to direct or A or R, or @R. Direct means data transfer to or from an 8- bit
address of internal 128B RAM or SFR address. @R, means data transfer to an 8-bit address
pointed by contents of ith register in the set (i = 0 or 1).
There is a 16-bit external memory data pointer, DPTR. The MOV DPTR, data16 instruction is
used to send 16 bits specified in data16 to DPTR.
MOVX (move external instruction) will transfer the data to or from external data memory. These
instructions are MOVX A, @DPTR and MOVX @DPTR, A. @DPTR means address as pointed
by 16 bits of DPTR. For an 8-bit external memory address, instead of DPTR, @R, is used (i = 0
or 1). MOVC (move code from external program memory instruction) will transfer the data from
the external program memory. Instructions are MOVC A, @A + DPTR and MOVC A, @A +
PC.
For stack operations, there are PUSH direct and POP direct instructions.
Bit Manipulation Instructions Each bit of certain SFRS and an 8-byte internal RAM are
assigned bit addresses in 8051 hardware. There are bit manipulation instructions to clear, set,
AND, OR, MOV the bit.
Byte Manipulation Instructions There are byte manipulation instructions to rotate right A,
rotate left A, rotate right A with carry, rotate left A with carry, complement A, clear A and swap
with A lower and upper nibble (set of 4 bits).
Arithmetic Instructions Arithmetic instructions of the source operand is stored in the
accumulator and the result of the operation is also stored in the accumulator. For example, ADD
A, R. It adds the byte in A with the byte in the nth register. (A + A + R). Three arithmetic
instructions are ADD, ADDC (add including carry bit) and SBBB (subtract including borrow
bit). Carry bit is set to 1 when an operation results in carry or borrow. Borrow is saved in the
carry bit. The second operand can be R n, direct, @Ri, or #data (i = 0 or 1). The meaning of these
is the same as in case of data transferred instructions (explained earlier). There is also an
instruction to adjust hexadecimal addition to decimal addition.
INC and DEC instructions increase (by 1) and decrease (by 1) the bits at the source. The source
can be Rn, direct, @Ri, or A.
MUL AB and DIV AB are used to find A-B← A x B and A-B← A+ B. The multiplication
results in lower byte in A and higher in B. Division results quotient is stored in A and the
remainder in B.
Logic Instructions Logic instructions one of the source operand is accumulator or direct and
result of operation is also in the accumulator or direct. For example, ANL A, Rn, and ANL
direct, Rn. It logical ANDs the byte in A or direct with the byte in nth register in the register set.
(A←A. Rn). Three logic instructions are ANL (AND logic), ORL (OR logic) and XRL (XOR
logic). The second source operand is @Ri, or Rn, or direct when the first source cum destination
is A, and is A and #data when the first source cum destination is direct.