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Experiment # 04 Page 1 of 10
FPGA BASED EMBEDDED SYSTEM DESIGN
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DEPARTMENT OF AVIONICS ENGINEERING
SUBJECT : FPGA BASED EMBEDDED
SYSTEM DESIGN
SUBJECT CODE : 408448
LAB NO : 4
4
TITLE : Testbench to Verify the
Functionality of a Design (Full
Adder and Subtractor)
SUBMITTED TO : Engr. Lal Said Khan
SEMESTER : 6
SECTION : 8B
Marks Obtain
Group Member 1 Group Member 2
NAME Syed Fasih
REGISTRATION
220701054
NUMBER
LAB REPORT
PERFORMANCE
TOTAL MARKS
DEADLINE FOR
SUBMISSION:
DATE OF SUBMISSION:
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FPGA BASED EMBEDDED SYSTEM DESIGN
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Objectives:
• The primary objective of this lab is to designing a 4-Bit Ripple Carry Full Adder
through instantiating individual 1-Bit Full Adders within the 4-Bit module.
• The students will gain a deep understanding of how to structure and interconnect
modules using instantiation techniques.
Introduction:
In Verilog, Instantiation is a fundamental concept in digital design that involves the creation
and utilization of modular components within larger circuits. It enables the encapsulation
and reuse of specific functionalities by allowing designers to define modules, which
represent individual building blocks of a digital system. When a module is instantiated, an
instance of that module is created within another module or at the top level of a design. The
instantiation process involves specifying the connections between the instantiated module
and other signals or ports in the surrounding module.
4-bit Carry Ripple Adder
A N-bit full adder can be designed by cascading N number of 1-bit full adders. Each full
adder takes a carry-in Cin, which is the carry-out Cout of the previous adder. This kind of
chain of adders forms a ripple-carry adder, since each carry-bit "ripples" to the next full
adder. The layout of a ripple-carry adder is simple, which allows for fast design time;
however, the ripple-carry adder is relatively slow, since each full adder must wait for the
carry-bit to be calculated from the previous full adder. A 4-bit ripple carry adder formed
by cascading four 1-bit full adders is shown in Figure 1.
Figure4.1. 4-bit Carry Ripple Adder formed by cascading four full adders
Verilog Module
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Figure 2 shows the Verilog module of a 4-bit carry ripple adder. A and B are the two 4-bit
input ports which is used to read in the two 4-bit numbers that are to be summed up. The
1-bit carry-in input port Cin is used to read in a carry bit, if another instance of the ripple
carry adder is cascaded towards lesser significant stage. The 4-bit sum generated by the
adder is presented in the 4-bit output port Sum and 1-bit carry-out in the Cout output port.
The carry out, Cout provides a carry-bit, if another instance of the ripple carry adder is
cascaded towards more significant stage.
LAB TASK 1:
4-bit Carry Ripple Adder:
Figure 4.2 Verilog module of a 4-bit Ripple Carry Adder
Verilog Code for 4-bit Carry Ripple Adder:
Test Bench:
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Time diagram:
Fig 4.1 Test Case 1
Fig 4.2 Test Case 2
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Explanation:
• The 4-bit Ripple Carry Adder uses four 1-bit full adders connected in series.
• Each full adder adds 1 bit of A, 1 bit of B, and carry-in, producing sum and carry-out.
• The carry-out of each adder is passed to the next adder’s carry-in, creating a ripple
effect.
• The testbench applies different inputs, checks if Sum and Carry-out are correct, and
displays the results.
LAB TASK 2:
Design 4×1 multiplier by instantiating 2×1 multiplier
Verilog Code:
Diagram
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FPGA BASED EMBEDDED SYSTEM DESIGN
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Test Bench:
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Time diagram:
Fig 4.3 Test Case 1
Fig 4.4 Test Case 2
Fig 4.5 Test Case 3
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Explanation:
• Hierarchical Design: The 4×1 multiplexer is built using smaller, reusable 2×1
multiplexers, demonstrating modular and scalable digital design principles.
• First-Level Multiplexing: Two 2×1 MUXes select between inputs I0/I1 and I2/I3
based on the least significant select line S0, producing intermediate outputs Y0 and Y1.
• Second-Level Multiplexing: A third 2×1 MUX selects between Y0 and Y1 based on the
most significant select line S1 to generate the final output Y.
• Simple Logic Implementation: The use of ternary operator in the mux2x1 module
(assign Y = (Sel) ? B : A;) simplifies the selection logic, ensuring clear and
efficient code.
Conclusion:
In conclusion, both the 4-bit Carry Ripple Adder and 4×1 Multiplexer were successfully
designed and tested. The Carry Ripple Adder demonstrated correct binary addition with carry
propagation, while the Multiplexer efficiently selected the desired input based on select lines.
These tasks reinforced the practical understanding of basic combinational circuits and their
importance in digital system.
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