AMC0311S, AMC0211S

SBASB13 – DECEMBER 2024

AMC0x11S Precision, 2.25V Input,

Basic and Reinforced Isolated Amplifiers with Fixed-Gain and Single-Ended Output
1 Features 3 Description
• Linear input voltage range: 0 to 2.25V The AMC0x11S is a precision, galvanically isolated
• High input impedance: 1GΩ (typical) amplifier with a 2.25V, high impedance input, fixed-
• Supply voltage range: gain, and single-ended output. The high-impedance
– High-side (VDD1): 3.0V to 5.5V input is optimized for connection to a high-impedance
– Low-side (VDD2): 3.0V to 5.5V resistive divider or other voltage signal source with
• Fixed gain: 1V/V high output resistance.
• Single-ended output The isolation barrier separates parts of the system
• Low DC errors: that operate on different common-mode voltage
– Offset error: ±1mV (maximum) levels. The isolation barrier is highly resistant to
– Offset drift: ±25µV/°C (maximum) magnetic interference. This barrier is certified to
– Gain error: ±0.25% (maximum) provide reinforced isolation up to 5kVRMS (DWV
– Gain drift: ±40ppm/°C (maximum) package) and basic isolation up to 3kVRMS (D
– Nonlinearity: ±0.02% (maximum) package) (60s).
• High CMTI: 50V/ns (minimum)
• Low EMI: Meets CISPR-11 and CISPR-25 The AMC0x11S outputs a single-ended signal
standards proportional to the input voltage with a fixed gain of
• Isolation ratings: 1V/V. The output is designed to connect directly to the
– AMC0211S: Basic isolation input of an ADC. The voltage applied to the REFIN pin
– AMC0311S: Reinforced Isolation sets the output voltage at 0V input.
• Safety-related certifications: The AMC0x11S devices come in 8-pin, wide- and
– DIN EN IEC 60747-17 (VDE 0884-17) narrow-body SOIC packages, and are fully specified
– UL1577 over the temperature range from –40°C to +105°C.
• Fully specified over the industrial temperature
Package Information
range: –40°C to +105°C
PART NUMBER PACKAGE(1) PACKAGE SIZE(2)
2 Applications AMC0211S (3) D (SOIC 8) 4.9mm × 6.0mm
• Motor drives AMC0311S DWV (SOIC 8) 5.85mm × 11.5mm
• Photovoltaic inverters
• Server Power Supply Units (PSU) (1) For more information, see the Mechanical, Packaging, and
• EV charging stations Orderable Information addendum.
(2) The package size (length × width) is a nominal value and
includes pins, where applicable.
(3) PRODUCT PREVIEW

VDC
High-side supply Low-side supply
(3.3 V or 5 V) (3.3 V or 5 V)
R1
VDD1 VDD2

R2
2.25V 2.25V
0V INP OUT 0V
Galvanic Isolation

ADC

SNSN REFIN
RSNS

GND1 GND2

Typical Application

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
AMC0311S, AMC0211S
SBASB13 – DECEMBER 2024 [Link]

Table of Contents
1 Features............................................................................1 6.17 Typical Characteristics............................................ 17
2 Applications..................................................................... 1 7 Detailed Description......................................................19
3 Description.......................................................................1 7.1 Overview................................................................... 19
4 Device Comparison Table...............................................3 7.2 Functional Block Diagram......................................... 19
5 Pin Configuration and Functions...................................4 7.3 Feature Description...................................................20
6 Specifications.................................................................. 5 7.4 Reference Input........................................................ 21
6.1 Absolute Maximum Ratings ....................................... 5 7.5 Device Functional Modes..........................................22
6.2 ESD Ratings............................................................... 5 8 Application and Implementation.................................. 23
6.3 Recommended Operating Conditions ........................5 8.1 Application Information............................................. 23
6.4 Thermal Information (D Package)...............................6 8.2 Typical Application.................................................... 23
6.5 Thermal Information (DWV Package)......................... 7 8.3 Best Design Practices...............................................26
6.6 Power Ratings ............................................................7 8.4 Power Supply Recommendations.............................27
6.7 Insulation Specifications (Basic Isolation)...................8 8.5 Layout....................................................................... 27
6.8 Insulation Specifications (Reinforced Isolation).......... 9 9 Device and Documentation Support............................28
6.9 Safety-Related Certifications (Basic Isolation)..........10 9.1 Documentation Support............................................ 28
6.10 Safety-Related Certifications (Reinforced 9.2 Receiving Notification of Documentation Updates....28
Isolation)...................................................................... 11 9.3 Support Resources................................................... 28
6.11 Safety Limiting Values (D Package)........................ 12 9.4 Trademarks............................................................... 28
6.12 Safety Limiting Values (DWV Package)..................13 9.5 Electrostatic Discharge Caution................................28
6.13 Electrical Characteristics ........................................14 9.6 Glossary....................................................................28
6.14 Switching Characteristics .......................................15 10 Revision History.......................................................... 28
6.15 Timing Diagram.......................................................15 11 Mechanical, Packaging, and Orderable
6.16 Insulation Characteristics Curves........................... 16 Information.................................................................... 28

2 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: AMC0311S AMC0211S

 AMC0311S, AMC0211S
[Link] SBASB13 – DECEMBER 2024

4 Device Comparison Table

PARAMETER AMC0211S (1) AMC0311S
Isolation rating per VDE 0884-17 Basic Reinforced
Package Narrow-body SOIC (D) Wide-body SOIC (DWV)

(1) PRODUCT PREVIEW

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3

Product Folder Links: AMC0311S AMC0211S
AMC0311S, AMC0211S
SBASB13 – DECEMBER 2024 [Link]

5 Pin Configuration and Functions

VDD1 1 8 VDD2

INP 2 7 OUT

SNSN 3 6 REFIN

GND1 4 5 GND2

Not to scale

Figure 5-1. DWV and D Package, 8-pin SOIC (Top View)

Table 5-1. Pin Functions

PIN
TYPE DESCRIPTION
NO. NAME

1 VDD1 High-side power High-side power supply(1)

2 INP Analog input Analog input

GND1 sense pin and inverting analog input to the modulator. Connect to
3 SNSN Analog input
GND1.

4 GND1 High-side ground High-side analog ground

5 GND2 Low-side ground Low-side analog ground

The voltage applied to this pin is added as an offset to the output voltage of
6 REFIN Analog input the device. Internally, a 90kΩ resistor is connected from REFIN to GND2.
Connect to GND2 if not used.

7 OUT Analog output Analog output

8 VDD2 Low-side power Low-side power supply(1)

(1) See the Power Supply Recommendations section for power-supply decoupling recommendations.

4 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: AMC0311S AMC0211S

 AMC0311S, AMC0211S
[Link] SBASB13 – DECEMBER 2024

6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
High-side VDD1 to GND1 –0.3 6.5
Power-supply voltage V
Low-side VDD2 to GND2 –0.3 6.5
Analog input voltage INP, SNSN to GND1 GND1 – 3 VDD1 + 0.5 V
Reference input voltage REFIN to GND2 GND2 – 0.5 VDD2 + 0.5 V
Input current Continuous, any pin except power-supply pins –10 10 mA
Junction, TJ 150
Temperature °C
Storage, Tstg –65 150

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

6.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per per ANSI/ESDA/JEDEC JS-002(2) ±1000

(1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)
MIN NOM MAX UNIT
POWER SUPPLY
VDD1 High-side power supply VDD1 to GND1 3 5.0 5.5 V
VDD2 Low-side power supply VDD2 to GND2 3 3.3 5.5 V
ANALOG INPUT
VClipping Nominal input voltage before clipping output VIN = VINP – VSNSN 0 2.56 V
VFSR Specified linear input voltage VIN = VINP – VSNSN 0(1) 2.25 V
VREFIN Reference input voltage REFIN to GND2 0 VDD2 V
ANALOG OUTPUT
CLOAD Capacitive load OUT to GND2 500 pF
RLOAD Resistive load OUT to GND2 10 1 kΩ
TEMPERATURE RANGE
TA Specified ambient temperature Specified ambient temperature –40 105 °C

(1) See the Analog Output section for details.

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 5

Product Folder Links: AMC0311S AMC0211S
AMC0311S, AMC0211S
SBASB13 – DECEMBER 2024 [Link]

6.4 Thermal Information (D Package)

D (SOIC)
THERMAL METRIC(1) UNIT
8 PINS
RθJA Junction-to-ambient thermal resistance 116.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 52.8 °C/W
RθJB Junction-to-board thermal resistance 58.9 °C/W
ΨJT Junction-to-top characterization parameter 19.4 °C/W
ΨJB Junction-to-board characterization parameter 58.0 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
note.

6 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: AMC0311S AMC0211S

 AMC0311S, AMC0211S
[Link] SBASB13 – DECEMBER 2024

6.5 Thermal Information (DWV Package)

DWV (SOIC)
THERMAL METRIC(1) UNIT
8 PINS
RθJA Junction-to-ambient thermal resistance 102.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 45.1 °C/W
RθJB Junction-to-board thermal resistance 63.0 °C/W
ΨJT Junction-to-top characterization parameter 14.3 °C/W
ΨJB Junction-to-board characterization parameter 61.1 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
note.

6.6 Power Ratings

PARAMETER TEST CONDITIONS VALUE UNIT
PD Maximum power dissipation (both sides) VDD1 = VDD2 = 5.5V 72 mW
PD1 Maximum power dissipation (high-side) VDD1 = 5.5V 33 mW
PD2 Maximum power dissipation (low-side) VDD2 = 5.5V 39 mW

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 7

Product Folder Links: AMC0311S AMC0211S
AMC0311S, AMC0211S
SBASB13 – DECEMBER 2024 [Link]

6.7 Insulation Specifications (Basic Isolation)

over operating ambient temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VALUE UNIT
GENERAL
CLR External clearance(1) Shortest pin-to-pin distance through air ≥4 mm
CPG External creepage(1) Shortest pin-to-pin distance across the package surface ≥4 mm
DTI Distance through insulation Minimum internal gap (internal clearance) of the insulation ≥ 15.4 µm
CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 ≥ 600 V
Material group According to IEC 60664-1 I

Overvoltage category Rated mains voltage ≤ 300VRMS I-IV

per IEC 60664-1 Rated mains voltage ≤ 600VRMS I-III
DIN EN IEC 60747-17 (VDE 0884-17)(2)
Maximum repetitive peak
VIORM At AC voltage 1130 VPK
isolation voltage

Maximum-rated isolation At AC voltage (sine wave) 800 VRMS

VIOWM
working voltage At DC voltage 1130 VDC
Maximum transient VTEST = VIOTM, t = 60s (qualification test),
VIOTM 4250 VPK
isolation voltage VTEST = 1.2 × VIOTM, t = 1s (100% production test)
VIMP Maximum impulse voltage(3) Tested in air, 1.2/50µs waveform per IEC 62368-1 5000 VPK
Maximum surge Tested in oil (qualification test),
VIOSM 10000 VPK
isolation voltage(4) 1.2/50-µs waveform per IEC 62368-1
Method a, after input/output safety test subgroups 2 and 3,
≤5
Vpd(ini) = VIOTM, tini = 60s, Vpd(m) = 1.2 × VIORM, tm = 10s
Method a, after environmental tests subgroup 1,
≤5
Vpd(ini) = VIOTM, tini = 60s, Vpd(m) = 1.3 × VIORM, tm = 10s
qpd Apparent charge(5) pC
Method b1, at preconditioning (type test) and routine test,
≤5
Vpd(ini) = VIOTM, tini = 1s, Vpd(m) = 1.5 × VIORM, tm = 1s
Method b2, at routine test (100% production)(7),
≤5
Vpd(ini) = VIOTM = Vpd(m), tini = tm = 1s
Barrier capacitance,
CIO VIO = 0.5VPP at 1MHz ≅1.5 pF
input to output(6)
VIO = 500V at TA = 25°C > 1012
Insulation resistance,
RIO VIO = 500V at 100°C ≤ TA ≤ 125°C > 1011 Ω
input to output(6)
VIO = 500V at TS = 150°C > 109
Pollution degree 2
Climatic category 55/125/21
UL1577
VTEST = VISO, t = 60s (qualification test),
VISO Withstand isolation voltage 3000 VRMS
VTEST = 1.2 × VISO, t = 1s (100% production test)

(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Maintain the
creepage and clearance distance of a board design to make sure that the mounting pads of the isolator on the printed circuit board
(PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques such as inserting
grooves, ribs, or both on a PCB are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured
by means of suitable protective circuits.
(3) Testing is carried out in air to determine the surge immunity of the package.
(4) Testing is carried out in oil to determine the intrinsic surge immunity of the isolation barrier.
(5) Apparent charge is electrical discharge caused by a partial discharge (pd).
(6) All pins on each side of the barrier are tied together, creating a two-pin device.
(7) Either method b1 or b2 is used in production.

8 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: AMC0311S AMC0211S

 AMC0311S, AMC0211S
[Link] SBASB13 – DECEMBER 2024

6.8 Insulation Specifications (Reinforced Isolation)

over operating ambient temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VALUE UNIT
GENERAL
CLR External clearance(1) Shortest pin-to-pin distance through air ≥ 8.5 mm
CPG External creepage(1) Shortest pin-to-pin distance across the package surface ≥ 8.5 mm
Minimum internal gap (internal clearance) of the double
DTI Distance through insulation ≥ 15.4 µm
insulation
CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 ≥ 600 V
Material group According to IEC 60664-1 I

Overvoltage category Rated mains voltage ≤ 300VRMS I-IV

per IEC 60664-1 Rated mains voltage ≤ 6000VRMS I-III
DIN EN IEC 60747-17 (VDE 0884-17)(2)
Maximum repetitive peak
VIORM At AC voltage 2120 VPK
isolation voltage

Maximum-rated isolation At AC voltage (sine wave) 1500 VRMS

VIOWM
working voltage At DC voltage 2120 VDC
Maximum transient VTEST = VIOTM, t = 60s (qualification test),
VIOTM 7000 VPK
isolation voltage VTEST = 1.2 × VIOTM, t = 1s (100% production test)
VIMP Maximum impulse voltage(3) Tested in air, 1.2/50µs waveform per IEC 62368-1 7700 VPK
Maximum surge Tested in oil (qualification test),
VIOSM 10000 VPK
isolation voltage(4) 1.2/50µs waveform per IEC 62368-1
Method a, after input/output safety test subgroups 2 and 3,
≤5
Vpd(ini) = VIOTM, tini = 60s, Vpd(m) = 1.2 × VIORM, tm = 10s
Method a, after environmental tests subgroup 1,
≤5
Vpd(ini) = VIOTM, tini = 60s, Vpd(m) = 1.6 × VIORM, tm = 10s
qpd Apparent charge(5) pC
Method b1, at preconditioning (type test) and routine test,
≤5
Vpd(ini) = 1.2 x VIOTM, tini = 1s, Vpd(m) = 1.875 × VIORM, tm = 1s
Method b2, at routine test (100% production)(7)
≤5
Vpd(ini) = Vpd(m) = 1.2 × VIOTM, tini = tm = 1s
Barrier capacitance,
CIO VIO = 0.5VPP at 1MHz ≅1.5 pF
input to output(6)
VIO = 500V at TA = 25°C > 1012
Insulation resistance,
RIO VIO = 500V at 100°C ≤ TA ≤ 125°C > 1011 Ω
input to output(6)
VIO = 500V at TS = 150°C > 109
Pollution degree 2
Climatic category 55/125/21
UL1577
VTEST = VISO, t = 60s (qualification test),
VISO Withstand isolation voltage 5000 VRMS
VTEST = 1.2 × VISO, t = 1s (100% production test)

(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Maintain the
creepage and clearance distance of a board design to make sure that the mounting pads of the isolator on the printed circuit board
(PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques such as inserting
grooves, ribs, or both on a PCB are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured
by means of suitable protective circuits.
(3) Testing is carried out in air to determine the surge immunity of the package.
(4) Testing is carried in oil to determine the intrinsic surge immunity of the isolation barrier.
(5) Apparent charge is electrical discharge caused by a partial discharge (pd).
(6) All pins on each side of the barrier are tied together, creating a two-pin device.
(7) Either method b1 or b2 is used in production.

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 9

Product Folder Links: AMC0311S AMC0211S
AMC0311S, AMC0211S
SBASB13 – DECEMBER 2024 [Link]

6.9 Safety-Related Certifications (Basic Isolation)

VDE UL
DIN EN IEC 60747-17 (VDE 0884-17),
EN IEC 60747-17, Recognized under 1577 component recognition and
DIN EN 61010-1 (VDE 0411-1) Clause : 6.4.3 ; [Link] ; [Link] ; CSA component acceptance NO 5 programs
[Link] ; [Link].2 ; [Link]
Basic insulation Single protection
Certificate number: Pending File number: Pending

10 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: AMC0311S AMC0211S

 AMC0311S, AMC0211S
[Link] SBASB13 – DECEMBER 2024

6.10 Safety-Related Certifications (Reinforced Isolation)

VDE UL
DIN EN IEC 60747-17 (VDE 0884-17),
EN IEC 60747-17,
Recognized under 1577 component recognition and
DIN EN IEC 62368-1 (VDE 0868-1),
CSA component acceptance NO 5 programs
EN IEC 62368-1,
IEC 62368-1 Clause : 5.4.3 ; [Link] ; 5.4.9
Reinforced insulation Single protection
Certificate number: Pending File number: Pending

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 11

Product Folder Links: AMC0311S AMC0211S
AMC0311S, AMC0211S
SBASB13 – DECEMBER 2024 [Link]

6.11 Safety Limiting Values (D Package)

Safety limiting(1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A
failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to
over-heat the die and damage the isolation barrier potentially leading to secondary system failures.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RθJA = 116.5°C/W, VDDx = 5.5V,
IS Safety input, output, or supply current 195 mA
TJ = 150°C, TA = 25°C
PS Safety input, output, or total power RθJA = 116.5°C/W, TJ = 150°C, TA = 25°C 1070 mW
TS Maximum safety temperature 150 °C

(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power, respectively. Do not exceed the maximum limits of IS and PS. These
limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the Thermal Information table is that of a device installed on a high-K test board for
leaded surface-mount packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum junction temperature.
PS = IS × VDDmax, where VDDmax is the maximum supply voltage for high-side and low-side.

12 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: AMC0311S AMC0211S

 AMC0311S, AMC0211S
[Link] SBASB13 – DECEMBER 2024

6.12 Safety Limiting Values (DWV Package)

Safety limiting(1) intends to minimize potential damage to the isolation barrier upon failure of input or output circuitry. A
failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to
over-heat the die and damage the isolation barrier potentially leading to secondary system failures.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RθJA = 102.8°C/W, VDDx = 5.5V,
IS Safety input, output, or supply current 220 mA
TJ = 150°C, TA = 25°C
PS Safety input, output, or total power RθJA = 102.8°C/W, TJ = 150°C, TA = 25°C 1210 mW
TS Maximum safety temperature 150 °C

(1) The maximum safety temperature, TS, has the same value as the maximum junction temperature, TJ, specified for the device. The IS
and PS parameters represent the safety current and safety power, respectively. Do not exceed the maximum limits of IS and PS. These
limits vary with the ambient temperature, TA.
The junction-to-air thermal resistance, RθJA, in the Thermal Information table is that of a device installed on a high-K test board for
leaded surface-mount packages. Use these equations to calculate the value for each parameter:
TJ = TA + RθJA × P, where P is the power dissipated in the device.
TJ(max) = TS = TA + RθJA × PS, where TJ(max) is the maximum junction temperature.
PS = IS × VDDmax, where VDDmax is the maximum supply voltage for high-side and low-side.

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 13

Product Folder Links: AMC0311S AMC0211S
AMC0311S, AMC0211S
SBASB13 – DECEMBER 2024 [Link]

6.13 Electrical Characteristics

minimum and maximum specification0s apply from TA = –40°C to +105°C, VDD1 = 3.0V to 5.5V, VDD2 = 3.0V to 5.5V,
REFIN = GND2, SNSN = GND1, VINP = 0.25V to 2.25V (unless otherwise noted); typical specifications are at TA = 25°C,
VDD1 = 5V, and VDD2 = 3.3V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
CIN Input capacitance 2 pF
RINP Input impedance INP pin to GND1 0.1 1 GΩ
IIB, INP Input bias current(1) INP pin, INP = GND1 –10 ±3 10 nA
CMTI Common-mode transient immunity 50 V/ns
ANALOG OUTPUT
Nominal gain 1 V/V
ROUT Output resistance OUTP or OUTN <0.2 Ω
sourcing or sinking,
Output short-circuit current INP = GND1, output shorted to 11 mA
either GND2 or VDD2
DC ACCURACY
VOS = (VOUT – VREFIN),
VOS Input offset voltage(1) (2) INP = SNSN = GND1, –1 ±0.2 1 mV
VREFIN = 250mV, TA = 25°C
TCVOS Input offset thermal drift(1) (2) (4) –25 ±4 25 µV/°C
EG Gain error(1) TA = 25℃ –0.25% ±0.05% 0.25%
TCEG Gain error drift(1) (5) –40 ±5 40 ppm/°C
Nonlinearity –0.02% ±0.002% 0.02%
Output noise INP = GND1, BW = 50kHz 220 µVrms
VDD1 DC PSRR, VINP = 250mV,
–80
VDD1 from 3V to 5.5V
VDD1 AC PSRR, VINP = 250mV,
–56
VDD1 with 10kHz / 100mV ripple
PSRR Power-supply rejection ratio(2) dB
VDD2 DC PSRR, VINP = 250mV,
–90
VDD2 from 3V to 5.5V
VDD2 AC PSRR, VINP = 250mV,
–69
VDD2 with 10kHz / 100mV ripple
AC ACCURACY
BW Output bandwidth 100 125 kHz
VINP = 2VPP, VINP > 0V,
THD Total harmonic distortion(3) –77 dB
fIN = 10kHz
VINP = 2.25VPP, fINP = 1kHz, BW = 10kHz 76 80
SNR Signal-to-noise ratio VINP = 2.25VPP, fINP = 10kHz, BW = dB
70
50kHz
POWER SUPPLY
IDD1 High-side supply current 4.4 6.0 mA
IDD2 Low-side supply current 4.8 7.0 mA

High-side undervoltage detection VDD1 rising 2.4 2.6 2.7

VDD1UV V
threshold VDD1 falling 1.9 2.0 2.1

Low-side undervoltage detection VDD2 rising 2.4 2.6 2.7

VDD2UV V
threshold VDD2 falling 1.9 2.0 2.1

(1) The typical value includes one standard deviation (sigma) at nominal operating conditions.
(2) This parameter is input referred.
(3) THD is the ratio of the rms sum of the amplitudes of first five higher harmonics to the amplitude of the fundamental.
(4) Offset error temperature drift is calculated using the box method, as described by the following equation:
TCVOS = (ValueMAX - ValueMIN) / TempRange

14 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: AMC0311S AMC0211S

 AMC0311S, AMC0211S
[Link] SBASB13 – DECEMBER 2024

(5) Gain error temperature drift is calculated using the box method, as described by the following equation:
TCEG (ppm) = (ValueMAX - ValueMIN) / (Value(T=25℃) x TempRange) x 106

6.14 Switching Characteristics

over operating ambient temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tr Output signal rise time 10% to 90%, unfiltered output 2.6 µs
tf Output signal fall time 10% to 90%, unfiltered output 2.6 µs
VINP to VOUT signal delay (50% - 10%) Unfiltered output 2.4 µs
VINP to VOUT signal delay (50% - 50%) Unfiltered output 3.0 3.2 µs
VINP to VOUT signal delay (50% - 90%) Unfiltered output 4.2 µs
AVDD step to 3.0V with DVDD ≥ 3.0V to
tAS Analog settling time 20 µs
VOUT valid, 0.1% settling

6.15 Timing Diagram

VFSR

INP

0V

tr tf

OUT

0V

50% - 10%

50% - 50%

50% - 90%

Figure 6-1. Rise, Fall, and Delay Time Definition

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 15

Product Folder Links: AMC0311S AMC0211S
AMC0311S, AMC0211S
SBASB13 – DECEMBER 2024 [Link]

6.16 Insulation Characteristics Curves

240 1400
AMC0311 AMC0311
AMC0211 1200 AMC0211
200

1000
160
800

PS( mW)
IS(mA)

120
600

80
400

40 200

0 0
0 25 50 75 100 125 150 0 25 50 75 100 125 150
TA( °C) TA( °C) G070
G069

Figure 6-2. Thermal Derating Curve for Safety- Figure 6-3. Thermal Derating Curve for Safety-
Limiting Current per VDE Limiting Power per VDE
1E+12
1E+11
1E+10 50%

1E+09
1E+08
Time to Fail (s)

20%
1E+07 TDDB Line
1E+06 (<1PPM Fail Rate)

1E+05 Operating Zone

1E+04
1E+03
VDE Safety Margin Zone
1E+02
1E+01

1000 1500 2000 2500 3000 3500 4000

Applied Voltage (VRMS) G077

TA up to 150°C, stress-voltage frequency = 60Hz, isolation working voltage = 1500VRMS, projected operating lifetime ≥50 years

Figure 6-4. Isolation Capacitor Lifetime Projection

16 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: AMC0311S AMC0211S

 AMC0311S, AMC0211S
[Link] SBASB13 – DECEMBER 2024

6.17 Typical Characteristics

at VDD1 = 5 V, VDD2 = 3.3 V, SNSN = GND1, REFIN = GND2, fIN = 10 kHz, and BW = 100 kHz (unless otherwise noted)

1 1

0.75 0.75

0.5 0.5

0.25 0.25

VOS(mV)
VOS(mV)

0 0

-0.25 -0.25

-0.5 -0.5 Device 1

-0.75 vs VDD1 -0.75 Device 2

vs VDD2 Device 3
-1 -1
3 3.5 4 4.5 5 5.5 -40 -25 -10 5 20 35 50 65 80 95 110 125
VDDx (V) G027 Temperature (°C) G026

Figure 6-5. Input Offset Voltage vs Supply Voltage Figure 6-6. Input Offset Voltage vs Temperature

0.25 0.25
Device 1
0.2 0.2
Device 2
0.15 0.15
Device 3
0.1 0.1

0.05 0.05
EG(%)

EG(%)

0 0

-0.05 -0.05

-0.1 -0.1

-0.15 -0.15
vs VDD1
-0.2 -0.2
vs VDD2
-0.25 -0.25
3 3.5 4 4.5 5 5.5 -40 -25 -10 5 20 35 50 65 80 95 110 125
VDDx (V) G020 Temperature (°C) G021

Figure 6-7. Gain Error vs Supply Voltage Figure 6-8. Gain Error vs Temperature
8 5

7 0

6 -5
Noise Density (μV/√Hz)

Normalized Gain (dB)

5 -10

4 -15

3 -20

2 -25

1 -30

0 -35
0.1 1 10 100 1000 10000 1 10 100 1000
Frequency (kHz) G017 fIN(kHz) G007

Figure 6-9. Input-Referred Noise Density vs Frequency Figure 6-10. Normalized Gain vs Input Frequency

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 17

Product Folder Links: AMC0311S AMC0211S
AMC0311S, AMC0211S
SBASB13 – DECEMBER 2024 [Link]

6.17 Typical Characteristics (continued)

at VDD1 = 5 V, VDD2 = 3.3 V, SNSN = GND1, REFIN = GND2, fIN = 10 kHz, and BW = 100 kHz (unless otherwise noted)

50 7

0
6
-50
5
-100
Output Phase (°)

-150 4

IDDx(mA)
-200
3
-250
2
-300

-350 1 IDD1
-400 IDD2
1 10 100 1000 0
fIN(kHz) G008 3 3.5 4 4.5 5 5.5
VDDx (V) G043

Figure 6-11. Output Phase vs Input Frequency

Figure 6-12. Supply Current vs Supply Voltage
7

4
IDDx(mA)

1 IDD1
IDD2
0
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temperature (°C) G044

Figure 6-13. Supply Current vs Temperature

18 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: AMC0311S AMC0211S

 AMC0311S, AMC0211S
[Link] SBASB13 – DECEMBER 2024

7 Detailed Description
7.1 Overview
The AMC0x11S is a precision, galvanically isolated amplifier with a 2.25V, high impedance input, fixed-gain,
and single-ended output. The input stage of the device drives a second-order, delta-sigma (ΔΣ) modulator. The
modulator converts the analog input signal into a digital bitstream that is transferred across the isolation barrier
that separates the high side from the low side.
On the low-side, the received bitstream is processed by an analog filter that outputs a GND2-referenced,
single-ended signal at the OUT pin. This single-ended output signal is proportional to the input signal. The output
voltage at 0V input is set by the voltage applied to the REFIN pin.
The SiO2-based, capacitive isolation barrier supports a high level of magnetic field immunity, as described in the
ISO72x Digital Isolator Magnetic-Field Immunity application note. The digital modulation used in the AMC0x11S
transmits data across the isolation barrier. This modulation, and the isolation barrier characteristics, result in high
reliability and high common-mode transient immunity.
7.2 Functional Block Diagram

VDD1 VDD2

Reference Barrier Analog Filter

INP OUT
DAC

Modulator
RX
TX

SNSN REFIN
Isolation

10 MHz Oscillator 90kΩ

GND1 GND2

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 19

Product Folder Links: AMC0311S AMC0211S
AMC0311S, AMC0211S
SBASB13 – DECEMBER 2024 [Link]

7.3 Feature Description

7.3.1 Analog Input
The high-impedance input buffer on the INP pin feeds a second-order, switched-capacitor, feed-forward ΔΣ
modulator. The modulator converts the analog signal into a bitstream that is transferred across the isolation
barrier, as described in the Isolation Channel Signal Transmission section.
There are two restrictions on the analog input signal. First, if the input voltage exceeds the value specified
in the Absolute Maximum Ratings table, the input current must be limited to 10mA. This limitation is caused
by the device input electrostatic discharge (ESD) diodes turning on. Second, linearity and noise performance
are specified only when the input voltage is within the linear full-scale range (VFSR). VFSR is specified in the
Recommended Operating Conditions table.
7.3.2 Isolation Channel Signal Transmission
The AMC0x11S uses an on-off keying (OOK) modulation scheme, as shown in Figure 7-1, to transmit the
modulator output bitstream across the SiO2-based isolation barrier. The transmit driver (TX) as illustrated in the
Functional Block Diagram transmits an internally generated, high-frequency carrier across the isolation barrier to
represent a digital one. However, TX does not send a signal to represent a digital zero. The nominal frequency of
the carrier used inside the AMC0x11S is 480MHz.
The receiver (RX) on the other side of the isolation barrier recovers and demodulates the signal and provides
the input to the analog filter. The AMC0x11S transmission channel is optimized to achieve the highest level of
common-mode transient immunity (CMTI) and the lowest level of radiated emissions. The high-frequency carrier
and RX/TX buffer switching cause these emissions.

Internal Clock

Modulator Bitstream
on High-side

Signal Across Isolation Barrier

Recovered Sigal
on Low-side

Figure 7-1. OOK-Based Modulation Scheme

20 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: AMC0311S AMC0211S

 AMC0311S, AMC0211S
[Link] SBASB13 – DECEMBER 2024

7.3.3 Analog Output

The AMC0x11S provides a single-ended analog output voltage proportional to the input voltage. The output is
referred to GND2 and is galvanically isolated from the input of the device. The output is designed to connect
directly to the input of an ADC.
The output buffer requires a minimum headroom of 250mV for linear operation. Therefore, with REFIN shorted
to GND2, the device shows non-linear behavior for input voltages near 0V. To extend the linear input range
to 0V, connect a reference voltage to the REFIN pin that is ≥250mV. The voltage applied to the REFIN pin is
added to the output voltage as an offset and provides headroom for the output buffer. The output voltage of the
AMC0x11S is equal to:

VOUT = VIN + VREFIN = (VINP – VSNSN) + VREFIN (1)

Connect the REFIN pin to GND2 if no offset is required. Figure 7-2 shows the input-to-output transfer
characteristic of the device.
Maximum input range before clipping (VClipping) Maximum input range before clipping (VClipping)

Linear input range (VFSR) Linear input range (VFSR)

2.56V + VREFIN

2.56V 2.25V + VREFIN

2.25V

Non-linear range
Non-linear range

Non-linear range

1V/V
VOUT

VOUT

1 V/V

0.25V + VREFIN

0.25V VREFIN

0 0
Input Voltage (VIN) Input Voltage (VIN)
0 0.25V 2.25V 0 0.25V 2.25V
2.56V 2.56V

Figure 7-2. Input to Output Transfer Curve of the AMC0x11S

Left: REFIN shorted to GND2. Right: VREFIN = 250mV

7.4 Reference Input

The voltage applied to the REFIN pin is added to the output voltage as an offset as described in the Analog
Output section. In a typical application, REFIN is either shorted to GND2 or biased at ≥250mV.
The output buffer is linear in the range of 250mV < VOUT < (VDD2 – 250mV). For linear operation, bias the
REFIN pin such that:

VREFIN ≥ 250mV (2)

and

VREFIN + VFSR, MAX ≤ VDD2 – 250mV (3)

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 21

Product Folder Links: AMC0311S AMC0211S
AMC0311S, AMC0211S
SBASB13 – DECEMBER 2024 [Link]

7.5 Device Functional Modes

The AMC0x11S operates in one of the following states:
• OFF-state: The low-side supply (VDD2) is below the VDD2UV threshold. The device is not responsive. OUT is
in Hi-Z state. Internally, OUT is clamped to VDD2 and GND2 by ESD protection diodes.
• Missing high-side supply: The low-side of the device (VDD2) is supplied and within the Recommended
Operating Conditions section. The high-side supply (VDD1) is below the VDD1UV threshold. The OUT pin is
driven to VREFIN (0V if REFIN is shorted to GND2).
• Analog input overrange (positive full-scale input): VDD1 and VDD2 are within recommended operating
conditions but the analog input voltage VIN is above the maximum clipping voltage VClipping, MAX. The device
outputs VClipping + VREFIN at the OUT pin.
• Analog input underrange (negative full-scale input): VDD1 and VDD2 are within recommended operating
conditions but the analog input voltage VIN is below the minimum clipping voltage VClipping, MIN. The OUT pin
is driven to VREFIN (0V if REFIN is shorted to GND2).
• Normal operation: VDD1, VDD2, and VIN are within the recommended operating conditions. The device
outputs a voltage proportional to the input voltage.
Table 7-1 lists the operating modes.
Table 7-1. Device Operational Modes
OPERATING DEVICE
VDD1 VDD2 VIN
CONDITION RESPONSE

OFF Don't care VDD2 < VDD2UV Don't care OUT is in Hi-Z state. Internally, OUT is
clamped to VDD2 and GND2 by ESD
protection diodes.

Missing high-side VDD1 < VDD1UV Valid(1) Don't care The OUT pin is driven to VREFIN (0V if REFIN
supply is shorted to GND2).

Input overrange Valid(1) Valid(1) VIN > VClipping, MAX The device outputs VClipping + VREFIN at the
OUT pin.

Input underrange Valid(1) Valid(1) VIN < VClipping, MIN The OUT pin is driven to VREFIN (0V if REFIN
is shorted to GND2).

Normal operation Valid(1) Valid(1) Valid(1) The device outputs a voltage proportional to
the input voltage.

(1) "Valid" denotes within the recommended operating conditions.

22 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: AMC0311S AMC0211S

 AMC0311S, AMC0211S
[Link] SBASB13 – DECEMBER 2024

8 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

8.1 Application Information

Industrial power systems such as motor drives are divided into two or more voltage domains that are galvanically
isolated from each other. For example, the high-voltage domain includes the AC grid, DC-link, and power stage
for driving the motor. The low-voltage includes the system controller and human interface. The controller must
measure the value of the DC-Link voltage while remaining galvanically isolated from the high-voltage side for
safety reasons. With the high-impedance input and galvanically isolated output, the AMC0x11S enables this
measurement.
8.2 Typical Application
Figure 8-1 illustrates a simplified schematic of an AC inverter for a 3-phase motor drive. The AMC0x11S device
is used for DC-link voltage sensing. In the power domain, the DC-link voltage is divided down to a 2V level
across the bottom resistor (RSNS) of a high-impedance resistive divider. The voltage across RSNS is sensed by
the AMC0x11S. The low-side gate driver supply is regulated to a 5V level to power the high-voltage side of the
AMC0x11S. In the signal domain, on the opposite side of the isolation barrier, the AMC0x11S outputs a voltage
proportional to the DC-link voltage.
DC (+)

R1

RTOP

M
R2
Low-side 3~
gate driver supply

+
RSNS
–
DC (–)

5V
VDD2 supply
(3.3V or 5V)

1µF 1µF

100nF 100nF
VDD1 VDD2

INP OUT to ADC

100pF SNSN REFIN

100nF Reference voltage
GND1 GND2

power domain signal domain

Figure 8-1. Using the AMC0x11S in a Typical Application

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 23

Product Folder Links: AMC0311S AMC0211S
AMC0311S, AMC0211S
SBASB13 – DECEMBER 2024 [Link]

8.2.1 Design Requirements

Table 8-1 lists the parameters for this typical application.
Table 8-1. Design Requirements
PARAMETER VALUE

DC-link voltage 450V (maximum)

High-side supply voltage 5V

Low-side supply voltage 3.3V

Maximum resistor operating voltage 125V

Voltage drop across the sense resistor (RSNS) for a linear response 2.25V (maximum)

Current through the resistive divider, ICROSS 200μA (maximum)

8.2.2 Detailed Design Procedure

The 200μA cross-current requirement at the maximum DC-link voltage (450V) determines that the total
impedance of the resistive divider is 2.25MΩ. The impedance of the resistive divider is dominated by the top
portion (shown exemplary as R1 and R2 in Figure 8-1 ) and the voltage drop across RSNS can be neglected
for a moment. The maximum allowed voltage drop per unit resistor is specified as 125V; therefore, the minimum
number of unit resistors in the top portion of the resistive divider is 450V / 125V ≅ 4. The calculated unit value
is 2.25MΩ / 4 = 563kΩ and the next closest value from the E96 series is 562kΩ. The sense resistor (RSNS) is
sized such that the voltage drop across the resistor at the maximum DC-link voltage (450V) equals the linear
full-scale range input voltage (VFSR) of the AMC0x11S, which is 2.25V. This resistance is calculated as RSNS
= VFSR / (VDC-link, MAX – VFSR) × RTOP, where RTOP is the total value of the top resistor string (4 × 562kΩ =
2.248MΩ). RSNS is calculated as 11.3kΩ and matches a value from the E96 series.
Table 8-2 summarizes the design of the resistive divider.
Table 8-2. Resistor Value Examples
PARAMETER VALUE

Unit resistor value, RTOP 562kΩ

Number of unit resistors in RTOP 4

Sense resistor value, RSNS 11.3kΩ

Total resistance value (RTOP + RSNS) 2.251MΩ

Resulting current through resistive divider, ICROSS 199.2μA

Resulting full-scale voltage drop across sense resistor RSNS 2.251V

Peak power dissipated in RTOP unit resistor 22.3mW

Total peak power dissipated in resistive divider 89.6mW

24 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: AMC0311S AMC0211S

 AMC0311S, AMC0211S
[Link] SBASB13 – DECEMBER 2024

[Link] Input Filter Design

Place a RC filter in front of the device to improve signal-to-noise performance of the signal path. Input noise
with a frequency close to the ΔΣ modulator sampling frequency (typically 10MHz) is folded back into the
low-frequency range by the modulator. The purpose of the RC filter is to attenuate high-frequency noise below
the desired noise level of the measurement. In practice, a cutoff frequency that is two orders of magnitude lower
than the modulator frequency yields good results.
Most voltage-sensing applications use high-impedance resistive dividers in front of the isolated modulator to
scale down the input voltage. In this case, a single capacitor, as shown in Figure 8-2, is sufficient to filter the
input signal. For (R1 + R2) >> RSNS, the cut-off frequency of the input filter is 1 / (2 x π x RSNS x C5). For
example, RSNS =10kΩ and C5 = 100pF results in a cutoff frequency of 160kHz.
VIN

R1

R2 VDD1
C5
INP

RSNS SNSN

GND1

Figure 8-2. Input Filter

[Link] Connecting the REFIN pin

The reference input has an internal, 90kOhm impedance connected to GND2. This impedance needs to be
considered when driving the REFIN pin from a high-impedance source. Connect a 100nF capacitor from
REFIN to GND2 to filter out high-frequency noise at the reference input. Figure 8-3 shows different options
for connecting the REFIN pin.
VDD2 supply
VDD2 VDD2 VDD2
(3.3V or 5V)
OUT OUT R1 OUT Reference voltage
RSOURCE
REFIN REFIN R2 REFIN

+
–
100nF
GND2 GND2 GND2
100nF

90k 90k

Figure 8-3. Connecting the REFIN pin

In the first example, REFIN is shorted to GND2 and the resulting reference voltage is 0V. In the second example,
VREFIN is derived from VDD2 through a resistive divider. In the third example, an external voltage source drives
the reference input pin.

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 25

Product Folder Links: AMC0311S AMC0211S
AMC0311S, AMC0211S
SBASB13 – DECEMBER 2024 [Link]

8.2.3 Application Curve

Figure 8-4 shows the typical full-scale step response of the AMC0x11S.
3
VINP
2.5 VOUT
VREF
2

Magnitude (V)
1.5

0.5

-0.5
135 140 145 150 265 270 275 280 285
Time (µs) G086

Figure 8-4. Step Response of the AMC0x11S

8.3 Best Design Practices

Do not leave the analog input (INP pin) of the AMC0x11S unconnected (floating) when the device is powered up.
If the device input is left floating, the output of the device is not valid.
Do not connect protection diodes to the input (INP pin) of the AMC0x11S. Diode leakage current potentially
introduces significant measurement error especially at high temperatures. The input pin is protected against high
voltages by the ESD protection circuit and the high impedance of the external resistive divider.

26 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: AMC0311S AMC0211S

 AMC0311S, AMC0211S
[Link] SBASB13 – DECEMBER 2024

8.4 Power Supply Recommendations

In a typical application, the high-side power supply (VDD1) for the AMC0x11S is generated from the low-side
supply (VDD2) by an isolated DC/DC converter. A low-cost option is based on the push-pull driver SN6501 and a
transformer that supports the desired isolation voltage ratings.
The AMC0x11S does not require any specific power-up sequencing. The high-side power supply (VDD1) is
decoupled with a low-ESR, 100nF capacitor (C1) parallel to a low-ESR, 1μF capacitor (C2). The low-side power
supply (VDD2) is equally decoupled with a low-ESR, 100nF capacitor (C3) parallel to a low-ESR, 1μF capacitor
(C4). Place all four capacitors (C1, C2, C3, and C4) as close to the device as possible. Figure 8-5 shows a
decoupling diagram for the AMC0x11S.
VIN

VDD1 VDD2
R1
C2 1µF C4 1µF

C1 100nF C3 100nF
R2 VDD1 VDD2

INP OUT to ADC

RSNS C5 100pF SNSN REFIN

C6 100nF Reference voltage
GND1 GND2

Figure 8-5. Decoupling of the AMC0x11S

Capacitors must provide adequate effective capacitance under the applicable DC bias conditions experienced in
the application. Multilayer ceramic capacitors (MLCC) typically exhibit only a fraction of the nominal capacitance
under real-world conditions. Consider this factor when selecting these capacitors. This issue is especially acute
in low-profile capacitors, in which the dielectric field strength is higher than in taller components. Reputable
capacitor manufacturers provide capacitance versus DC bias curves that greatly simplify component selection.
8.5 Layout
8.5.1 Layout Guidelines
The Layout section details a layout recommendation with the critical placement of the decoupling capacitors (as
close as possible to the AMC0x11S supply pins). This example also depicts the placement of other components
required by the device.
8.5.2 Layout Example
Figure 8-6. Recommended Layout of the AMC0x11S
VDD1 VDD2
VIN Clearance area, keep free of
any conductive materials
C2 C4

C1 C3
R1

INP OUT to ADC

RSNS

R2
C5

REFIN from MCU or external reference

C6

GND1 GND2

Top Metal
Inner or Bottom Layer Metal
Via

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 27

Product Folder Links: AMC0311S AMC0211S
AMC0311S, AMC0211S
SBASB13 – DECEMBER 2024 [Link]

9 Device and Documentation Support

9.1 Documentation Support
9.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Isolation Glossary application report
• Texas Instruments, Semiconductor and IC Package Thermal Metrics application report
• Texas Instruments, ISO72x Digital Isolator Magnetic-Field Immunity application report
• Texas Instruments, 18-Bit, 1-MSPS Data Acquisition Block (DAQ) Optimized for Lowest Distortion and Noise
reference guide
• Texas Instruments, 18-Bit, 1-MSPS Data Acquisition Block (DAQ) Optimized for Lowest Power reference
guide
• Texas Instruments, Isolated Amplifier Voltage Sensing Excel Calculator design tool
9.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on [Link]. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
9.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
9.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
9.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

9.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

10 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE REVISION NOTES
December 2024 * Initial Release

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

28 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: AMC0311S AMC0211S

 PACKAGE OPTION ADDENDUM

[Link] 23-May-2025

PACKAGING INFORMATION

Orderable part number Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
(1) (2) (3) Ball material Peak reflow (6)
(4) (5)

AMC0311SDWVR Active Production SOIC (DWV) | 8 1000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 105 AMC0311S
AMC0311SDWVR.A Active Production SOIC (DWV) | 8 1000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 105 AMC0311S
AMC0311SDWVR.B Active Production SOIC (DWV) | 8 1000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 105 AMC0311S

(1)
Status: For more details on status, see our product life cycle.

(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance,
reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional
waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.

(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.

(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum
column width.

(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown.
Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.

(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.

Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two
combined represent the entire part marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and
makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative
and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers
and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF AMC0311S :

• Automotive : AMC0311S-Q1

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

[Link] 23-May-2025

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

[Link] 16-Dec-2024

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
AMC0311SDWVR SOIC DWV 8 1000 330.0 16.4 12.15 6.2 3.05 16.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

[Link] 16-Dec-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
AMC0311SDWVR SOIC DWV 8 1000 353.0 353.0 32.0

Pack Materials-Page 2
 PACKAGE OUTLINE

DWV0008A SCALE 2.000

SOIC - 2.8 mm max height
SOIC

SEATING PLANE
11.5 0.25
PIN 1 ID TYP 0.1 C
AREA
6X 1.27
8
1

5.95 2X
5.75 3.81
NOTE 3

4
5
0.51
8X
0.31
7.6 0.25 C A B
A B 2.8 MAX
7.4
NOTE 4

0.33
TYP
0.13

SEE DETAIL A

(2.286)
0.25
GAGE PLANE

0.46
0.36
0 -8
1.0
0.5 DETAIL A
(2) TYPICAL

4218796/A 09/2013

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.

[Link]
 EXAMPLE BOARD LAYOUT

DWV0008A SOIC - 2.8 mm max height

SOIC

8X (1.8) SEE DETAILS

SYMM

8X (0.6) SYMM

6X (1.27)
(10.9)

LAND PATTERN EXAMPLE

9.1 mm NOMINAL CLEARANCE/CREEPAGE
SCALE:6X

SOLDER MASK SOLDER MASK METAL

METAL
OPENING OPENING

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4218796/A 09/2013

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

[Link]
 EXAMPLE STENCIL DESIGN

DWV0008A SOIC - 2.8 mm max height

SOIC

8X (1.8) SYMM

8X (0.6)
SYMM

6X (1.27)

(10.9)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:6X

4218796/A 09/2013

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

[Link]
 IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on [Link] or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2025, Texas Instruments Incorporated