Analog CMOS IC Lab

Submitted to
Dr. Menka Yadav

Submitted by
Bhuvan Sharma
2023UEC1020
ECE1

Department of Electronics and Communication Engineering

Malaviya National Institute of Technology Jaipur
Jaipur, India, 302017
List of Contents

S.No Contents Signature

1 Analysing the V-I Characteristics of NMOS
2 Analysing the V-I Characteristics of PMOS
3 Analysing the Resistive Load NMOS
4 Analysing the Diode Connected Load NMOS

1
Contents
1 Analysing the V-I Characteristics of NMOS 3

2 Analysing the V-I Characteristics of PMOS 5

3 Analysing the Resistive Load NMOS 7

4 Analysing the Diode Connected Load NMOS 10

2
1 Analysing the V-I Characteristics of NMOS
Aim
In this experiment, my goal was to understand the voltage-current behavior of an NMOS
transistor. I wanted to see how it performs in both the triode and saturation regions,
which is essential for designing robust integrated circuits.

Software Used
I used Cadence software—specifically Virtuoso—to simulate the circuit and capture the
performance details. This tool helped me visualize the device behavior under various
biasing conditions.

Theory
The NMOS transistor can operate in different modes based on the applied voltages. In
the triode region, where the transistor behaves like a resistor, the drain current is given
by:
2 i
Wh VDS
ID = µn Cox (VGS − Vth )VDS −
L 2
In the saturation region, the current levels off and is expressed as:
1 W  
ID = µn Cox (VGS − Vth )2 1 + λVDS
2 L
Here, parameters such as the electron mobility (µn ), oxide capacitance (Cox ), device
dimensions (W and L), threshold voltage (Vth ), and channel-length modulation (λ) play
key roles.

Circuit Diagram

Figure: NMOS Cross Sectional Diagram

3
Experiment Results
I captured the V-I characteristics using Cadence simulations. Here are two graphs that
represent the results:

Graph 1: Id vs Vds

Graph 2: Id vs Vgs

Conclusion and Results

From this experiment, I learned that the NMOS transistor clearly exhibits two distinct
regions of operation. The simulation data aligns well with the theoretical expectations,
and the extracted device parameters were consistent with what I anticipated.

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2 Analysing the V-I Characteristics of PMOS
Aim
This experiment was designed to explore the V-I characteristics of a PMOS transistor. I
wanted to observe how a PMOS device behaves under different bias conditions and how
its performance compares with that of an NMOS transistor.

Software Used
I again used Cadence Virtuoso for simulating the PMOS device. This tool provided
detailed insights into the PMOS operation and helped me capture the necessary mea-
surements.

Theory
The PMOS transistor works in a similar manner to the NMOS but with inverted voltages.
In the triode region, the drain current is:
Wh V2 i
ID = µp Cox (VSG − |Vth |)VSD − SD
L 2
And in the saturation region, the current is:
1 W  
ID = µp Cox (VSG − |Vth |)2 1 + λVSD
2 L
Key parameters here include the hole mobility (µp ) and the source-to-gate voltage (VSG ).

Circuit Diagram

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 Figure: PMOS Cross Sectional View

Experiment Results
I obtained the V-I curves for the PMOS device under varying conditions. The following
graphs summarize the findings:

Graph 1: Id Vs Vds

Graph 2: Id vs Vgs

Conclusion and Results

The PMOS transistor exhibited behavior in line with theoretical predictions, with clear
demarcation between the linear and saturation regions.

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3 Analysing the Resistive Load NMOS
Aim
In this part of the lab, I set out to analyze an NMOS transistor with a resistive load. The
focus was to determine the operating point through load-line analysis and to calculate
the amplifier gain.

Software Used
For this experiment, I relied on Cadence Virtuoso to simulate the circuit. This tool
enabled me to precisely determine the operating point and to perform gain measurements.

Theory
When an NMOS transistor is used with a resistive load, the load line is given by:
VDD − VDS
ID =
R
And in saturation, the NMOS device follows:
1 W
ID = µn Cox (VGS − Vth )2
2 L
The point where the load line intersects the transistor’s characteristic curve determines
the operating point.

Gain Equations
For a common-source amplifier with a resistive load, the voltage gain can be approximated
by:
Av = −gm R
with transconductance defined as:
W
gm = µn Cox (VGS − Vth )
L
This helps in estimating the overall gain of the circuit.

Circuit Diagram
Below is the schematic for the resistive load NMOS circuit.

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 Figure: Resistive Load NMOS Circuit

Experiment Results
I captured several simulation results for this configuration:

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 Graph 1: Transient Analysis

Graph 2: AC Analysis

Conclusion and Results

This experiment confirmed that the load-line method accurately determines the operating
point, and the gain measurements agreed well with the theoretical estimates. I found that
the practical results were very close to the calculated values.

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4 Analysing the Diode Connected Load NMOS
Aim
The purpose of this experiment was to study an NMOS transistor when it is configured
as a diode-connected load. This setup is common in biasing circuits and current mirrors,
and I was particularly interested in its V-I behavior and amplifier gain characteristics.

Software Used
I used Cadence Virtuoso again for this experiment. This tool allowed me to simulate the
diode-connected configuration with high accuracy.

Theory
In a diode-connected NMOS configuration, the gate and drain are tied together, meaning:

VGS = VDS

In the saturation region, the drain current is described by:

1 W
ID = µn Cox (VGS − Vth )2
2 L
This arrangement forces the transistor into a stable operating point, making it ideal for
biasing applications.

Gain Equations
When used as an active load, the effective resistance of the diode-connected transistor is
approximated by:
1
Rdiode ≈
gm
Thus, the voltage gain in a simple model is:

Av = −gm × Rdiode ≈ −1.

1
Using a more refined model that considers the output resistance ro,diode ≈ λID
, the gain
becomes:
Av = −gm × ro,diode .
Moreover, an alternate expression for the gain is given by:
√
gm1
Av = − √ ,
gm2

where gm1 is the transconductance of the input transistor and gm2 is that of the diode-
connected load.

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Circuit Diagram
Here is the schematic of the diode-connected NMOS configuration.

Figure: Diode-Connected NMOS Circuit

Experiment Results
I gathered several sets of simulation data:

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Graph 1: Transient Analysis of Diode Connected Load

Graph 2: Transient Analysis of Diode Connected Load

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 Graph 3: AC Analysis with Output Resistance

Conclusion and Results

This experiment confirmed that a diode-connected NMOS provides the expected V-I
characteristics, making it suitable√ for biasing applications. The various gain models,
g
including the expression Av = − √gm1 m2
, offered valuable insights into the amplifier’s be-
havior. Overall, the simulation results were consistent with the theoretical predictions,
and the hands-on work enhanced my practical understanding of these circuits.

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