American International University- Bangladesh (AIUB)

Faculty of Engineering (EEE)

Course Name: Digital Logic Circuits Course Code: EEE 3101
Semester: Summer 24-25 Assignment Name: OBE Assignment
Marks: 30 Term: Final
Faculty: DR. SHAHRIYAR MASUD RIZVI Section O
Student Name: MD. ISHRAQ AL-DIN SARKER ARNOB Student ID: 23-53603-3 Serial :
Submission Date: 9/20/2025 Department: CSE

Assessed
COs
Program BNQF Teaching-
/ COs/CLOs Statements K P A
Outcome Indicato Learning Strategy
CLOs
Indicator r
Number
Show​ a​ digital​ system​ with​ conflicting P1,P2, OBE Assignment
CO2 3 - P.a.3.C3 FS.1
requirements of a complex engineering problem. P6 (Final Term)

X Y - M E T R O - Z

23 - 5 360 3 - 3
Instructions Related to Use Variables:
Note that this problem uses the variables M, E, T, R, O,
which are the digits of your student ID (XY-METRO-Z).
Any value in student ID comes ‘0’ will be replaced by ‘(X+Y+Z)’

Marking Rubrics (to be filled by Faculty):

Complex Task Assessment Evaluation Criteria Marks

Problem Criteria
P1, P2, Outline the Excellen Good Averag Poor
P6 necessary t (2) (1.5) e (0)
steps of the (1-.5)
block All the steps have Not all the steps Few steps have All the steps
diagram been identified have been been identified have been found
and identified and in the correct in the wrong
I. are in the correct and in the correct sequence sequence.
sequence sequence
FSM design Excellen Good Averag Poor
and HDL Code t (6-5) (4.5-3 e (0)
) (2.5-.5)
All the designs were Not all the designs Few designs were All the designs
accurate and working were accurate and accurate and were wrong and
working working not working
Design counter Excellen Good Averag Poor
with the t (9.5-6 e (2.5-0)
II. necessary (12-10) ) (5.5-3)
diagram and Circuit design is Circuit design is Circuit design is Circuit design is
also DAC correct and complies correct, but does not incorrect and does wrong and does
with the problem comply with the not comply with not comply with
problem the problem the problem
III. Design of Excellen Good Averag Poor
System t (5-4) (3.5-2 e (0.5-0)
with timer ) (1.5-1)
circuit Design is correct and Design is correct Design​ has Design has major
complies with the and complies major​ flaws flaws which does
requirements, with no with the which does not not comply with
or minor calculation requirements, but comply with the the requirements,
errors. with major requirements, with major
calculation errors. but with minor calculation errors.
calculation errors.
IV. Limitations of Excellen Good Averag Poor
the developed t (5-4) (3.5-2 e (0)
system ) (1.5-1)
Provides limitations Provides limitation Provides improper Provides no
and analyzes the only limitations and limitation
performance performance and gives no
correctly analysis performance
analysis
Marks Obtained:
Recently, while traveling by metro in Dhaka, you noticed the automatic crowd management system at
the platform entry. For safety reasons, only 10 passengers are allowed on the platform at a time. A
yellow boundary line is marked before the platform gates.

●​ Each passenger’s ticket card has an RFID sensor that detects entry.
●​ If more than 3 passengers cross the yellow line simultaneously, an alarm should
trigger. The alarm should be activated only when and as long as this condition is met.
●​ A synchronous counter keeps track of the number of people inside the platform. In a day
a maximum of 20 tickets is issued.
●​ A 555 timer is used to generate the clock for both counter and alarm.
●​ The FSM states are encoded as the following: (IDLE → CHECK → OPEN → CLOSE).
●​ The platform monitoring system sends the current passenger count to the control room
in analog form via DAC, while the ADC is used to read sensor inputs.

1.​ Sketch the block diagram of the system showing RFID sensors, ADC, synchronous counter,
FSM, DAC, and alarm unit.
2.​ Demonstrate how the FSM transitions between IDLE, CHECK, OPEN, and CLOSE states
depending on counter values. The FSM transitions from OPEN to CLOSE after 20 tickets are
issued. Also, show Verilog HDL code for the system. [Hint: Use a done-type signal from the
counter to transition from OPEN to CLOSE state.]
3.​ The alarm should trigger if more than 3 passengers cross simultaneously. Show the simplified
Boolean expression for this condition. Show using only NAND gates. Show how this logic
controls the timerN.
4.​ Show the 555-timer circuit for the alarm with frequency = P5 Hz and duty cycle = Q% [where P
= M+E+T+R+O, Q = 100 – P]. If P5 is not within 250–4500 Hz, set f = 400 Hz. Select the most
suitable capacitor from 50 μF, 250 μF, or 470 μF. [Hint: If P=20, then P5=205.]
5.​ Show how the DAC output voltage represents the passenger count for 5 and 10 passengers
(assume 4-bit DAC, Vref = 5 V).
6.​ Illustrate limitations of this developed metro safety system.
 Answer to the question no. 1:

Explanation of the Blocks:

●​ RFID Sensors detect tickets and send input Signals.
●​ ADC Converts analog Sensor signals to digital form
●​ Synchronous Counters Counts passenger entering (max 20/day, max 10 at a time)
●​ FSM (JDLE CHECK Open CLOSE) Controls the Gate
●​ 555 Timer: Provide clock pulse to the counters and alarm.
●​ Alarm unit triggers when> 3 passengers cross Simultaneously.
●​ DAC Converts passenger count to analog voltage for Control room.

Answer to Question No. 2

The FSM (Finite State Machine) has 4 states: IDLE, CHECK, OPEN, and CLOSE.

State Transitions:

●​ IDLE → CHECK: Transition occurs when an entry pulse is detected.

●​ CHECK → OPEN: If passenger count < 10 and alarm = 0.

●​ CHECK → IDLE: If passenger count = 10 or alarm = 1.

●​ OPEN → CLOSE: After allowing one passenger entry and incrementing the ticket counter.

●​ CLOSE → IDLE: If done = 0 (ticket issued < 20).

●​ CLOSE → CLOSE/Lock: If done = 1 (ticket issued = 20).

State Transition Table:

Present State Condition Next State Output

IDLE entry_pulse = 0 IDLE 0

IDLE entry_pulse = 1 CHECK 0

CHECK alarm = 1 OR count = 10 IDLE 0

CHECK count < 10 OR done = 0 OPEN 1

OPEN – CLOSE 1

CLOSE done = 0 IDLE 0

CLOSE done = 1 CLOSE/Lock 0

●​ Verilog HDL code:

module gate_fsm(
input wire clk,
input wire reset,
input wire entry_pulse,
input wire alarm,
input wire [4:0] passenger_count,
input wire [5:0] ticket_issued,
output reg gate_open,
output reg accept_entry
);

localparam IDLE = 2'b00,

CHECK = 2'b01,
OPEN = 2'b10,
CLOSE = 2'b11;

reg [1:0] state, next_state;

wire done = (ticket_issued >= 20);

always @(posedge clk or posedge reset) begin

if (reset)
state <= IDLE;
else
state <= next_state;
end
always @(*) begin
next_state = state;
gate_open = 0;
accept_entry = 0;

case (state)
IDLE: begin
if (entry_pulse)
next_state = CHECK;
end

CHECK: begin
if (alarm || passenger_count >= 10)
next_state = IDLE;
else if (!done)
next_state = OPEN;
end

OPEN: begin
gate_open = 1;
accept_entry = 1;
next_state = CLOSE;
end

CLOSE: begin
if (!done)
next_state = IDLE;
else
next_state = CLOSE;
end
endcase
end

endmodule
 Answer to the question no. 3

If more than 3 passengers cross simultaneously (with 4 sensors S₃, S₂, S₁, S₀), the alarm triggers only when all 4 sensors
= 1.

Here,

Alarm = S₃ · S₂ · S₁ · S₀

Fig: Circuit design only with NAND gate

Controlling 555 Timer:

Here, the alarm signal is connected to the RESET pin of the 555 timer.

●​ When alarm = 1, RESET = HIGH, the 555 timer is enabled and the buzzer turns on.

●​ When alarm = 0, RESET = LOW, the 555 timer is disabled and the buzzer is off.
 Answer to the question no. 4

For My ID 23-53603-3, the values are M=5, E=3, T=6, R=0, O=3.
Thus, P = M + E + T + R + O = 5 + 3 + 6 + 0 + 3 = 17.
The frequency P5 = P × 5 = 17 × 5 = 85 Hz.
Since 85 Hz is not within the range of 250-4500 Hz, the frequency is set to f = 400 Hz.
The duty cycle Q = 100 - P = 100 - 17 = 83%.

The period T = 1/f = 1/400 = 0.0025 s.

The high time TH = duty cycle × T = 0.83 × 0.0025 = 0.002075 s.
The low time TL = T - TH = 0.0025 - 0.002075 = 0.000425 s.

The capacitor values are evaluated for suitability:

For C = 50 μF:
R2 = TL / (0.693 × C) = 0.000425 / (0.693 × 50 × 10⁻⁶) ≈ 12.27 Ω
R1 + R2 = TH / (0.693 × C) = 0.002075 / (0.693 × 50 × 10⁻⁶) ≈ 59.87 Ω
R1 = (R1 + R2) - R2 ≈ 59.87 - 12.27 = 47.60 Ω

For C = 250 μF:

R2 ≈ 2.45 Ω
R1 + R2 ≈ 11.97 Ω
R1 ≈ 9.52 Ω

For C = 470 μF:

R2 ≈ 1.30 Ω
R1 + R2 ≈ 6.37 Ω
R1 ≈ 5.07 Ω

The capacitor C = 50 μF is selected because it gives the highest resistor values, reducing
current and power waste.

Thus, the 555-timer circuit components are:

R1 = 47.60 Ω

R2 = 12.27 Ω

C = 50 μF

The circuit diagram for the 555-timer in astable mode is standard, with R1 connected
between Vcc and pin 7, R2 connected between pin 7 and pins 6/2, and the capacitor C
connected from pins 6/2 to ground. Pins 4 and 8 are connected to Vcc, and pin 1 is
connected to ground. The output is taken from pin 3.
 Answer to the question no. 5
For 5 Passenger,

For, 5 Passenger (5)_10 = (0 1 0 1 ) _2 D3>D2>D1>D0

V_out =-5x2R/R = (0/2^0 + 1/ 2^1 + 0/2^2 + 1 /2^3)

=-5x2R (1/2 + 1/8)= -6.75 = 7V

For 10 Passenger (10)_10 = = ( 1 0 1 0 )_2 D3>D2>D1>D0

V_out =-5x2R/R = (1/2^0 + 0/ 2^1 + 1/2^2 + 0 /2^3)

=-5x2 (1+ 1/4)= -12.5 = 13V

Answer to the question no. 6

Although the developed metro safety system successfully manages platform crowd control, it still has several
limitations as described below which may affect its reliability and performance.

1.​RFID Reading Errors:

The RFID sensor may fail to read a passenger’s ticket card due to metal interference, electromagnetic noise, or it may
read the same card multiple times, which will negatively affect system accuracy.

2.​Simultaneous Crossing Detection:

The logic for detecting more than three passengers crossing at the same time may produce false alarms if passengers
walk closely together but not truly simultaneously.

3.​Fixed Capacity Limitation:

The counter is designed to allow a maximum of 10 passengers at a time and 20 tickets per day, which may not be
suitable for peak hours or special events with high capacity.

4.​Analog Communication Limitations:

Using a low-resolution DAC to send passenger count to the control room may result in inaccurate monitoring due to
analog noise or voltage drop.

5.​Power Dependency:
During power outages, the system may stop functioning unless a reliable UPS or backup power system is provided.

6.​Human Factors and Scalability:

The system cannot distinguish between adults, children, or luggage. It only counts entries but not actual persons. The
system is also designed only for one platform gate.