VerilogBasicsAssignment
Implement below circuits using verilog, write
testbench, compile and simulate using verilog
1. 4x1 Multiplexer
2. 1x4 Demultiplexer.
3. 3x8 Decoder.
4. 8x3 Encoder.
5. Design a 4*1 Multiplexer using conditional operator.
6. Half Adder.
7. Full Adder.
8. Half Subtractor.
9. Full Subtractor
10. Consider the following program:
Module adder sign(X,Y,S,S2s);
input [3:0] X, Y;
output [7:0]S,S2s;
assign S = X + Y,
S2s = {{4{X[3]}}, X} + {{4{Y[3]}}, Y};
Endmodule
(a) If X=0011 and Y=1101, What will be the value of
S and S2s?
(b) What operation is assigned for S2s in the given
program.
11.Write verilog code for below circuits
12.8x1 Multiplexer using 2*1 Multiplexer
13. 1x8 demultiplexer using 1*2 Demultiplexer.
14. 4x16 Decoder using 2x4.
15. 16x4 Encoder using 4x2.
16. n-to-2^n decoder (Hint:using for loop)
17. Design a 8-to-3 Priority Encoder:
(a) using Casex
(b) using for loop
18.4-bit Ripple Carry
Expectation:
Students should write verilog code by themselves, compileand
simulate.
Prepare a very clean and easily readable document, attach the
snaps of waveform, code and testbench.
Installing iverilog & gtkwave
sudo
yum install
iverilog yum
install gtkwave
xzxxCommand to compile &simulate:
iverilog -o my_design
mux2x1_tb.v
mux2x1.v vvp
my_design
gtkwave vcd_file.vcd
Develop the passion of learning. If you do, you will
never cease to grow.