6

Data Conversion Algorithm

In microprocessor and microcontroller based systems, the input, output and intermediate level
data may appear in various formats like: (i) Binary, (ii) Hex, (iii) Unpacked Hex, (iv) Decimal, (v)
BCD, (vi) Unpacked BCD, (vii) CA-code, (viii) CC-code, and (ix) ASCII. The data are the
representations of some practical variables and hence they have certain quantitative values,
which are weighed by numbers. The numbers may be real, complex, integer, floating, unsigned
and signed. During the development phase of a system, a designer encounters situations where
she has to convert data from one format to another. For example, we might be required to convert
the BCD number 20 into CC-type data in order to show it on CC-type 7-Segment display devices
(CC7SDD). In this chapter, we intend to study various types of data conversion algorithms.

6.1 Introduction to Number Systems

6.1.1 Meaning of a Figure
How much does the figure ‘1111’ represent? We certainly would answer as: One Thousand One
Hundred One Ten and One Unit or simply as One Thousand One Hundred and Eleven’. How
much this figure would mean to a microprocessor? Only fifteen! Why has the same figure been
interpreted as having different values? It is because, the ‘Human Being’ takes the number as
having a base of ‘10’ and on the other hand, the microprocessor takes the number as having a
base of ‘2’. The ‘Natural Construction’ of a human being is accompanied with an environment
where she counts things using base ‘10’ because he has 10 fingers in her hands. The ‘Artificial
Construction’ (architecture) of the microprocessor dictates it to count things using base ‘2’
because it has been built with transistors, which posses only two stable states (ON or OFF).
6.1.2 Decimal Number
Human beings use decimal number system to quantify things using ten symbols, which are 0, 1,
2, 3, 4, 5, 6, 7, 8, and 9. The symbols are placed in a row to represent the quantity under some
agreed arbitrary rules. For example:
1111 has the meaning of: 1x103 + 1x102 + 1x102 + 1x100 = 1x1000 + 1x100 + 1x10 + 1x1= 1111 (decimal)

The agreed rules of the decimal number system are:

i. The 1st digit positional weight (Unit Positional Eight = UPW) is 1 = 101 - 1
ii. The 2nd digit positional weight (Ten Positional Weight = TPW) is 10 = 102- 1
iii. The 3rd digit positional weight (Hundred Positional Weight = HPW) is 10 = 103- 1
iv. The 4th digit positional weight (Kilo Positional Weight = KPW) is 1000 = 104- 1
v. and so on for other digits to be inserted to get more and more larger number = 10n - 1
344 Chapter - 6

6.1.3 BCD Number

BCD is an acronym for ‘Binary Coded Decimal’. The actual meaning of BCD is: A decimal digit (0
to 9) is represented using four binary bits (0000 to 1001) for the purpose of storing a decimal digit
in a memory location. Because, the bit capacity of a memory location is 8-bit, it can hold BCD (or
packed BCD) number from 00 to 99. Now, we may say that the sad memory location is full and it
cannot accommodate any more decimal digit. That is to say that the memory location is packed.

6.1.4 Unpacked BCD Number

The BCD representation of a decimal digit is only four bits (0000 to 1001 for the digits 0 to 9). A
memory location has the storage capacity (there is noting such as maximum or minimum) of
eight bits. Then, how would we store a decimal digit (say 3) in a memory location using BCD
format? Certainly, we must use ‘0000 0011’ or ‘1111 0011’ to store the decimal digit 3. This is to
say that the unused upper four bits of the memory location must all be either 0s or 1s. However,
most of the programmers prefer to insert 0s for the unused bits. Now, we say that the memory
location is containing an unpacked BCD (uBCD) number. It is unpacked in the sense that
another decimal digit (if desired) could be inserted replacing the unused upper four bits. So, the
memory location that contains uBCD 03, it can now contain any BCD (packed BCD) number from
03 to 93. The uBCD representation has applications in many data conversion algorithms one of
which is: ‘converting two packets of 8-bit scan codes [Section-7.2.A3, P-376] of two pressed down
keys into a two-digit BCD number’.

6.1.5 Binary Number

Microprocessor uses binary number system to quantify things using two symbols, which are 0, 1.
The symbols are placed in a row to represent the quantity under some agreed arbitrary rules. For
example:
1111 has the meaning of: 1x23 + 1x22 + 1x22 + 1x20 = 1x8 + 1x4 + 1x2 + 1x1= 15 (decimal)

The agreed rules of the decimal number system are:

i. The 1st digit positional weight is 1 = 21 - 1
ii. The 2nd digit positional weight is 2 = 22 - 1
iii. The 3rd digit positional weight is 4 = 23 - 1
iv. The 4th digit positional weight 8 = 24 - 1
vi. and so on for other digits to be inserted to get more and more larger number = 2 n- 1

6.1.6 Hexadecimal Number

Hexadecimal number system is a compact form of binary number system and hence we use it as
a matter of convenience. In hex system, a hex digit is obtained by adding four bits of a binary
number. Thus, the binary number ‘1111 1111 1100 0011’ can be conveniently represented in hex
system using only four hex digits like FFC3.

In hex system, a number is represented using sixteen symbols, which are 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,

A, B, C, D, E, and F. The symbols A, B, C, D, E and F are for the decimal values of 10, 11, 12, 13, 14
and 15 respectively. The symbols are placed in a row to represent the quantity under some
agreed arbitrary rules. For example:
1111 has the meaning of: 1x163 + 1x162 + 1x162 + 1x160 = 4096 + 256 + 16 + 1 = 4369 (decimal)
The agreed rules of the hexadecimal number system are:
Introduction to Number Systems 345

i. The 1st digit positional weight is 1 (01h) = 161 - 1

ii. The 2nd digit positional weight is 16 (10h) = 162 - 1
iii. The 3rd digit positional weight is 256 (100h) = 163 - 1
iv. The 4th digit positional weight is 4096 (1000h) = 164 - 1
vii. and so on for other digits to be inserted to get more and more larger number = 16n - 1

6.1.7 Unpacked Hexadecimal Number

When all the 8-bits of a memory location is used to represent a hex digit, we get an unpacked hex
(uHEX) number. An uHEX number has the similar features to that of the uBCD number.

6.1.8 Unsigned BINary Number

Every bit of the given number carries positive positional values. Thus, we have:
10010001 = 1x27 + 0x26 + 0x25 + 1x24 + 0x23 + 0x22 + 0x21 + 1x20 = 128+16+1 = +145 (decimal)
6.1.9 Signed Magnitude (SM) Method to Represent Negative Number
In this representation, all the bits have positive positional values except the MS-bit. The MS-bit
has no positional value but it carries the ‘Sign’ of the given number. The MS-bit is ‘1’, which
means that the given number is a ‘Negative Number’. Thus, we have:
10010001 = - (+ 0x26 + 0x25 + 1x24 + 0x23 + 0x22 + 0x21 + 1x20) = - (16+1) = -17 (decimal)
6.1.10 2s Complement Code (TC) Method to Represent Negative Number
In this representation:
i. All the bits of the number except the MS-bit carry positive positional values
ii. The MS-bit carries both the positional value and the sign.
iii. If the MS-bit is ‘1’, which means that the MS-bit carries negative positional value.
Thus, we have:
10010001 = - 1x27 + ( + 0x26 + 0x25 + 1x24 + 0x23 + 0x22 + 0x21 + 1x20) = -128+16+1 = -111d
6.1.11 Rules to Obtain TC Code for Negative Number by Manual Method
Showing calculation to obtain the TC for the decimal number –7:
i. Ignore the negative sign of the input number. Now, we have got: 7
Get the 8-bit binary code for 7. We have: 00000111
ii. Invert all the bits of the above step- i. We have: 11111000 (F8H)
iii. Add, 1 with the value of step - ii We have: 11111001 (F9H)
This (F9H) is the TC code for the negative number, -7.
The computers based on Intel’s 8085, 8086, 80186, 80286, 80386, Pentium and 8051 architectures
use TC form while processing the negative numbers.

Example –6.1 [converting –ve number into TC Code]

Write 8086 ASM codes to get TC code for the decimal number –7.
Solution:
mov al, 07h ; apply Rule- i of Section – 6.1.11
not al ; apply Rule-ii of Section – 6.1.11
add al, 01h ; apply Rule-iii al = F9
OR
mov al, - 07h ; use of negative Unary Operator ( Section – 3.1.C3, P-169) al = F9h
346 Chapter - 6

6.2 (a) Converting BINary Number into BCD Number by Counting Rule
6.2.A1 Introduction
There are many occasions where we are required to convert binary number into equivalent BCD
number. For an example, the ‘Cost Computation Flow Chart’ Fig-7.8 indicates that the 8086 have
produced the cost of ‘99.990 Kg goods at the rate of 19.99 Tk/Kg’ as 32-bit binary value, which is
0130FE21h. Now, we need to convert it into equivalent BCD (1998.8001) in order to show the cost
to the customer. The conversion can be can be carried out in two methods:
i. Counting Rule - a Slow Process for comparatively large number,
ii. Horner Rule – a Fast Process to convert data of any size.
6.2.A2 Converting Two-digit (00h – 63h) BINary Number into BCD Number (00 – 99)
Let us carry out an analysis to find the ways of converting a two-digit BINary number (range: 00h
– 63h) into equivalent BCD number (range: 00d – 99d).
If we have the 00h for the input BINary, then we have 00 for the output BCD. When the input
Binary is 01h, the output BCD is 01 and so on. So, we can use the following algorithm for
converting an input Binary number (range: 00h – 09h) into equivalent BCD number (00 – 09):
i. Keep the input BINary number (INPBIN) in ah-register,
ii. Keep initially 00 as initial partial BCD (IPBCD) into ah-register for the output BCD.
iii. Keep incrementing the al-register and decrementing the ah-register until ah-register is
emptied. Here, we are counting up the destination register (al) for as many times as the
source register (ah) is. This is reason for calling it the Counting Rule.
iv. The Binary-to-BCD (BIN2BCD) conversion is complete and the al-register contains the
BCD number
v. The scenario is presented below in tabular form:
Input BIN Expected Output BCD
00 00
01 01
02 02
………………………………..
………………………………..
08 08
09 09
0A 10
0B 11
…………………………………
63 99

We observe in the above table that for the BINary inputs, 00-09h; the output BCD number is same
as the input Binary number. But, for the inputs, 0Ah – 63h, the expected outputs are, 10 – 99.
6.2.A3 BIN2BCD Conversion Algorithm for Input BINary Number of Range: 00h – 63h
if (input BINary = 00h – 09h)
{
no need of BIN-to-BCD conversion;
output BCD = input BIN;
exit;
}
Converting BINary Number into BCD Number by Counting Rule 347

if (input BINary = 0Ah – 63h)

{
input BINary needs conversion to produce the correct BCD as per table of P-340;
exit;
}

6.2.A4 Analysis to Develop the Formal BIN2BCD Routine for Input BINary of Range: 00h –
63h
The Counting Method:
Say, the input BINary = 0Ah
The expected output BCD = 10
How can we get the output image, 10 for the input image 0Ah?
Let us look at the following table, which does the BIN-to-BCD conversion process.
Steps: Operation Input BINary Partial BCD Remarks
0 nothing 0A 00 (0000 0000) …………..
1 increment Output BCD by 1 09 01 (0000 0001 …………..
decrement Input Binary by 1
2 same as above 08 02 (0000 0010) …………
3 same as above 07 03 (0000 0011) …………
4 same as above 06 04 (0000 0100) …………
5 same as above 05 05 (0000 0101) …………
6 same as above 04 06 (0000 0110) …………
7 same as above 03 07 (0000 0111) …………
8 same as above 02 08 (0000 1000) ………..
9 same as above 01 09 (0000 1001) …………...
10 same as above 00 0A (0000 1010) BCD is to be 10 (00010000)

In the above table, we have finished the conversion by decrementing the input BINary for as
many times as the input BINary is and at the same time incrementing (adding BCD 01) the output
BCD. Assume that the previous BCD value is 09. Now we have added 01 with it and the result
should be BCD 10. But, the output has turned into an incorrect BCD of 0Ah instead of correct
BCD of 10. It has been due to the binary nature of the CPU, which has considered the input
numbers as binary and accordingly it has performed a binary addition on them. Now, to get the
desired BCD, the output bit pattern, 0000 1010 has to be transformed to the pattern, 0001 0000 by
adding 06h (0000 0110) with the incorrect BCD. The scenario appears as:
……………………………………………………………………………………………………………………………
Input Incorrect Desired Operations Required Remarks
BINary Output BCD Correct BCD to get Correct BCD
09h - 09 (0000 1001) - Correct BCD
0AH 0A (0000 1010) 10 (0001 0000) 0000 1010
+ 0000 0110 (06) add 06 with incorrect BCD
--------------------
0001 0000 (10d) Correct BCD is obtained
………….…………………………………………………………………………..……………………………………
19H - 19 (0001 1001) - Correct BCD
1AH 1A (0001 1010) 20 (0010 0000) 0001 1010
+ 0000 0110 (06) add 06 with incorrect BCD
-------------------
0010 0000 (20d) Correct BCD is obtained
348 Chapter - 6

From the analysis of P-341, we observe that:

When we tell the CPU to add two BCD numbers (incrementing the BCD number 9 by 1 - means adding
the BCD numbers 9 and 1), it carries out Binary addition on the given numbers and produces an
incorrect output BCD result. The output BCD result is not wrong but incorrect, which means that the
incorrect output BCD result could be corrected (adjusted) to obtain the correct output BCD result.

From the analysis of P-341, we may now state the following rule, which will obtain correct BCD
result from an incorrect BCD result after the addition of two BCD numbers (example: add 9, 1).
Rule-1: Add 06 with the incorrect output BCD result to get correct BCD when the lower 4-
bit of the incorrect BCD result is greater than 09.
6.2.A5 Control Structure for BIN2BCD Conversion: (Input BINary Range: 00h – 63h)
L1: 00 (Initial Partial BCD Result = IPBCD) → al
INPBIN → ah
L2: while (ah !=0)
{
increment the content of al-register
If ((al3 – al0) > 9)
06 + al → al
}
L3: save result
L4: end
6.2.A6 8086 Assembly Program for BIN2BCD Routine of Section-6.2.A5
Let us assume that 5Ah is an input BIN number and is available via memory location 03001h of
the following data structure of Fig-6.1. The DSM
expected output BCD would be saved at location
03300h. 04FFF End Address

03302 Output
03301
03300 BCD = 90

03002 Input
03001 BIN = 5Ah
03000 Start Address

00000 Base Address

577b
Figure-6.1: Data Structure for Counting Rule Based BIN2BCD Conversion Routine
L1: mov ah, BYTE PTR [bx+01h] ; the input Binary is brought into ah
mov al, 00h ; IPBCD (00) in al-register
L1A: add al, 01h ; output BCD result is incorrect
cmp al, 09h ; checking if (al3 – al0 ) > 9
jng L2 ; IPBCD hasn’t taken the form 0A, 1A,2A
add al, 06h ; adjustment done to get correct BCD
L2: dec ah
jnz L1A
L3: mov BYTE PTR [bx+0300h], al ; BCD is saved in location 03300h
L4: hlt
Converting BINary Number into BCD Number by Counting Rule 349

6.2.A7 BIN2BCD Conversion for Input BINary Range: 00h – FFh

The input binary numbers has the range 00h – FFh. The expected BCD is 0000 – 0255.
Analysis
1. Control structure of Section-6.2.A5 works for the input BINary number with range: 00h – 63h.
2. For the input BINary number 63h; the expected BCD is: 99 (1001 1001)
3. For the input BINary 64h; the expected BCD is: 100 (1 0000 0000)
4. For the input BINary 64h; we have to increment the previous BCD number 99. As a result, we will
get an incorrect output BCD of value 9A whose bit pattern is: 1001 1010
5. Add 06 with the result of step-4 (lower 4-bit >9). 1001 1010
+ 0000 0110 Rule – 1, P-342
We get ………………………… 1010 0000 : not a pattern for 100
6. Add (0110 0000 = 60) with the result of step-5. + 0110 0000 New Rule = 2
------------------------------------------------------------------------
We get…………………………. 1 0000 0000 : yes a bit patter of 100
7. A carry is generation in the operation of step-6. It constitutes the MS-Part of the result.

From the above analysis, we may state the next new rule (Rule-2) to obtain correct BCD result:
Rule-2: Add 60h with the incorrect BCD result to get correct BCD result when the upper 4-
bit of the incorrect BCD is greater than 09.
6.2.A8 Pseudo Codes for BIN2BCD Routine for Input BINary Number of Range: 00h – FFh
Before we proceed writing the routine, we must declare storage locations (either Registers- or Memory
Space) of appropriate sizes so that they can hold the input number and the output result correctly. In the
present case, we reserve an 8-bit (1 byte) storage location to hold the input binary number. How many byte
locations are to be reserved for the output BCD result? The output number (the result) is a BCD number
with base 10 and its positional weight is less than the positional weight of the hex system. Therefore, we
need more storage locations to hold the BCD result. In this case, we can declare two byte storage locations to
hold the BCD result. From the above analysis, we also observe that the upper part of the result is due the
accumulated carries. The carries are produced due to repetitive additions – a direct consequence of the
Counting Rule.
Now, we may write the following control structure:
L1: initialize everything as needed;
BIN Æ ah; 00 Æ al; 00 Æ cl (carry_counter)
L2: if (BIN = 0)
Goto L10 ; input BINary = 00, so the output BCD = 00
L3: inc al ; increment IPBCD
If ((al3 – al0) != 9)
Goto L5
L4: al + 06h → al ; lower 4-bit of incorrect BCD > 9, so add 06h (Rule – 1)
L5: If ((al7 – al4) != 9)
Goto L7
L6: al + 60h Æ c, al ; upper 4-bit of incorrect BCD > 9, so add 60h (Rule – 2)
L7: If (carrybit ! = 1)
Goto L9
L8: cl + 01h → cl ; Increment the carry_counter , the cl-register;
L9: ah – 01h → ah
If (ah !=0)
Goto L3
L10: al-register contains lower part of the BCD result and the cl-register contains the upper part.
L11: end
 Chapter - 6
350

6.2.A9 Flow Chart and 8086 Assembly Codes for BIN2BCD Routine for Input BINary
Number of Range: 00h – FFh (Counting Method)

START: nop
L1: mov ah, BIN ; Input BIN
mov al, 00h ; IPBCD
mov dl, 00h ; Carry Counter

L2: cmp ah, 00h

jz L10

L3: add al, 01h

mov ch, al
and ch, 0Fh
cmp ch, 09h
jle L9 ; ch <= 9

L4: add al, 06h

L5: mov ch, al

mov cl, o4h
shr ch, cl
cmp ch, 09h
jle L9 ; ch <= 9
L6: add al, 60h

L7: jnc L9

L8: add dl, 01h

L9: dec ah
jnz L3

L10: ; result in <dl, al>

L11: hlt

Figure-6.2: Flow Chart/ASM Code to Convert Two-digit (00h – FFh) Binary into BCD by Counting Rule

Example – 6.2 [Converting 2-digit Binary Number 00h – FFh into BCD by Counting Method]
Let us test the BIN2BCD routine of Section-6.2.A9 using MicroTalk-8086 trainer. The input BINary number
will be taken from memory location 03010h and the BCD result will be shown at DP0 – DP3 positions of the
display unit of the trainer.
Procedures:
1. Type the assembly codes of Section – 6.2.A9 and save it as: ……\mtk8086\P62b.asm
2. Write the following codes at L1 by deleting the code mov ah, BIN
mov si, 3000h
mov ah, BYTE PTR [bx+10h] ; reading input Binary from memory location 03010h
3. Append the following codes at L10
call RESDISP ; BCD result will be shown at display unit.
4. Assemble the program and down load the P62b.abs (or P62.abs) file into the trainer starting at 01000h.
5. After down loading, enter input binary via 03010h and then execute the program at location 01000h.
6. The result will be seen at DP5 – DP8 positions of the display unit of the trainer.
7. Test the program by entering any other input binary value at location 03010h.
Rules to Adjust Incorrect BCD into Correct BCD after Addition 351

6.2 (b) Rules to Adjust Incorrect BCD into Correct BCD after Addition
6.2.B1 Introduction
We have observed the following facts in the previous studies:
i. When the 8086 microprocessor is asked to add two BCD numbers, it does the addition
process by considering the input BCD numbers as if these are the Binary numbers and
produces an incorrect BCD result.
ii. We have seen the existence of two rules (Rule-1 and Rule-2), which must be applied on
the incorrect BCD result to get the correct BCD result.
In practice, there may be any combination of BCD numbers waiting for addition. We shall see in
the following discussion that the above two rules do not cover all possible BCD numbers. In fact,
there exits Four Rules, which cover all possible BCD numbers.
Case-1:
BCD1 = 17 : 0001 0111
+ BCD2 = 13 : 0001 0011
------------------------------------------------------------------------------------------
Incorrect BCD = 2A : 0010 1010
Adjustment + 06 : 0000 0110
------------------------------------------------------------------------------------------
Correct BCD = 30 : 0011 0000
Rule-1 : After the addition of two BCD numbers, let us check if the lower 4-bit is greater than 9 and then add
06 with the incorrect BCD result to get the correct (adjusted) BCD.
…………………………………………………………………………………………………………………
Case-2:
BCD1 = 83 : 1000 0011
+ BCD2 = 21 : 0010 0001
------------------------------------------------------------------------------------------
Incorrect BCD = A4 : 1010 0100
Adjustment + 60 : 0110 0000
------------------------------------------------------------------------------------------
Correct BCD = 104 : 1 0000 0100
Rule-2 : After the addition of two BCD numbers, let us check if the upper 4-bit is greater than 9 and then
add 60h with the incorrect BCD result to get the correct (adjusted) BCD.
……………………………………………………………………………………………………………………………………………………………………………………………………………………………………

ase-3:
BCD1 = 78 : 0111 1000
+ BCD2 = 09 : 0000 1001
------------------------------------------------------------------------------------------
Incorrect BCD = 81 : 1000 0001 ; lower 4-bit < 9; upper 4-bit < 9
Adjustment + 06 : 0000 0110
------------------------------------------------------------------------------------------
Correct BCD = 87 : 1000 0111
The incorrect BCD result is 1000 0001 where the lower 4-bit is less than 9 and the upper 4-bit is also less than
9. But, from the observation, we can tell that 06h has to be added with the incorrect BCD result to get the
correct BCD result. We just cannot do it at will! We must find a reason to add 06h. Somebody (I don’t who
and when) went through the bit pattern of the input and output BCD numbers and she noticed that there
occurred an auxiliary carry (carry from the middle of the bit) during the addition. This clue could be taken
as a reason to formulate the 3rd rule, which is:
352 Chapter - 6

Rule-3 : After the addition of two BCD numbers, let us check if there has occurred an auxiliary carry and
then add 06 with the incorrect BCD result to get the correct (adjusted) BCD.
…………………………………………………………………………………………………………………
Case-4:
BCD1 = 90 : 1001 0000
+ BCD2 = 79 : 0111 1001
------------------------------------------------------------------------------------------
Incorrect BCD = 109 : 1 0000 1001
Adjustment + 60 : 0110 0000
------------------------------------------------------------------------------------------
Correct BCD = 169 : 1 0110 1001

The incorrect BCD result is 1 0000 1001 where the lower 4-bit is not greater than 9 and the upper 4-bit is also
not greater than 9. But, from the observation, we can tell that 60h has to be added with the incorrect BCD
result to get the correct BCD result. When we observe the bit pattern of the input and output BCD numbers,
we notice that a full carry had occurred (carry from the last bit) during the addition. This clue could be taken
as a reason to formulate the 4th rule, which is:

Rule-4: After the addition of two BCD numbers, let us check if there has occurred any full carry and then
add 60h with the incorrect BCD result to get the correct (adjusted) BCD.
…………………………………………………………………………………………………………………

6.2.B2 daa Instruction of the 8086 to get Correct (adjusted) BCD from Incorrect BCD
Assume that the CPU has been asked to add two unknown BCD numbers, which are BCD1 and
BCD2. After the addition, we will have to apply all the above-mentioned four rules to get the
correct BCD result. The program is:
L1: mov al, BCD1
add al, BCD2 ; result in C, al
L2: if (al4 – al0) > 9
al + 06h → al
L3: if (al7 – al4) > 9
al + 60h → al
L4: if (AC = 1)
al + 06h → al
L5: if (C = 1)
al + 60h → al

In order to allow the CPU executing the above program, all the pseudo codes from L2: to L5:
must be replaced by valid assembly codes. And in fact, the programmers had to do this for all the
microprocessors until the arrival of 8085. Starting from 8085, all the later MPUs of the Intel family
have built-in electronic circuitry to implement the functionalities of these four rules. The 8086
instruction set contains a single instruction named daa, which could be invoked to replace all
these four rules by activating the internal electronic circuitry of the 8086. The instruction daa
stands for: ‘carry out Decimal adjustment after Addition on the content of al-register’. We must
note that the daa works only on the al-register. The above program can now be re-written as:
L1: mov al, BCD1
add al, BCD2
L2: daa ; correct BCD in C, al
Rules to Adjust Incorrect BCD into Correct BCD after Addition 353

Example – 6.3 [ Adding two BCD numbers and then adjusting by daa instruction]
Write 8086 ASM codes to add the BCD numbers 123456 and 945678. Be sure that the result is a correct BCD
number of 01069134 (decimal 1069134).
Solution:
A: Register Model

B: Computation Mechanism
1. bh + bl → C, bh ; < 0, CE > : < 0, 1100 1110 > Incorrect Partial Result
apply all four rules ; < 1 , 34 > : < 1, 0011 0100 > Corrected Partial Result
2. ch + cl + C → C, ch ; < 0, 8B > : < 0, 1000 1011 > Incorrect Partial Result
apply all four rules ; < 0, 91 > : < 0, 1000 0001 > Corrected Partial Result
3. dh + dl + C → C, dh ; < 0, A6 > : < 0, 1010 0110 > Incorrect Partial Result
apply all four rules ; < 1, 06 > : < 1, 0000 0110 > Corrected Partial Result
4. Now, the final Correct BCD result is: 01 06 91 34
C: Assembly Codes
L1: add bh, bl ; 78h + 56h = CEh = 1100 1110
mov al, bh ; daa instruction is only applicable on al-register
daa ; CEh + 06h + 60hh = 1 34 < 1,34 >,Rule-1,2 are applied
mov bl, al ; bl = 34

L2: adc ch, cl ; 56h + 34h + 01h = 8Bh = 1000 1011

mov al, ch ;
daa ; 8Bh + 06h = 0 91 : < 0, 91 > , Rule-1 is applied
mov bh, al ; bh = 91

L3: adc dh, dl ; 94h + 12h + 00h = A6h = 1010 0110

Mov al, dh
Daa ; A6h + 60h = 1 06 : < 1, 06 > , Rule-2 is applied.
Mov cl, al ; cl = 06

L4: jnc L5
mov ch, 01h ; ch = 01
L5: call RESDISP ; result at DP1 = DP8 positions of the tainer
L6: hlt ; Final correct BCD result in : < ch, cl, bh, bl >
D: Procedures to Execute using MicroTalk-8086 Trainer
1. Pass the 1st BCD number via memory locations < 03012, 03011, 03010 >.
2. Pass the 2nd BCD number via memory locations < 03015, 03014, 03013 >.
3. Insert ASM instructions at suitable place of the above program to read the input BCD numbers form
the memory locations and keep them into relevant registers as per register model given above.
4. Insert ASM instructions at suitable place of the above program to show result at DP1 – DP8 positions
of the trainer [see …\mtk8086\p63.asm].
5. Save the complete program as …\mtk8086\P63b.asm. Assemble it and down load the P63b.abs (or
P63.abs) into the trainer starting at location 01000h.
6. Execute the down loaded program.
7. The correct result will be shown at DP1-DP8 positions of trainer.
354 Chapter - 6

6.3 Converting Binary Number into BCD by Horner Rule

6.3.1 Introduction to Converting n-bit Binary Number into Equivalent BCD
The ‘Counting Method’ that we have seen in Section-6.2 (a) for the conversion of Binary number
into BCD number is a slower process. The Counting Rule is a slower process because we have to
decrement the input number one-by-one until it becomes zero and only at this moment the
output BCD result becomes available.

In Section – 6.2.A9, we find that there are 21 ASM instructions, which are required to convert the
number FFh into 0255 using the counting rule. If we use the ‘Fast Method’ (also known as
Horner Rule), only 16 assembly codes produce the BCD result [Example-6.4, P-349]. There is a
saving of five instructions. In reality, we deal with numbers containing tens of digits and in this
case the Horner Rule is the only choice to adopt to convert binary number into BCD. As we will
see shortly, the Horner Rule pours reagent to the conversion process for approaching to the BCD
result very fast [Example-6.4, P-349].

Assume that we have an n-bit unsigned binary number as follows:

Input Binary = bn-1bn-2, ................................, b1b0
Output BCD = bn-1x2n-1 + bn-2x2n-2+ .....................................+ b1x21 + b0x20
= (bn-1x2n-1 + bn-2x2n-2+ ................................+b2x21+ b1)2 + b0
= ((bn-1x2n-1 + bn-2x2n-2+ ............................... + b3x21+b2)2+ b1)2 + b0
…………………………………………………………………………..
= (((.........(((bn-1)2 + bn-2)2+ ............................... + b3)2+b2) 2+ b1) 2 + b0

‘something_2’

‘something_1’
When we carefully observe the above expression while moving from right to left, we notice that
the bit values are always added with ‘something’, which is multiplied by 2. For example:
i. The b0-bit is seen to have been added with: (something_1) x 2 + b0
ii. The b1-bit is seen to have been added with: (something_2) x 2 + b1
………………………………………………………………………………………………………………………………
………………………………………………………………………………………………………………………………
iii. The bn-2 - bit is seen to have been added with: (something_n-1) x 2 + bn-2

But, this feature is not seen for the last bit, bn-1[4]. In order to offer similar feature to every bit
including the bit bn-1, we may re-write the above expression as follows:
Output BCD = (((.......(((IPBCD)2 + bn-1)2 + bn-2)2+ ............. + b3)2+b2)2+ b1)2 + b0
where, IPBCD stands for ‘Initial Partial BCD’ and is assigned the value of 00

The above expression is known as ‘Horner Expression or Horner Rule’ due to W.G. Horner, who
used it in the year of 1819 (the original rule belongs to Isaac Newton in 1711) for algebraic
simplification. This is a particular case of the general-purpose polynomial of the form:
A(x) = anxn + an-1xn-1 + ...………...+ a2x2 + a1x1 + a0x0 [19].
Converting Binary Number into BCD by Horner Rule 355

Golam Mostafa (the author) of Ahsanullah University of Science and Technology (AUST), Dhaka,
for the 1st time in Bangladesh in the year of 1998, carried out the low-level implementation of the
Horner Rule to convert 32-bit unsigned BINary number into equivalent BCD number in
connection with the design of a ‘Digital Weighing Machine (DWM)’ based on the 8-bit
architecture of the Intel 8085 microprocessor. The author implemented it for the 8051
architectures in the year 2003 and that for the 8086 architecture in the year 2004. In fact, the
author had an eye on it in 1992 when he intended to develop the DWM along with Prof. Dr.
Shamsuddin at the EEE department of IIT (now IUT) in connection with the design of DWM.

6.3.2 Evaluation of Horner Expression for n-bit Binary Number

In Section-6.3.1, we deduced the following Horner Rule to convert n-bit binary number into
equivalent BCD number:
Output BCD = (((.......(((IBCD)2 + bn-1)2 + bn-2)2+ ............. + b3)2+b2)2+ b1)2 + b0
where, IPBCD stands for ‘Initial Partial BCD’ and is assigned a value of 00

Simple observation tells us to adopt the following steps:

i. Assign 00 as an initial value for IPBCD and then compute the expression: (IBCD)2 + bn-1
for BCD value. Let us keep the computed BCD value of (IBCD)2 + bn-1 into the variable,
IPBCD. Now, we have:
(((.......(((IBCD)2 + bn-2)2+ ............. + b3)2+b2)2+ b1)2 + b0.

ii. Let us compute the expression: (IBCD)2 + bn-2 for its BCD value and keep the result
into the variable, IPBCD. Now, we have:
(((.......(((IBCD)2 + bn-3)2+ ............. + b3)2+b2)2+ b1)2 + b0.
………………………………………………………………………………
Finally, we will compute the BCD value of (IBCD)2 + b0 and its value would be kept into the
variable, IPBCD. Now, it is the IPBCD, which holds the correct BCD value for the given n-bit
binary number. The readers have certainly noticed the key-role played by the term IPBCD for
accumulating the partial results as the evaluation of the Horner Rule was going on for each bit of
the input binary number.

The tasks carried out by the above steps may concisely be represented in the following ways:
i. Catch the MS-bit (bn-1) of the input binary number by shifting the bit in the Carry bit.
ii. Evaluate the BCD value for the expression: (IPBCD x 2 + bn-1 ) → IPBCD. This means
updating the Partial BCD result.
iii. Repeat Step-ii for all the bits including LS-bit (b0)
The above three steps may also be represented in one of the following two ways:
(i) IPBCD x 02 + bx ) → IPBCD ; where x = n-1, n-2,……..,1, 0
(ii) x = n - 1;
while ( x != - 1)
{
IPBCD x 02 + bx ) → IPBCD ;
x--;
}
 Chapter - 6
356

Example – 6.4 Convert 8-bit Binary Number (00h – FFh) into BCD (0000 – 0255) using Horner Rule
1. Input Binary = b7 b6 b6 b5 b3b2b1b0
2. Output BCD (using Horner Rule) = (((IBCDx2+b7) 2 + ......+ b2)2 + b1)2 + b0 [where, IBCD = 00]
3. Manual Demonstration of the Computation Mechanism
Assume an input binary data: BIN = FFh = 11111111B
Expected BCD = 0255
Step Bit Shifted to Carry No of Rotation Partial Value Contributed Partial Contribution
Left Bit (C) /Rest Data (Previous_Partial x 2 + C) To Total Value
Through Carry
1 b7 1 1st (00h) 2 + 1 = 01h
/1111111x daa ; 01 01d

2 b6 1 2nd (01h) 2 + 1 = 03h

/111111xx daa ; 03 03d

3 b5 1 3rd (03h) 2 + 1 = 07h

/11111xxx daa ; 07 07d

4 b4 1 4th (07h) 2 + 1 = 0Fh

/1111xxxx daa ; 15 15d

5 b3 1 5th (15h) 2 + 1 = 2Bh

/111xxxxx daa ; 31 31d

6 b2 1 6th (31h) 2 + 1 = 63h

/11xxxxxx daa ; 63 63d

7 b1 1 7th (63h) 2 + 1 = C7h

/1xxxxxxx daa ; 127d 127d

8 b0 1 8th (1, 27h) 2 + 1 = 2, 4Fh

/ xxxxxxxx daa ; 2, 55d 255D Result OK

In the 1st step, we have computed (IPBCD) 2 + b7 and found the BCD result of: (00) 2 + 1 = 01d. In the 2nd, 3rd,
…, 8th steps, the partial values have been computed using the previous partial value and the current data bit
and it agrees with the Horner Rule. In every step, the partial result appears as the double of the previous
partial value. The binary to BCD conversion process is complete in only eight steps, which corresponds to
the number of bits present in the input binary number. The Horner Rule is really fast comparing to the
Counting Rule of Section-6.2.A9, which requires that the input binary number have to decremented one-by-
one for as many times as the number is.
4. 8086 Based Data Structure to Implement the Computation Mechanism

Figure-6.3: 8086 Register Model to Implement BIN2BCD Routine for 8-Bit Data using Horner Rule
Converting Binary Number into BCD by Horner Rule
357

5. Computation Control Structure

initialize everything as needed; Input BINary → ch; IPBCD (0000) → < bh, bl >; rotation_count (08h) → cl
while (rotation_count !=0)
{
bl x 2 + bx [ x = 7,6,...,1,0]
daa al → bl
bh x 2 + carry
daa al → bh
}
6. Computation Flow Chart

Figure-6.4: Flow Chart to Implement the BIN2BCD Routine for 8-Bit Data
7. Coding of the Flow Chart of Fig-6.4
START: nop
L1: mov ch, INPBIN ; input Binary is in ch-register
mov bl, 00h ; IPBCD = 00 lower byte
mov bh, 00h ; IPBCD = 00 upper byte
mov cl, 08h ; bits in the input Binary
clc
L2: rcl ch, 01h ; b7 is caught and kept in carry bit
L2A: call EVADH ; evaluate (IPBCD x 2 + bx)→ IPBCD by Horner Rule
L3: dec cl
jnz L2
L4: call RESDISP ; result at display DP5 – DP8 of the trainer
358 Chapter - 6

L5: hlt
L6: jmp L2
EVADH: mov al, bl
adc al, al ; performing al x 2 + bx
daa ; adjusting to correct BCD.
mov bl, al
mov al, bh ; getting upper byte of the PBCD
adc al, al ; performing ah x 2 + c
daa ;
mov bh, al
ret
8. Procedures for Program Execution:
a. Open the program …\mtk8086\P64.asm and look into its structure
b. Download program …\mtk8086\p64.abs. Enter the input binary (00h – FFh) via 03010h.
c. Execute the downloaded program at 01000h. The DP1-DP8 positions show the BCD result.

6.3.3 Mechanism of Implementation of Horner Rule for Converting 32-bit Binary into BCD
Let us assume that we have:
Input BIN = b31b30 ………………………..b1b0
= 0000 0001 0011 0000 1111 1110 0010 0001
= 0130FE21h
Expected BCD = 19988001
According to Horner Rule:
BCD = (((……(IPBCD) 2 +b31)2 + b30 )2 + ………………+ b1)2 + b0
It is assumed that the given 32-bit Binary number (00000000h – 0130FE21h) is given via the
indicated memory locations of Fig-6.5. The output BCD number (range: 00000000 – 19988001) is
available to the user via the indicated memory locations of Fig-6.5.
W orking R egister: al
Input BINary (00000000H - 0130FE21H) Ouput BCD (0000000- 19988001)
R AM Input BIN- Data Order Internal R AM Output BC D Data Order
di 03003 x7x6 M SDigits cx 03303 y7y6 MSDigits
03002 x5x4 BIN2BCD 03302 y5y4
si 03001
03000
x3x2
x1x0 LSDigits bx 03301
03300
y3y2
y1y0 LSDigits

BIN2BC D
03003 03002 03001 03000 03303 03302 03301 03300
31 24 23 16 15 8 7 0 7 6 5 4 3 2 1 0

Input : 32-Bit Binary Data Ouput: 8-Digits BC D Data

638a R otation C ount in: ah

Figure-6.5: Recommended Data Structure to Convert 32-bit Binary into BCD using Horner Rule
Mechanism of Catching b31 and then b30 and then b29, ………, and then b15 and so on…..
i. Bring the input binary number from external memory into the di and si registers of the 8086
CPU. Now, we have the following binary pattern for the input binary number 0130FE21h.

Figure-6.6: 32-bit Input Binary Number is Loaded into di- and si-register
Converting Binary Number into BCD by Horner Rule 359

ii. Let us catch b31 by bringing it into the carry-flag (CF) position of the FR-register of the 8086.
Next, we have to catch the b30 bit and next b29 and … and then b0. While catching the input
data bits using the CF, we must be sure that whenever the b31 enters into the CF, the b30 must
enter into b31 position, ……., b16 into b17, b15 into b16, ……., and b0 into b1 position. This
requirement can be achieved by executing the following two instructions:
a. rcl si, 01h
The above instruction shifts the bits of SI-register to the left by 1-bit position and
through the CF as per rules shown below:
TP (Temporary Position) ← SI15 (MS-bit of SI-register = b15)
SIn + 1 ← SIn ; n = 0 – 14
SI0 ← CF ; the previous value of CF enters at SI0 (LS-bit of SI-register = b0)
CF ← SI15 ; SI15 (MS-bit of SI-register = b15) has entered into CF
b. rcl di, 01h
The execution of the rcl di, 01h instruction follows the same rules as that for the rcl si,
01h instruction. Therefore, the rcl di, 01h instruction will accomplish events that are:
TP (Temporary Position) ← DI31 (MS-bit of DI-register = b31)
DIn + 1 ← DIn ; n = 16 - 30
DI16 ← CF ; previous value of CF (b15) enters at SI16 (LS-bit of DI-register = b16)
CF ← DI31 ; DI31 (MS-bit of DI-register = b31) has entered into CF

After the execution of the above two ASM instructions, the bit pattern of the di and si are :

Figure-6.7: Bit Pattern of DI- and Si-Registers after the Execution of ‘rcl di, 01h & rcl si, 01h’ Instructions
Mechanism of Updating the BCD Result Table.
It has been shown in Fig-6.5 that the cx- and bx-registers are reserved for holding the BCD
number. The Horner Rule produces the final BCD in an incremental way, which is:
i. Initially keep 0000 0000 as IPBCD (Initial Partial BCD) in the cx- and bx-registers.
ii. Catch b31 and compute : IPBCD x 2 + b31.
iii. Step-ii involves the addition of a BCD number with itself and then with b31. which could be 0 or
1. The addition will be carried out the MPU, which will simply perform a binary addition on the
given numbers. The result will be an incorrect BCD. Therefore, we will have to apply the daa
instruction to get correct BCD. Let us recall that daa instruction only work on al-register.
iv. Add the partial result of Step-iii with the previous BCD, which resides in cx and bx.
v. Repeat Step-ii to iv for all the bits of the input binary number.

The following ASM codes could be executed to implement the above steps:

Figure-6.8 : Registers to Hold the BCD Result for the given 32-bit Binary Number
360 Chapter - 6

L1: ; IPBCD is 0000 0000 and store them in cx and bx registers

mov cx, 0000h ; IPBCD = 0000 0000
mov bx, 0000h
L2: ; it is assumed that the bit b31 has been made available in the CF of
; the CPU by the subroutine CTACHBIT. And now, compute IPBCD x 2 + b31.
; It means that:if we consider all the four 8-bit registers of Fig-6.8 as a
; single 32-bit register, then we need to add it with itself and then add
; the carry bit, which is either 0 or 1. After that, we need to perform
; necessary adjustment on the incorrect BCD result (by daa instruction) to
; get correct BCD. However, practically, we have four separate 8-bit
; registers. Now. We can update it in the following way:
a. Get the content of bl-register and add it with itself and add with
bit b31 of the input binary.
b. Perform BCD adjustment by executing the daa instruction. The upper
part of the result (0 or 1) will enter into the carry bit of the CPU
and the lower 8-bit will enter into bl-register.
c. Get the content of bh-register. Add it with itself (because we have
to compute (IPBCD x2) and then add it with the carry bit of the
previous operation. Perform daa operation to get correct BCD.
d. Similar operations as above for the remaining cl and ch registers.

mov al, bl ; because daa works only on al-register

adc al, al ; (al + al + b31)→ c, al ; b31 is already in carry bit
daa ; correct BCD is in carry bit and al-register
mov bl, al ; lower 8-bit of the corrected BCD is put back into bl
;-------------
mov al, bh
adc al, al
daa
mov bh, al
;--------------
mov al, cl
adc al, al
daa
mov cl, al
;--------------
mov al, ch
adc al, al
daa
mov ch, al
;--------------
Final Pseudo Codes for 32-bit BIN2BCD Conversion Routine
L1: ; cx and bx are initialized with IPBCD of 0000 0000
; di and si are initialized with 32-bit input binary number
; ah-register is initialized with number of bit rotation, 32 (20h).
; al-register is reserved for daa operation
L2: call CTACTHBIT ; get the MS-bit, next bit of the input and so on..
Call EVADH ; use SUR to compute IPBCx2 + bx and update PBCD
L3: dec ah ; checking if computation is done for all the bits
jnz L2 ; IPBCX2 + bx is not finished for all bits
nop ; conversion done. The BCD number is in cx and bx
L4: call BCD2CC7SDD ; send result to 7SDD display of MicroTalk-8086
L5: hlt
Converting BCD Number into BINary by Counting Rule
361

6.4 Converting BCD Number into BINary by Counting Rule (Slow Method)
6.4.1 Introduction
There are many applications where we need to convert a decimal (the BCD) number into its
equivalent binary number before the next processing could be carried out. For example, in a
Digital Weighing Machine (Chapter-7), the input weight and the rate are the decimal/BCD
numbers. To get the cost, we have to multiply these two BCD numbers. But the 8086 architecture
doesn’t support the multiplication of two BCD numbers. Therefore, it is required that we convert
the given BCD numbers into BIN numbers and then carry out the binary multiplication to get
binary cost. We then convert the binary cost into BCD cost to get the cost in decimal format.
6.4.2 Converting Two-digit BCD (00 – 99) into BINary (00h – 63h)
In this section, we will take a simple example of a two-digit unsigned BCD number (range: 00 –
99 = 0000 0000 to 1001 1001) to demonstrate the principles of BCD-to-BIN (BCD2BIN) conversion
using Counting Method.
In Counting Method, the conversion process follows the steps outlined below:
i. The BCD number is expressed in terms of its positional values. Thus, we have:
BCD = TU
Where:
T stands for Ten Positional Factor, TPF (0 – 9)
U stands for Unit positional Factor, UPF (0 – 9)
BCD = TPF x Ten Positional Weight + UPF x Unit Positional Weight
BCD = TPFx101 + UPFx100
= (TPF x TPW) + (UPF x UPW)
= TPV (Ten Positional Value) + UPV (Unit Positional value)
Here, the given number is a BCD and it is a BCD number because the ‘Positional Weights’ of
the digits are given by decimal format. Therefore, the corresponding BINary number could
be easily found by replacing the positional decimal weights by the corresponding positional
binary weights. This transformation just changes the number form the decimal domain into
the binary domain but it doesn’t change the quantity. Now, we can state that:
BIN = TPF x 0Ah + UPF x 01h
ii. Now, let us evaluate the above expression as:
a. Computing TPV, which is multiplication of two numbers that can be done by repetitive additions
(some sort of counting procedure).
b. Computing UPV, which is the multiplication of the numbers UPF and 01h.
c. Computing BIN = TPV + UPV

Counting Method would take relatively longer time to finish the conversion when the input BCD
number is very large (say 4-digit like 8934). It is due to separate computation of all the Positional
Values and then adding them together to get the final binary result. There is a Fast Method
(really very fast and is known as Horner Rule)) for BCD2BIN conversion.
6.4.3 Control Structure for Two-digit BCD2BIN (00 – 99) Routine Counting Rule
L1: Extract UPF and TPF
L2: while (UPF !=0)
IPR1 (00h) + 01h → IPR1 → UPV
L3: while (TPF !=0)
IPR2 (00h) + 0Ah → IPR2 → TPV
L4: BINary Number = UPV + TPV
362 Chapter - 6

6.4.4 ASM Codes to Convert Two-digit BCD (00-99) into BINary by Counting Rule
Assume that the input BCD number (00 – 99) is given via RAM location 03010h of DSM. The
following ASM codes will read the BCD number from a memory location and then will convert it
into binary. The result will be saved into memory location 04010h of the DSM.
L1: mov bx, 3000h
mov cl, BYTE PTR [bx+10h] ; al = input BCD (say 35)
and cl, 0Fh ; getting UPF = 05 in cl-register

mov ch, BYPTE PTR [bx+10h] ; cl = input BCD (say 35)

mov ch, cl SHR 04h ; get TPF = 03 in ch-register
; see Section-3.1.C3 for SHR operator
L2: mov al, 00h ; IPR1 = 00h in al-register
L2A:add al, 01h ; adding UPW = 01h
dec cl ; cl register holds UPF
jnz L2A ; al contains partial UPV

L3: mov ah, 00h ; IPR2 = 00h in ah-register

L3A:add ah, 0Ah ; adding TPW = 0Ah
dec ch ; ch register holds TPF
jnz L3A ; ah-register contains partial TPV

L4: add al, ah ; al-register contains BINary number

mov BYTE PTR [bx+4010h], al ; result is saved in location 04010h of DSM

In the above example, we have not considered the carry. The size of the input BCD number (00 –
99) indicates that the output BINary would be (00h – 63h), which fits in an 8-bit register.
However, if the input BCD number is 257 (0000 – 0257, the BCD format), the output BINary is:
0101h and we have to consider the carry that is generated after the addition of UPV and TPV.
The result is greater than 8-bit and two 8-bit registers (one 16-bit register) must be used to hold
the result.

Example – 6.5 [Converting 4-digit BCD number into Binary by Counting Rule]
Derive expression based on Counting Rule for converting four digit BCD number (KHTU = 0000 - 9999) into
BINary number (0000h - 270Fh) and then write control structures for its evaluation.
Solution:
BCD = KHTU
= Kx103 + Tx102 + Hx101 + Ux100
= Kx1000 + Hx100 + Tx10 + U x1
BIN = KPF x 03E8h + HPF x 64h + TPF x 0Ah + UPF x 01h
L1: Extract UPF, TPF, HPF and KPF
L2: while (UPF !=0)
IPR1 (00h) + 01h → IPR1 → UPV ; IPR1 = Initial Partial Result - 1
L3: while (TPF !=0)
IPR2 (00h) + 0Ah → IPR2 → TPV
L4: while (HPF !=0)
IPR3 (00h) + 64hh → IPR3 → HPV
L5: while (KPF !=0)
IPR4 (00h) + 03E8h → IPR4 → KPV
L6: 16-bit Binary number is in ax-register = UPV + TPV + HPV + KPV
Program Execution using MicroTalk-8086: Download …\mtk8086\p65.abs. Enter input via memory
locations <03011, 03010>. Execute at 01000h. The Binary result will appear at DP5 – DP8 positions of display.
Converting BCD Number into BINary by Horner Rule
363

6.5 Converting BCD Number into BINary by Horner Rule (Fast Method)
6.5.1 Introduction to the Conversion of n-digit BCD into BINary using Horner Rule
The theory of the development of Horner Rule for converting BCD number into BINary number
is similar to that of BINary to BCD. However, in the case of BCD to BINary conversion using
Horner Rule, there appears a little bit difficulty, which is:
i. In the case of BINary to BCD conversion, we deal with only a single bit of the input
binary number. The value of the bit could be either 0 or 1 and hence the task of
evaluating IPBCDx2 + bx was relatively a simpler job.
ii. In the case of BCD to BINary conversion, we deal with a digit of the input BCD
number. The value of the digit can be any one of the ten symbols (0, 1, 2, 3, 4, 5, 6, 7, 8,
9) of the decimal number system. Now, the task of evaluating the expression IPBIN x
0Ah + dx faces a little bit of difficulty.

Let us assume that we have an n-digit BCD number. Therefore, the BCD is:
BCD = dn-1 dn-2……………………………d1d0
= dn-1 x 10n-1 + dn-2 x 10n-2 + ………+ d1 x 101 + d0 x 100
= (dn-1 x 10n-2 + dn-2 x 10n-3 + ……...+ d1) 10 + d0
………………………………………………………………………………………………….
= ((……(dn-1) 10 + dn-2 ) 10 + ……..+ d1 ) 10 + d0 ; it is a BCD because of the weight 10
So, the equivalent BINary is:
BIN = ((…..(dn-1) 0Ah + dn-2 ) 0Ah + ….+d1 ) 0Ah + d0 ; it is a BIN because of the weight 0Ah
If we scan the above series from the right to the left we observe that the digit value is added with
‘something’, which has been multiplied by 0Ah. But this pattern is not found for the digit dn-1. To
offer similar pattern to all the digits, we may re-write the above expression as:
BIN = (((IPBIN x 0Ah + dn-1) 0Ah + dn-2 ) 0Ah + ……..+ d1 ) 0Ah + d0
Where, IPBIN (Initial Partial Binary)=00. This is known as Horner Expression.

6.5.2 Computation Model for n-digit BCD2BIN Conversion using Horner Rule
Iterative Approach: From left to right
Computation Philosophy: Catch digit value of the input BCD and add it with 0Ah times of the
previously computed partial BINary value. Continue until the same
is done for the LS-digit of the input BCD.
Pseudo Codes:
L1: initialize everything as needed. Get BCD number and store them in a table.
L2: extract dn-1 from BCD table
pass dn-1 as unpacked BCD via a suitable register
call EVABH ; EVABH will compute (IPBIN x 0Ah + dx ) → IPBIN
L3: repeat all the steps of L2: for all the digits including d0 of the input BCD number.

EVABH: ; computing IPBIN x 0Ah + dx and updating the IPBIN

SL1: Compute (IPBIN x 0Ah ) → L ; L refers to a Location (RAM or Register) stcak.
SL2: perform (L+ dx ) → IPBIN
SL3: return to calling routine
364 Chapter - 6

6.5.3 Converting Two-digit (00-99) BCD into BINary (00h – 63h) by Horner Rule
Let us assume:
Input BCD = d1d0 (78) and is available via location 03001h of the DSM of MicroTalk-8086
Expected BIN = 4Eh and is available to user via location 04010h of the DSM of MicroTalk-8086
According to Horner Rule :
BIN = ((IPBIN x 0Ah + d1) 0Ah + d0
Computation Data Structure:

Figure-6.9 : Data Structure for Converting Two-digit BCD (00-99) into Binary (00h – 63h) using Horner Rule
8086 Assembly Codes:
The particular input BCD number 78 is taken to understand the steps involved in the conversion.
L1: mov ax, 0000h ; IPBIN = 00h
mov ch, BYPTR PTR [bx+01h] ; input BCD is in ch-register d1d0 = 78
mov cl, 04h
mov dl, ch
sar dl, cl
anl dl, 0Fh ; dl contains 07
call EVABH ; EVABH computes (IPBIN x 0Ah + dx)→ IPBIN
anl ch, 0FH ; extracting d0 as 08 from input BCD
call EVABH
L2: mov BYTE PTR [bx+4010h], al ; BINary output is at location 04010h
hlt
EVABH: mov bl, 0Ah ; Evaluate to Binary Value using Horner Rule
mul bl ; computing (IPBIN x 0Ah) → ax-register
mov dh, 00h
add ax, dx ; computing (IPBIN x 0Ah + dx)→ al (ah = 00)
ret

Example – 6.6 [Converting 4-digit BCD number into Binary by Horner Rule]

1. Open the program …\mtk8086\P66.asm and look into its structure

2. Down load the program …\mtk8086\P65x.abs into the McroTalk-8086 trainer.
3. Enter the input BCD (4-igit) number via memory locations <03011, 03010>.
4. Execute the down loaded program at 01000h.
5. The DP3 – DP8 positions of the trainer will show the binary value for the input BCD number.
6. Test the functioning of the program for different input BCD numbers.
Multiplication of Unsigned Binary Numbers by Formula 365

6.6 (a) Multiplication of Unsigned Binary Numbers by Formula

6.6.A1 Introduction
In our ‘good old days’ of primary schooling, we were lined up every morning to recite a long
‘Multiplication Table (MULTAB, in Bangla, we call it Namta)’. We had been using the MULTAB
(a mental calculator compared to today’s CASIO Calculator) for performing addition,
subtraction, multiplication and division calculations on decimal numbers. In our present ‘good
scientific days’, we are still using this table for arithmetic calculations. The tradition of learning
the Namta (MULTAB) through recitation is still going on in our primary schools. The Namta
(MULTAB) contains the following formulae:
Table – 6.1 : Multiplication Table (MULTAB, Namta)
1x 1 = 1 2x1 = 2 3x1 = 3 …… 9x1 = 9 10x1 = 10 11x1 = 11 12x1 = 12 … 20x1 = 20
1x2 = 2 2x2 = 4 3x2 =6 …… 9x2 = 18 10x2 = 20 11x2 = 22 12x2 = 24 … 20x2 = 40
1x3 = 3 2x3 = 6 3x3 = 9 …… 9x3 = 27 10x3 = 30 11x3 = 33 12x3 =36 … 20x3 = 60
1x4 = 4 2x4 = 8 3x4 = 12 …… 9x4 = 36 10x4 = 40 11x4 = 44 12x4 = 48 … 20x4 = 80
1x5 = 5 2x5 = 10 3x5 = 15 …… 9x5 = 45 10x5 = 50 11x5 = 55 12x5 = 60 … 20x5 = 100
1x6 = 6 2x6 = 12 3x6 = 18 …… 9x6 = 54 10x6 = 60 11x6 = 66 12X6 = 72 … 20x6 = 120
1x7 = 7 2x7 = 14 3x7 = 21 …… 9x7 = 63 10x7 = 70 11x7 = 77 12x7 = 84 … 20x7 = 140
1x8 = 8 2x8 = 16 3x8 = 24 …… 9x8 = 72 10x8 = 80 11x8 = 88 12x8 = 96 … 20x8 = 160
1x9 = 9 2x9 = 18 3x9 = 27 …… 9x9 = 81 10x9 = 90 11x9 = 99 12x9 = 108 … 20x9 = 180
1x10 = 10 2x10 = 20 3x10 = 30 …… 9x10 = 90 10x10 = 100 11x10 = 110 12x10 = 120 … 20x20 = 400

6.6.A2 Multiplication of Two 8-bit Unsigned Binary Numbers by mul Formula

After observing that the 8086 provides the result of 20 x 20 (14h x 14h) by executing the
instruction mul 14h , 14h (almost equivalent to 14hx14h) , we immediately feel excited to say that
the 8086 somehow has learnt the MULTAB. But the actual fact is something else, which is:
We (the human being) have permanently recorded the MULTAB in our biological memory (brain or
mind or somewhere else?) after reciting it for so many times. The 8086 has no biological memory and
therefore, there is no way for it to remember the MULTAB. The designer of the 8086 has embedded
electronics circuitry within the MPU to compute the said multiplication job by repetitive additions.
This electronics circuit is called upon by executing the instruction: mul ah.

In the case of unsigned multiplication of 8-bit binary numbers:

a. Data1 (say, the Multiplicand, MLPC) must be in the al-register,
b. Data2 (say, the Multiplier, MLPR) can reside in an 8-bit GPR-register or in a memory location,
c. The 16-bit Result (Product) will always be accumulated by the ax-register. The ah-register holds
the upper 8-bit and the al-register holds the lower 8-bit of the result.
Pseudo Codes: ASM Codes:
L1: MLPC → al L1: mov al, 16h ; MLPC = 78h
MLPR → ah mov bah 15h ; MLPR = 15h
L2: al x ah → ax L2: mul ah ; the result is in < ah, al > ; ax = 09D8h = 2520

The meaning of mul bl should stand as: The 8-bit content of the al-register (al-register always
remains silent in the mul instruction) is multiplied with the 8-bit content of the ah-register and the
16-bit result is placed in the ax-register.
If the data2 (say, the MLPR) resides in a memory location, then the instruction syntax would be
as follows, where the data2 is accessible by any one of the valid ‘Memory Addressing Modes [Fig
– 2.42, P-113].
mul BYTE PTR ds:[si]
366 Chapter - 6

Example – 6.7 [ mul instruction for multiplication of two 8-bit unsigned numbers]
Write ASM programs to multiply the unsigned numbers 78h and 15h and save the source codes as P66.asm
in the path ….\mtk8086\P66.asm. Download the corresponding P66.abs file into the RAM space of the
MicroTalk-8086 trainer starting at location 01000h. (a) Execute the downloaded program using S/S (Single
Stepping) command and check that at the end of the execution of the mul instruction, the ax-register
contains 09D8h. (b) Reset the trainer and execute the whole program using the DOP (Do a Program)
command and then observe that the 7SDD unit shows the result both in hexadecimal (09D8) and BCD (2520)
formats.
Procedures:
1. Goto the DOS path: ….\mtk8086. [from the CD marked as CDGMW1].
2. Open the file P66.asm and see its contents and structure.
3. Exit the DOS screen.
4. Assemble the program using MASM to create the files: P66.lst and P66.obj.
5. Process the P66.obj file using LOD186 to create the file P66.abs.
6. Follow the steps of Section – 1.7.B4 (P-35) to download the P66.abs file.
7. Enter input hex numbers 78h and 15h via memory locations 03010h and 03011h [see procedures at P-
35].
7. Single step the downloaded program as per labels of the P66.lst program [see procedures at P-35].
8. After single stepping the mul instruction at 010Dh, check the content of the ax-register for the value
09D8.
9. Reset the trainer and execute the whole program using the DOP command.
10. The 7SDD unit of the trainer shows result in both hexadecimal and BCD formats as per following
layout.
i. Product as Hex Number at Positions: DP0 – DP3
ii. Product as BCD Number at Positions: DP10 – DP15
11. Study the following structure of the P66.asm program.
START: nop
L1: ; initialize as needed
L2: ; read MLPC into al-register from location 03010h
; read MLPR into ah-register from external DSM location 03011h
L3: mul ah
L4: call SEND_HEXRESULT_7SDD
L5: call SEND_BCDRESULT_7SDD
L6: hlt
;-------------------------------
SEND_HEXRESULT_7SDD:
SR1: ;------------------------
;------------------------
call HEX2CC
SR2: ;-------------------------
call CCXDRAM
ret
SEND_BCDRESULT_7SDD:
S21: ;------------------------
S22: call EVADH ; Evaluate Decimal Value using Horner Rule ------
;------------------------
S23: call CCXDRAM
ret
Multiplication of Unsigned Binary Numbers by Formula 367

6.6.A3 Multiplication of Two 16-bit Unsigned Binary Numbers by mul Formula

In the case of unsigned multiplication of two 16-bit binary numbers:
d. Data1 (say, the Multiplicand, MLPC) must be in the ax-register,
e. Data2 (say, the Multiplier, MLPR) can reside in a 16-bit GPR-register or in two consecutive
memory locations,
f. The 32-bit Result (Product) will always be accumulated by the < dx, ax > register. The dx-register
holds the upper 16-bit and the ax-register holds the lower 16-bit of the result.

Pseudo Codes: ASM Codes:

L1: MLPC → ax L1: mov al, 0FFFFh ; MLPC = 65535
MLPR → bx mov bx, 0FFFFh ; MLPR = 65535
L2: ax x bx → <dx, ax > L2: mul bx ; result in < dx, ax > = FFFE0001h = 4294836225

The meaning of mul bx should stand as: The 16-bit content of the ax-register (ax-register always
remains silent in the mul instruction) is multiplied with the 16-bit content of the bx-register and
the 32-bit result is placed in the < dx, ax > register.
If the data2 (say, the MLPR) resides in a memory location, then the instruction syntax would be
as follows, where the data2 is accessible by any one of the valid ‘Memory Addressing Modes [Fig
– 2.42, P-113].
mul WORD PTR ds:[si]

Example – 6.8 [mul instruction for multiplication of two 16-bit unsigned numbers]
Download the program …\mtk8086\P68.asm into the MicroTalk-8086 trainer starting at location 01000h.
Enter the 16-bit MLPC (say, FFFFh) via memory locations < 03011h, 03010h >. Enter the 16-bit MLPR (say,
FFFFh) via memory locations < 03013h, 03012h >. Execute the program. The DP0 – DP9 positions of the
trainer should show the 32-bit result in BCD format (4294836225). Try with other numbers.

6.6 (b) Multiplication of Signed Numbers by Formula

6.6.B1 Multiplication of Two 8-bit Signed Binary Numbers by imul Formula
In 80x86 architecture, ‘Two’s Complement Code (TC)’ system is used to represent the negative
numbers. In TC, a negative number has a LH at its MS-bit position and it represents negative
positional value. All other bits (b6 – b0) represent positive positional values. For a positive
number, there is always a LL at its MS-bit position. Accordingly, under TC’s rule, we have the
following range of numbers that are presentable by 8-bit codes.
- 128 (decimal) = 1000 000 (80h) (binary) = -1x27 + ( 0x26 + ………….+ 0x20)
-1 (decimal) = 1111 1111 (FFh) (binary) = -1x27 + ( 1x26 + ………….+ 1x20)
0 (decimal) = 0000 0000 (00h) (binary) =
+127 (decimal) = 0111 1111 (7Fh) (binary) = 0x27 + ( 1x26 + ………….+ 1x20)
The imul stands for ‘Integer Multiplication’. It can multiply both positive and negative numbers,
of the range shown above. The working principle of the imul instruction has already been
discussed in Section-3.5 (c). Let us make some more studies here with examples:

Example – 6.9 [ imul instruction for multiplication of two 8-bit signed/unsigned numbers ]
Multiplicand, MLPC = -128 (decimal)
Multiplier, MLPR = +127 (decimal)
Expected Product = -128 x 127 = -16256 (decimal)
368 Chapter - 6

ASM Codes:
START: mov al, -128 ; one operand must be in al-register
mov ah, +127 ; 2nd operand may be in a register or in a memory location
imul ah
The result is in the ax-register and is C080h. Now, this figure must be processed by user program
to get the expected BCD value of –16256. This means that we have to somehow obtain 3F80h (this
is the unsigned binary of 16256) from C080h and then convert the 3F80h into its BCD value of
16256. And then place the –ve sign before 16256 at the time of display. Observe that imul has
produced the result C080h (and not 3F80h).
According to Intel literature, the imul instruction affects only the CF- and the OF-flags [P-87]. It
doesn’t update the SF-flag. The author has observed through experiments that the sign and
magnitude of the result of imul instruction could be obtained by consulting the following flow
chart:

Figure – 6.10 : Flow Chart to Determine the Sign and Magnitude of the Result of imul Instruction
SL1: jo SL2A
SL2: ; extract sign from the result
mov bl, ah ; bl = C0h to determine the value of MS-bit
rcl bl, 01h
jnc SL6 ; SF = 0
SL3: jnc SL5
SL4: ; result is negative ; SF = 1
mov dx, 0000h
sub dx, ax
mov ax, dx ; ax = 3F80H = 16256
call BIN2BCD
; place –ve sign before the result 16256 to get -16256
call DISPLAY
hlt
SL5: jmp SL4
SL6: jnc SL8
SL7: nop
SL8: ; result is positive; extract it and then display
hlt
Multiplication of Signed Binary Numbers by Formula 369

SL2A: ; extract sign from the result

mov bl, ah ; bl = C0h to determine the value of MS-bit
rcl bl, 01h
jnc SL6A ; SF = 0
SL3A: jnc SL5A
SL4A: nop
SL5A: jmp SL8
SL6A: jc SL8A
SL7A: nop
SL8A: jmp SL4

Program Execution by DOP Command:

1. Download the program ….\mtk8086\P69.abs.
2. Enter the input data for MLPC and MLPR in Hex format as per following table [Table-6.1] via the
indicated memory locations.
3. Execute the whole program using the DOP command of the MicroTalk-8086 trainer.
4. Observe the expected result on the display devices as per following table.
Table – 6.1
SN. MLPC via 03000h MLPR via 03001h Expected BCD Result Output on Display of Com.
MicroTalk-8086 Trainer
DP0 DP1 ………..……DP6
1 + 127 (7Fh) + 127 (7Fh) + 16129 + 016129 OK
2 + 127 (7Fh) - 128 (0h) - 16256 - 016256 OK
3 - 128 (80h) - 128 (80h) + 16384 + 016384 OK
4 + 56 (38h) + 55 (37h) + 3080 + 003080 OK
5 - 18 (EEh) + 81 (51h) - 1458 - 001458 OK
6 - 84 (ACh) + 81 (51h) - 6804 - 006804 OK
7 + 108 (6Ch) + 81 (51h) + 8748 + 008748 OK
Program Execution by Single Stepping Command to Verify the Validity of the Flow Chart of Fig-6.10
1. Open the file ….\mtk8086\P68.lst.
2. Download the program CDGMW1\mtk8086\P68.abs.
3. Enter the input data for MLPC and MLPR in Hex format as per following table [Table – 6.2] via the
indicated memory locations.
3. Follow the address labels of the P68.lst file and then execute one instruction at a time using the S/S
command until the address field shows 01018h.
4. Now check the content of the ax-register (press AX key) and the flag bits (press FB key). Check that the
values of ax-register and the flag bits agree with values that are given in the following table.
5. Trace the Flow Chart of Fig-6.10 as per flag bit values of the following table and check that the flow
chart of F-g-6.10 helps to find the sign and the magnitude of the result of imul instruction.
Table – 6.2
Sn MLPC MLPR Expected Result Flag Bits Sign and Magnitude Com.
via 03000h via 03001h as per Fig-6.9x
BCD AX O S C
F F F
1 + 127 (7Fh) + 127 (7Fh) + 16129 3F01h 1 0 1 + BCD of 3F01h OK
2 + 127 (7Fh) - 128 (0h) - 16256 C080h 1 1 1 - BCD of |0000h – C080h| OK
3 - 18 (EEh) + 81 (51h) - 1458 FA4Eh 1 1 1 - BCD of |0000h – FA4Eh| OK
4 - 128 (80h) - 128 (80h) + 16384 4000h 1 0 1 + BCD of 4000h OK
5 + 108 (6Ch) + 81 (51h) + 8748 222Ch 1 0 1 + BCD of 222Ch OK
6 - 1 (FFh) - 1 (FFh) +1 0001h 0 0 0 + BCD of 0001h OK
370 Chapter - 6

6.6.B2 Multiplication of Two 16-bit Signed Binary Numbers by imul Formula

The working principles of the imul instruction for 16-bit signed/unsigned numbers are same as
that for the imul instruction for 8-bit signed/unsigned numbers. The only difference is in the size
of the output result. While dealing with 16-bit values, we have the following range of numbers
that are presentable by 16-bit codes.
- 32768 (decimal) = 1000 000 0000 0000 (8000h) = -1x215 + ( 0x214 + ………….+ 0x20)
-1 (decimal) = 1111 1111 1111 1111 (FFFFh) = -1x215 + ( 1x214 + ………….+ 1x20)
0 (decimal) = 0000 0000 0000 0000 (0000h)
+ 32767 (decimal) = 0111 1111 1111 1111 (3FFFh) = 0x215 + ( 1x214 + ………….+ 1x20)

In 16-bit by 16-bit unsigned multiplication, one operand must be in the ax-register. The 2nd
operand may reside in one of the valid GPRs or in two consecutive memory locations. The imul
instruction produces 32-bit signed result for negative numbers an unsigned result for positive
numbers. The upper 16-bit of the result goes into dx-register and the lower 16-bit result goes into
ax-register. Let us verify the validity of the working principles of the imul instruction for the
input data (MLPC, MLPR) of the following table [Table – 6.3].
Table – 6.3
SN. MLPC via MLPR via Expected BCD Result Output on Display of Com.
<03001h, 03000h> <03003h, 03002> MicoTalk-8086 Trainer
DP0 DP1 ………..…DP10
1 + 32767 (7FFFh) + 32767 (7FFFh) + 1073676289 + 1073676289 OK
2 + 32767 (7FFFh) - 32768 (8000h) - 1073709056 - 1073709056 OK
3 - 32768 (8000h) - 32768 (8000h) + 1073741824 + 1073741824 OK
4 - 1 (FFFFh) - 1 (FFFFh) -1 - 0000000001 OK
5 - 4096 (F000h) + 4096 (1000h) - 16777216 - 0016777216 OK

Example – 6.10 [ imul instruction for multiplication of two 16-bit signed/unsigned numbers ]
Program Execution by DOP Command:
1. Download the program …\mtk8086\P610.abs into the MicroTalk-8086 trainer.
2. Enter the input numbers (MLPC and MLPR) of Table-6.3 via the indicated memory locations.
3. Execute the downloaded program at 01000h using the DOP command.
4. The display unit of the trainer should show the correct sign and magnitude of the result.
Program Execution by Single Stepping Command to Verify the Validity of the Flow Chart of Fig-6.9x
1. Follow address labels of P69.lst file and then execute one instruction at a time using the S/S command
until the address field shows 01018h.
4. Now check the content of the <dx, ax> registers and the flag bits. Verify that the values agree with
values that are given in the following table [Table-6.4].
5. Trace the Flow Chart of Fig-6.9x as per flag bit values of the following table and check that the flow
chart of F-g-6.9x helps to find the sign and the magnitude of the result of imul instruction.
Table – 6.4
S MLPC via MLPR via Expected Result Flag Bits Sign and Magnitude Com
n <03001, <03003, 03002h> as per Fig-6.9x
03000h> BCD <DX, AX> O S C
F F F
1 + 32767 (7FFFh) + 32767 (7FFFh) + 1073676289 3FFF 0001 1 0 1 + BCD of 3FFF 0001h OK
2 + 32767 (7FFFh) - 32768 (8000h) - 1073709056 C080 8000 1 1 1 - BCD of |00000000h-C0008000h| OK
3 - 32768 (8000h) - 32768 (8000h) +1073741824 4000 0000 1 0 1 + BCD of 40000000h OK
4 - 1 (FFFFh) - 1 (FFFFh) -1 0000 0001 0 0 0 + BCD of 00000001h OK
5 - 4096 (F000h) + 4096 (1000h) - 16777216 FF00 0000 1 1 1 - BCD of |00000000 – FF000000| OK
Multiplication of Unsigned Binary Numbers by Repetitive Additions
371

6.6 (c) Multiplication of Two Unsigned Binary Numbers by Repetitive Additions

6.6.C1 8-bit x 8-bit Unsigned Multiplication by Repetitive Additions
In Section-6.6.A2, we have used the mul instruction to multiply two 8-bit unsigned binary
numbers. The mul instruction uses a multiplication (MULTAB) table similar to Table – 6.1 to find
the product of two numbers. The mul instruction is, in fact, the implementation of ‘finding the
product of two numbers by repetitively adding the Multiplicand with previously computed
partial results for as many times as the Multiplier is’. For example:
The value of 05h x 04h (14h) can be obtained as follows:
i. Using the mul instruction:
mov al, MLPC ; MLPC (multiplicand) is in al-register
mov bh, MLPR ; MLPR (multiplier) is in bh-register
mul ah ; product is in ax-register

ii. Using Repetitive Addition Process (RAP):

Multiplicand, MLPC = data1
Multiplier, MLPR = data2
Product = add MLPC with initial partial result (IPR = 00h)
cumulatively for as many times as the MLPR is.

We intend to practice the RAP method for multiplication in order to get familiar with the basic
instructions that the MPU carry out to multiply two numbers. In practical applications, while
dealing with large numbers, we will be using the mul instruction.
Let us assume that we have the following two numbers to multiply:
MLPC = 00h – FFh
MLPR = 00h – FFh
Result = 0000h – FE01h

The upper part of the result is, in fact, the accumulation of the carry bits that are generated owing
to repetitive addition processes.
The Computation Process:
i. Data Structure

Figure-6.11: Data Structure for Multiplying Two 8-Bit Unsigned Numbers by Repetitive Additions
372 Chapter - 6

ii. Flow Chart

Figure-6.12: Flow Chart describing Multiplication by Repetitive Additions

iii. Pseudo Codes
START: nop
L1: Initialize base address of DSM
Initialize the bx-pointer to point locations in DSM
0000h → dsr
3000h → bx
al ← 00h (IPR = 00)
00h → 04001h (Ccounter) ; Carry Counter
L2: Read MLPC and keep in al-register
Read MLPR and save in ah-register
cl ← (03010h) ; al = MLPC
ch ← (03011h) ; ah = MLPR
L3: al + MLPC → C, al ; multiplication process begins by RAP
L4: if (Carry = 1)
Goto L9
Multiplication of Unsigned Binary Numbers by Repetitive Additions 373

L5: MLPR- 01h → MLPR

L6: if (MLPR !=0)
Goto L3
L7: Result Lower Byte (RLbyte) → 04000h
Result Upper Byte (RUbyte) → 04001h
L8: halt
L9: Ccounter + 01h → Ccounter
Goto L5

iv. Assembly Codes

START: nop
L1: mov ax, 0000h
mov ds, ax ; SBA is set at 00000h
mov bx, 3000h ; beginning address of DSM
mov al, 00h ; IPR = 00
mov BYTE PTR ds:[bx+1001h], 00h ; Carry Counter = 00
L2: mov cl, BYTE PTR ds:[bx+3010h] ; read MLPC
mov ch, BYTE PTR ds:[bx+3011h] ; read MLPR
L3: add al, cl ; result in C, cl
L4: jc L10
L5: dec ah ; decrementing the MLPR
L6: jnz L3 ; all additions are not done
L7: mov BYTE PTR ds:[bx+1000h], cl ; save Result_Lower_Byte
L8: call RESDISP

L9: hlt
L10: add BYTE PTR ds:[bx+1001h], 01h ; carry bits are accommodated
jmp L5

Program Execution:

Example – 6.11 [multiplying two 8-bit unsigned numbers by repetitive additions]

1. Let us open the program …\mtk8086\P611.asm and see its structure. This program takes the MLPC
and MLPR from the user via the keyboard of the MicroTalk-806 trainer. The input and output variables
are shown in the data structure of Fig-6.11.
1. Down load program …\mtk8086\P611.abs into the MicroTalk-8086 trainer stating at location 01000h
2. Enter the MLPC (say: FFh) via memory location as indicated in the data structure of Fig-6.11.
3. Enter the MLPR (say: F0h) via memory location as per data structure of Fig-6.11.
4. Execute the program starting at location 01000h. See Appendix-A for the procedures of
executing a down loaded program using MicroTalk-8086.
5. The Hexadecimal format of the result will appear at the DP3-DP8 positions of the display
unit of the trainer.
6. The decimal format of the result will be shown at DP10-DP15 positions of the display unit of
the trainer.
374 Chapter - 6

6.6.C2 16-bit x 16-bit Unsigned Multiplication by Repetitive Additions

In this section, we shall multiply two unsigned 16-bit numbers by ‘full repetitive addition’
method using the MicroTalk-8086 microprocessor learning system. There will be absolutely no
use of either of the following two instructions, which are available with the 8086 architectures.
-

i. mul al, byte_data

ii. mul ax, word_data
Let us assume that we have the following two unsigned 16-bit numbers to multiply.
04FFF

0300F r7r6
0300E r5r4 Final
0300D r3r2 Result
0300C r1r0
0300B r7’’’’r6’’’’ L4:
0300A r5’’’’r4’’’’
03009 r5’’’r4’’’
Output DSM
L3:
03008 r3’’’r2’’’ Partial
519 03007 r5’’r4’’ L2: Result
x3x2 x1x0 : Multiplicand, MLPC 03006 r3’’r2’’
y3y2 y1y0 : Multiplier, MLPR 03005 r3'r2' L1:
r3'r2' r1'r0' = (x1x0) x (y1y0) : L1 03004 r1'r0'
03003 x3x2
r5’’r4’’ r3’’r2’’ = (x3x2) x (y1y0) : L2 Multiplicand
03002 x1x0
Inputs
r5’’’r4’’’ r3'''r2''' = (x1x0) x (y3y2) : L3 03001 y3y2
Multiplier
03000 y1y0
r7’’’’r6’’’’ r5’’’’r4’’’’ = (x3x2) x (y3y2) :L4 02FFF
r7r6 r5r4 r3r2 r1r0
01000 CSM
Carry Carry
00000
559b
Figure-6.13: Computation Mechanism Figure-6.14 : Input/Output Data Structure

Program Codes to Implement Computation Mechanism of Fig-6.11

START: nop
00h → r7r6, r5r4, r3r2, r1r0 ; initial results
00h → r1’r0’, r3’r2’, r3’’r2’’, r5’’r4’’, r3’’’r2’’’, r5’’’r4’’’, r5’’’’r4’’’’, r7’’’’r6’’’’
L1: - compute [x1x0]x[y1y0] by repetitive addition
mov al, 00h ; al is the working register and also holds IPR
mov ah, y1y0 ; ah holds the multiplier
L1A: add al, x1x0
jc L1C
L1B: dec ah
jnz L1A
jmp L1D
L1C: r3’r2’ + C → r3’r2’
Jmp L1B
L1D: al → r1’r0’ ; we have : [r3’r2’ r1’r0’] for L1: [x1x0)]x [y1y0]
L2: - compute [x3x2]x[y1y0] by repetitive addition
mov al, 00h ; al is the working register s
mov ah, y1y0 ; ah holds the multiplier
L2A: add al, x3x2
jc L2C
L2B: dec ah
jnz L2A
jmp L2D
Multiplication of Unsigned Binary Numbers by Repetitive Additions 375

L2C: r5’’r4’’ + C → r5’’r4’’

Jmp L2B
L2D: al → r3’’r2’’ ; we have : [r5’’r4’’ r3’’r2’’] for L2: [x3x2]x [y1y0]
L3: - compute {[x1x0]x[y3y2]} by repetitive addition
mov al, 00h ; al is the working register and also holds IPR
mov ah, y3y2 ; ah holds the multiplier
L3A: add al, x1x0
jc L3C
L3B: dec ah
jnz L3A
jmp L3D
L3C: r5’’’r4’’’ + C → r5’’’r4’’’
jmp L3B
L3D: al → r3’’’r2’’’ ; we have : [r5’’’r4’’’ r3’’’r2’’’] for L3: [x1x0] x [y3y2]
L4: - compute {[x3x2]x[y3y2]} by repetitive addition
mov al, 00h ; al is the working register
mov ah, y3y2 ; ah holds the multiplier
L4A: add al, x3x2
jc L4C
L4B: dec ah
jnz L4A
jmp L4D
L4C: r7’’’’r6’’’’ + C → r7’’’’r6’’’’
jmp L4B
L4D: al → r5’’’’r4’’’’ ; we have : [r7r6 r5’’’’r4’’’’] for L4: [x3x2] x [y3y2]
L5: - now add the partial results
mov ah, 00h ; ah-register will accumulate the carries
[r3’r2’ + r3’’r2’’] → al
jc L5A
jmp L5B
L5A: ah + 01h → ah
L5B: al + r3’’’r2’’’ → al
jc L5C
jmp L5D
L5C: ah + 01 → ah
L5D: al → r3r2 ; the value of ah-register will be added with r5r4 components
L6: - now add the three r5r4 components of L2, L3 and L4.
mov cl, 00h; ; cl-register will accumulate the carries
[r5’’r4’’ + ah ] → al
jc L6A
jmp L6B
L5A: cl + 01h → cl
L5B: al + r5’’’r4’’’’ → al
jc L6C
jmp L6D
L5C: cl + 01 → cl
L6D: al + r5’’’’r4’’’’ → al
Jc L6E
Jmp L6F
376 Chapter - 6

L6E: cl + 01h → cl
L6F: al → r5r4 ; the value of cl-register will be added with r7r6
L7: - now add r7r6 with cl-register
r7r6 + cl → r7r6
L8: - the multiplications is done-

6.6.C3 Testing the Multiplication Program of Section-6.6.C2 sing C and IBMPC

The following C-based program is a convenient way of testing the functionality of the
computation mechanism of Fig-6.13. Assume that the input numbers are: 1234h and ABCDh,
which are given directly in the program. After the execution of the program, he result will be
shown on the screen of the IBMPC.
#include <stdio.h>
#include <conio.h>
#include <string.h>
void bmult();
unsigned char r1r0=0, r3r2=0, r5r4=0, r7r6=0;
unsigned char r3r2_1=0, r3r2_2=0, r3r2_3=0;
unsigned char r5r4_2=0, r5r4_3=0, r5r4_4=0;
void main()
{

union buff {
unsigned long size;
unsigned char ch [4];
} y;

clrscr();

bmult();

y.ch[0] = r1r0;
y.ch[1] = r3r2;
y.ch[2] = r5r4;
y.ch[3] = r7r6;
printf("\n%lx ", (y.size));
getch();

}
void bmult()
{
// x3x2 = 12; x1x0 = 34h, y3y2 =AB; y1y0=CDh
BM: asm mov bl, 0x00
asm mov al, 0x00
asm mov ah, 0x34 // y1y0 ; y3y2y1y0=1234h
L1A: asm add al, 0xCD // x1x0; X3x2x1x0=ABCDh
asm jc L1C
Multiplication of Unsigned Binary Numbers by Repetitive Additions
377

L1B: asm dec ah

asm jnz L1A
asm jmp L1D
L1C: asm inc bl
asm jmp L1B
L1D: asm mov r1r0, al // r3r2_1, r1r0
asm mov r3r2_1, bl // 29A4h

asm mov bl, 0x00

asm mov al, 0x00
asm mov ah, 0x34 // y1y0; y3y2y1y0=1234
L2A: asm add al, 0xAB //x3x2 ; x3x2x1x0=ABCD
asm jc L2C
L2B: asm dec ah
asm jnz L2A
asm jmp L2D
L2C: asm inc bl
asm jmp L2B
L2D: asm mov r3r2_2, al // r5r4_2, r3r2_2
asm mov r5r4_2, bl // 22BCh

asm mov bl, 0x00

asm mov al, 0x00
asm mov ah, 0x12 // y3y2; y3y2y1y0 = 1234h
L3A: asm add al, 0xCD // x1x0l x3x2x1x0=ABCDh
asm jc L3C
L3B: asm dec ah
asm jnz L3A
asm jmp L3D
L3C: asm inc bl //r5r4_3
asm jmp L3B
L3D: asm mov r3r2_3, al // r5r4_3, r3r2_3
asm mov r5r4_3, bl // 0E6Ah

asm mov bl, 0x00

asm mov al, 0x00
asm mov ah, 0x12 // y3y2 ; y3y2y1y0=1234h
L4A: asm add al, 0xAB // x3x2; x3x2x1x0=ABCDh
asm jc L4C
L4B: asm dec ah
asm jnz L4A
asm jmp L4D
L4C: asm inc bl //r7r6
asm jmp L4B
L4D: asm mov r5r4_4, al // r7r6, r5r4_4
asm mov r7r6, bl //0C06h
L5: asm mov ah, 0x00
asm mov bl, r3r2_1
asm mov al, r3r2_2
asm add al, bl
378 Chapter - 6

asm jc L5A
asm jmp L5B
L5A: asm inc ah
L5B: asm mov bl, r3r2_3
asm add al, bl
asm jc L5C
asm jmp L5D
L5C: asm inc ah
L5D: asm mov r3r2, al // r3r2=5Ah;
L6: asm mov al, ah
asm mov ah, 0x00
asm mov bl, r5r4_2
asm add al, bl
asm jc L6A
asm jmp L6B
L6A: asm inc ah
L6B: asm mov bl, r5r4_3
asm add al, bl
asm jc L6C
asm jmp L6D
L6C: asm inc ah
L6D: asm mov bl, r5r4_4
asm add al, bl
asm jc L6E
asm jmp L6F
L6E: asm inc ah
L6F: asm mov r5r4, al
L7: asm add r7r6, ah
}
6.6.C4 Program Execution using MicroTalk-8086 Trainer

Example – 6.12 [multiplying two 16-bit unsigned numbers by full repetitive additions]
1. Assume the input numbers as: Multiplicand = 1234h
Multiplier = ABCDh
2. Expected Result: Product = 0C374FA4h
3. Let us use keyboard of the trainer and store the multiplicand and the multiplier in the
specified RAM locations of the input/output data structure of Fig-6.13.
3. Let us use keyboard of the trainer and store 00h to all four-memory locations of the data
structure holding the final result.
4. Write the complete 8086-assembly program for the above mixed codes of Section-6.6.C2 and
save as: …\mtk8086\P612.asm. Assemble it and download the program P612.abs.
5. Enter the MLPR (ABCDh) and the MLPC (1234h) into the indicated memory locations of the
data structure of Fig-6.13. Execute the down loaded program staring at location 01000h.
6. Open the memory locations that hold the final result. We must see as follows::
(0300F) = 0C
(0300E) = 37
(0300D) = 4F
(0300C) = A4
Multiplication of Unsigned Binary Numbers by Repetitive Additions 379

6.6.C5 16-bitx16-bit Multiplication by ‘8-bit mul Instruction’:

In this section, we shall multiply two unsigned 16-bit numbers by ‘partial repetitive addition’
method. There will be the use of the mul instruction. Let us assume that the input/output
variables are organized as per data structure of Fig-6.13, 6.14 and are repeated here.
Mixed Codes:
START: nop 519
x3x2 x1x0 : Multiplicand, MLPC
L1: al ← y1y0 y3y2 y1y0 : Multiplier, MLPR
al x BYTE PTR [3002h] ; (x1x0) x (y1y0), L1: r3'r2' r1'r0' = (x1x0) x (y1y0) : L1
al → r1’r0’ r5’’r4’’ r3’’r2’’ = (x3x2) x (y1y0) : L2
ah → r3’r2’ r5’’’r4’’’ r3'''r2''' = (x1x0) x (y3y2) : L3
L2: al ← y1y0 r7’’’’r6’’’’ r5’’’’r4’’’’ = (x3x2) x (y3y2) :L4

al x BYTE PTR [3003h] ; (x3x2) x (y1y0), L2: r7r6 r5r4 r3r2 r1r0

al → r3’’r2’’ Carry Carry

ah → r5’’r4’’
L3: al ←y3y2
al x BYTE PTR [3002h] ; (x1x0) x (y3y2), L3:
04FFF
al → r3’’’r2’’’
ah → r5’’’r4’’’
0300F r7r6
L4: al ← y3y2 0300E r5r4 Final
0300D r3r2 Result
al x BYTE PTR [3003h] ; (x3x2) x (y3y2), L4: 0300C r1r0
al → r5’’’’r4’’’’ 0300B r7’’’’r6’’’’
L4:
0300A r5’’’’r4’’’’
ah →r7’’’’r6’’’’ 03009 r5’’’r4’’’
Output DSM
L3:
03008 r3’’’r2’’’ Partial
L5: ; adding the partial results to get final result 03007 r5’’r4’’ Result
L2:
03006 r3’’r2’’
r1’r0’ → 0300Ch 03005 r3'r2' L1:
03004 r1'r0'
03003 x3x2
L5A: r3’r2’ + r3’’r2’’ + r3’’’r2’’’ → < cl, 0300h> 03002 x1x0 Multiplicand
Inputs
03001 y3y2
Multiplier
L5B: r5’’r4’’ + r5’’’r4’’’ + r5’’’’r4’’’’ + cl → <ch, 0300Eh> 03000 y1y0
02FFF

L5C: r7’’’’r6’’’’ + ch → 0300Fh 01000 CSM

L6: halt 00000

559b

6.6.C6 16-bitx16-bit Multiplication by ‘Double Precision mul Instruction’

The multiplications codes of Section-6.6.C5, 6.6.C6 can be replaced by the following assembly
codes where 16-bit by 16-bit multiplications are carried out using the mul instructions.
START: nop
mov ax, 0000h
mov ds, ax
mov bx, 3000h
L1: mov ax, WORD PTR [bx+02h] ; 16-bit multiplicand
mul WORD PTR ds:[bx] ; memory resident multiplier ; result in <dx, ax>
L2: mov WORD PTR ds:[bx+0Ch], ax ; lower 16-bit of result
mov WORD PTR ds:[bx+0Eh], dx ; upper 16-bit of the result
L3: hlt
380 Chapter - 6

6.6 (d) Multiplication of Two Unsigned Binary Numbers by Fundamental Principles

6.6.D1 Introduction
In the absence of mul instruction, how would we multiply two unsigned numbers? We could use
the repetitive additions Process method (RAP). In the absence of RAP method, what technique is
there to multiply two numbers? It is the ‘Paper and Pencil Process (triple P Process or PPP)’
method. The PPP dictates us to employ our basic instincts to carry out multiplication process. The
author wishes to term it as the ‘Fundamental Principles’ of carrying out multiplication. There are
already mul and RAP methods for multiplication, then why are we interested to study the PPP
method? The PPP method is ‘Simple and Elementary (Basic)’. It is the original approach that a
human being adopts to multiply two numbers in a machine-free environment. The mul and the
RAP methods are artificial and evolved in a machine-based environment to perform
multiplication process using machines (computers). The mul and RAP are, of course, designed
based on PPP method, but they hide the ‘inner working principles’ of the multiplication process.
PPP method is the only method that will always survive even at the inactivity/destruction of all
machines because it is an integral part of the human being. It is a natural desire that we get
familiar with the progression of human thoughts and preserve them in recorded form.
6.6.D2 Multiplication of Two 8-Bit Unsigned Numbers by Shit-Left-Add (SLA) Method
The following ‘Binary Multiplication Table (BMT)’ is the basis of the SLA method of
multiplication:
0 0 1 1
x0 x1 x0 x1
______ ______ ______ ________
0 0 0 1

Let us use the above BMT table and multiply two unsigned binary numbers: 32h and 27h.

Figure-6.15: Explaining the PPP Method for Multiplying Two Numbers by SLA Technique
In Fig-6.15, why have we placed the partial result of MLPR1-bit to the 1-position left of the partial
result of the MLPR0-bit? It is because the partial result of MLPR1-bit weighs two times (it is ten
times for the decimal system) of the partial result of MLPR0-bit. For the same reason, the partial
results of the remaining bits are placed to the 1-position left of their previous partial results. We
also notice that the 0-valued bits of the MLPR carry 00 partial results. 1-valued bit carry partial
results equal to the MLPC but shifted to the left by 1-bit position.
Multiplication of Unsigned Binary Numbers by Fundamental Principles 381

Example – 6.13 [multiplication of two 8-bit unsigned numbers by Shift-Left-Add (SLA) method]
The Computation Model: In Fig-6.15, we have placed the partial results of the bits of the MLPR to the 1-
position left of the previous partial results. This means that we have created the partial results of the bits of
the MLPR by shifting the MLPC to the left by 1-bit position. After adding all the partial results, we came up
with a 16-bit result. This makes sense because of the fact that the multiplication of two 8-bit numbers
produces 16-bit result. In Fig-6.15, the partial results are individually 8-bits. But, because we are placing
them to the left by 1-bit position, the partial result of MLPR7-bit occupies the position b7 – b14. We also
notice that we have created the partial results of the bits of the MLPR by shifting the MLPC to the left by 1-
bit position. This feature of the SLA method suggests us to use 16-bit register model for computation
purposes. The SLA method suffers from the drawback of consuming more memory space due to performing
16-bit additions of the successive partial results though the partial results themselves are 8-bits. The Shift-
Right-Add (SRA) method overcomes the excessive memory space consumption aspects.

Data Structure
04FFF

Output
04001 RUB, 07h
04000 RLB, 9Eh DSM
03FFF

Input
03011 MLPR, 27h
03010 MLPC, 32h
1533
Figure-6.16: Data Structure and Computation Model for SLA Method for Multiplying Two 8-Bit Numbers
Flow Chart:
The flow chart is the direct translation of the manual computation
performed in Fig-6.15. In Fig-6.15, we observe that the 0-valued bits
of the MLPR contribute 00 partial results. The 1-valued bits of the
MLPR have partial results exactly equal to the MLPC but shifted to
the left by n-bit position, where n corresponds to the bit position of
the MLPR. Thus for:
i. MLPR0-bit, we have a partial result, which is equal to the 0-
position left-shifted MLPC (0011 0010).
ii. MLPR1-bit, we have a partial result, which is equal to the 1-
position left-shifted MLPC (0110 0100).
…….………………………………………………………….
iii. MLPR7-bit, we have a partial result, which is equal to the 7-
position left-shifted MLPC (0000 0000).
At L2, the program checks the MLPR0-bit for LH and if so, it adds
0-position left-shifted MLPC with IPR and leaves the result in the
IPR. The program then shifts the MLPC to the left by 1-position so
that it can be added with IPR at the next catch of the MLPRX-bit.
In case, the MLPR0-bit (or any other bit) appears to be 0, the
program cleverly avoids adding the 00h-valued partial result with
the IPR. But, it maintains the computation structure of Fig-6.15 by
left-shifting the MLPC. It is achieved by branching the program
control to Label L3A.
Figure-6.17: Flow Chart- Algorithm of SLA Method for Multiplying Two Unsigned 8-Bit Binary Numbers
382 Chapter - 6

Assembly Codes:
START: nop
L1: ;--- initialization -------
mov bx, 3000h ; offset pointer
mov al, BYTE PTR [bx+10h] ; MLPC
mov ah, 00h ;
mov cl, BYTE PTR [bx+11h] ; MLPR
mov ch, 08h ; MLPR size
mov dx, 0000h ; IPR (Initial Partial Result)
;--------------------------
L2: rcr cl, 01h ; catch 1st, 2nd... bit
jnc L3A ; ignoring 0s of MLPR
;--------------------------
L3: add dl, al
adc dh, ah ; updating IPR
L3A: shl ax, 01h ; MLPC shifting to left
L4: dec ch
jnz L2
;--------------------------
L5: mov WORD PTR [bx+1000h], dx ; result in locations <04001h, 04000h>
call HEXRESDISP ; show result at DP0-DP3 positions of trainer.
call BCDRESDISP ; show BCD at DP10-DP15

L6: hlt
;-------------------------------
HEXRESDISP:
SR1: mov di, 3000h
mov ax, WORD PTR [bx+1000h] ; getting the H4x result
mov bx, 0400h
mov WORD PTR ds:[bx+0120h], ax
;---------------------------------
mov si, 0121h ; beginning addr of HEX result and down
mov di, 0100h ; begin address of CC table and up
mov ch, 02h ; 2 byte HEX to convert
call HEX2CC
;---------------------------------
SR2: mov ch, 09h ; number of cc bytes to transfer
mov cl, 90h ; DP0 position auto index and up
mov di, 0100h ; pointing to CC table
mov bx, 0400h; BYTE PTR [bx+0104h], 00h ; blank
mov WORD PTR [bx+0105h], 0000h ; to blank
mov WORD PTR [bx+0107h], 0000h
mov BYTE PTR [bx+0104h], 00h
call CCXDRAM
ret
;====================================
HEX2CC: mov al, BYTE PTR [bx+si] ; al = 09
and al, 0F0h ; al = 00 , X0 format
mov ah, 0FEh
mov bp, ax
mov ax, 0F000h ;using ROM-based Lookup table for conversion
mov es, ax
mov al, BYTE PTR es:[bp+00h] ; F0000 + FE90 = FFE90
mov BYTE PTR [bx+di], al
mov al, BYTE PTR [bx+si] ; al = 09
mov cl, 04h
rol al, cl
and al, 0F0h ; al = 00
mov ah, 0FEh
mov bp, ax
mov ax, 0F000h
mov es, ax
mov al, BYTE PTR es:[bp+00h] ; use LUT-3 (Ref Manual of MicoTalk-8086)
inc di
mov BYTE PTR [bx+di], al
;---------------------------------
dec ch
jnz FRW1
ret ; returning to MLP
Multiplication of Unsigned Binary Numbers by Fundamental Principles
383

FRW1: dec si
inc di
jmp HEX2CC
;=========================================
CCXDRAM:
mov al, cl
mov dx, 0002h
out dx, al
mov dx, 0000h
AGNCCX: mov al, BYTE PTR [bx+di]
out dx, al
dec ch
jnz FRW2
ret ; returning to MLP
FRW2: inc di
jmp AGNCCX
;=================================
BCDRESDISP:
mov dx, 0000h ; BIN2BCD
mov ah, 00h
mov cx, WORD PTR [bx+0120h]
mov di, 0010h
AGNCON: rcl cx, 01h
call EVADH ; BCD (HEX) to BCD by Horner Rule
dec di
jnz FRW3
jmp SHOW ; show BCD result at DP10 - DP15
FRW3: jmp AGNCON
;-----------------------------
EVADH: mov al, dl ; Evaluate to decimal value by Horner Rule
adc al, al
daa
mov dl, al
mov al, dh
adc al, al
daa
mov dh, al
mov al, ah
adc al, al
daa
mov ah, al
ret
;----------------------------
SHOW: mov WORD PTR ds:[bx+0120h], dx
mov BYTE PTR ds:[bx+0122h], ah
;---------------------------------
mov si, 0122h ; pointing beginning address of Hex table
mov di, 010Ah ; pointing beginning address of CC-table
mov ch, 03h ; 3 byte HEX to convert to cc codes
call HEX2CC
;---------------------------------
mov ch, 06h ; number of bytes to transfer
mov cl, 9Ah ; DP0 position auto index
mov di, 010Ah ; pointing to CC table
call CCXDRAM
ret
;--------------------------------------------------------
Program Execution:
1. Let us open the file …\mtk8086\P613.asm and look into its structure, which should be same as above.
2. Down load the file ….\mtk8086\P613.abs into the MicroTalk-8086 trainer.
3. Enter MLPC (32h) and MLPR (27h) via memory locations as indicated in the data structure of Fig-6.16.
4. Execute the down loaded program stating at location 01000h.
5. The DP0 – DP1 positions of the display unit of the trainer will show the result in Hex format.
6. The DP10 – DP15 positions of the trainer will show the result in decimal format.
7. Check the functionality of the program for any other 8-bit values for the MLPC and MLPR.
384 Chapter - 6

6.6.D3 Multiplication of Two 8-Bit Unsigned Numbers by Shit-Right-Add (SRA) Method

Introduction: In the multiplication process of Section-6.6.D2, we have computed the partial
results for all the individual bits of the MLPR. These partial results are depicted in Fig-6.15. We
may designate these partial results as:
i. IPR0 = MLPC x MLPR0 (Initial Partial Result due to Bit-0 of MLPR)
ii. IPR1
………….
viii. IPR7 = MLPC x MLPR7 (Initial Partial Result due to Bit-7 of MLPR)

The next step was to add these partial results together to get the final result. While adding these
partial results together, we took great care to ensure that the partial results are properly placed
with respect to each other. This is to say that:
i. IPR1 must be left-shifted by 1-position and then add it with IPR0. Leave the result in
IPR0.
ii. IPR2 must be left-shifted by 2-position and then add it with previously accumulated
partial result (the IPR0 of Step-i).
iii. And so on…………………………………………………………………………………….
Now, the observation stands as:
i. Compute partial results for the individual bits of the MLPR.
ii. Position a partial result (Fig-6.15) according to its positional weight.
iii. And then add these partial results together to get the final result.
In Fig-6.15 of SLA method, we positioned the partial results by left-shifting the MLPC. This
arrangement required performing 16-bit additions on the partial results of 8-bits values. It was
due to the fact that the IPR7 occupied the space of b7 – b14 positions.
The 16-bit additions on the partial results of the SLA method can be avoided by positioning the
partial results in the following way. This way is known as SRA (Shift-Right-Add) method and
performs 8-bit additions on the partial results of 8-bit values.
i. Compute IPR0 – IPR7 for all the bits of the MLPR.
ii. Right Shift the IPR0 by 1-position.
Place IPR1 below the IPR0 by aligning it with the left-most bit of IPR0.
(This arrangement has ensured that the IPR1 is placed at the correct place according to its
positional weight).
Now perform an 8-bit addition between IPR1 and IPR0. Leave the result in IPR0.
iii. Right Shift the previously computed partial-result (the IPR0) by 1-position.
Place IPR2 below the IPR0 by aligning it with the left-most bit of IPR0.
(This arrangement has ensured that the IPR1 is placed at the correct place according to its
positional weight).
Now perform an 8-bit addition between IPR2 and IPR0. Leave the result in IPR0.
iv. Repeat all the actions of Step-ii for the remaining partial results, IPR2 – IPR7.

In the SRA method, the 8-bit additions on the 8-bit partial results have been made possible by
right-shifting the partial results and not left-shifting the MLPC of the SLA method.
Multiplication of Unsigned Binary Numbers by Fundamental Principles 385

The Partial Results Matrix of SRA Method:

Figure-6.18: Explaining the PPP Method for Multiplying Two Unsigned Binary Numbers by SRA Technique

Example – 6.14 [multiplication of two 8-bit unsigned binary numbers by Shift-Right-Add (SRA) method]
The Computation Model: The computation matrix of Fig-6.18 provides us the following clues, based on
which we might be able to create a ‘Register Based Computation Model’.
i. An initial partial result (IPR) of 00h may be kept in the upper part of a 16-bit register (say it is
dx-register). Because, we are shifting the IPR to the right for each partial result corresponding
to each bit of the MLPR, the LS-bit of the IPR must propagate through the lower part (the dl-
register) of the 16-bit register.
ii. At the end of computation, one more right-shift must be carried out to align the final result
with the LS-bit of the dx-register.

Data Structure
04FFF

Output
04001 RUB, 07h
04000 RLB, 9Eh DSM
03FFF

Input
03011 MLPR, 27h
03010 MLPC, 32h
1533
Figure-6.19: Data Structure and Computational Model for SRA Method to Multiply Two 8-Bit Numbers
386 Chapter - 6

START: nop

L1: ;--- initialization -------

mov bx, 3000h ; offset pointer
mov al, BYTE PTR [bx+10h] ; MLPC
mov cl, BYTE PTR [bx+11h] ; MLPR
mov ch, 08h ; MLPR size
mov dx, 0000h ; IPR (Initial Partial Result)
;--------------------------
L2: rcr cl, 01h ; catch 1st, 2nd... bit
jnc L3A ; ignoring 0s of MLPR
;--------------------------
L3: add dh, al ; updatinf IPR
L3A: rcr dx, 01h ; IPR shifting to right why not shr
L4: dec ch
jnz L2
;--------------------------
L5: mov WORD PTR [bx+1000h], dx ; result in memory at <04001, 04000>
call HEXRESDISP ; Hex esult at positions: DP0 - DP3
call BCDRESDISP ; BCD result at positions: DP10 - DP15
L6: hlt
;--------------------------------------------------------------------
6.7 (a) Division of Two Unsigned Binary Numbers using Formula
6.7.A1 Dividing a 16-bit unsigned number by an unsigned 8-bit number by Formula
The 8086 has a division instruction known as div, which works in the following ways:
i. The 16-bit dividend must be in the ax-register.
ii. The 8-bit divisor can reside in an 8-bit GPR-register or in an external memory location.
The memory location can be accessed in one of 24 possible addressing modes [P-113].
iii. After the division, the al-register will contain the 8-bit result (quotient) and the ah-
register will hold the 8-bit remainder.
iv. In the case where the dividend is not exactly divided (means zero remainder) by the
divisor, the quotient is left as it is (means truncated). The CPU doesn’t round the
quotient (means making the next higher value). It is the responsibility of the
programmer to do so by checking that remainder>(divisor/2).
v. If an attempt is made to divide something by 0 or the quotient is too large (>FF) that it
doesn’t get fit into the al-register, the 8086 will automatically be interrupted and will
jump to execute an ISUR that corresponds to interrupt type code of 00h.
vi. All flags of the 086 remain undefined after the division operation.
Instruction Syntaxes:
a. mov ax, 1234h ; immediate addressing mode
mov bl, 34h ; 8-bit divisor
div bl ; result in <ah,al> = <remainder, quotient>
b. mov ax, WORD PTR [bx+10h] ; indirect memory reference addressing mode
div BYTE PTR [bx+12h] ; result in <ah, al>

Example – 6.15 [dividing an unsigned 16-bit number by an unsigned 8-bit number (FEFF/FF = FF – FE)]
1. Dividend : 00FFh (0255) Divisor : 12h (18)
2. Result : Quotient : 0Eh (14) Remainder : 03h (03)
4. Down load …\mtk8086\P615.abs into the MicroTalk-8086 trainer starting at location 01000h.
5. Enter the dividend and divisor via memory locations <03011h, 03010h> and 03012h of the trainer.
6. Execute the program. The DP0 – DP1 positions of the display show the quotient in Hex format and the
DP3 – DP4 positions of the display show the remainder in BCD format.
8. Check that the program works well for the dividend = FEFFh and divisor = FFh.
9. Check that the program doesn’t work for the dividend = FFFFh and the divisor = FFh. Why?
Division of Unsigned Numbers by Formula 387

6.7.A1 Dividing a 32-bit unsigned number by a 16-bit unsigned number by Formula

In this division process,
i. The 32-bit dividend is kept in the <dx, ax> register,
ii. The 16-bit divisor is kept in a 16-bit GPR or into two consecutive memory locations.
iii. After the multiplication, the ax-register will contain the 16-bit result (quotient) and the
dx-register will contain the 16-bit remainder.
iv. If the quotient is not the integral multiples of the divisor, then the quotient is truncated
to the nearest lower value. It is the task of the programmer to round the quotient.
v. An attempt to divide something by 0 or the quotient is too large (>FFFF) to get fit into
the ax-register; the 8086 will automatically execute an ISUR for int 00h.
Instruction Syntaxes:
a. mov ax, 1234h ; lower 16-bit of dividend , direct addressing
mov dx, 5678h ; upper 16-bit of dividend
mov bx, 789Ah ; 16-bit divisor
div bx ; result = <remainder, quotient> = <dx, ax>

b. mov ax, WORD PTR [bx+10h] ; indirect memory reference addressing mode
mov dx, BYTE PTR [bx+12h] ;
div WORD PTR [bx+14h] ;16-bit divisor is taken from memory locations

Example – 6.16
[dividing an unsigned 32-bit number by an unsigned 16-bit number (FFFE00FF/FFFF = FFFF – 00FE)]
1. Dividend : FFFE00FFh (4294836479)
Divisor : FFFFh (65535)
2. Result :
Quotient : FFFF (65535) Remainder : 00FE (0254)
3. Down load …\mtk8086\P616.abs into the MicroTalk-8086 trainer starting at location 01000h.
4. Enter the dividend via memory locations <03013h - 03010h> of the trainer.
5. Enter the divisor via memory location <03015h, 03014h> of the trainer.
6. Execute the program. The DP0 – DP3 positions of the display show the quotient in Hex format and the
DP12 – DP15 positions of the display show the remainder in Hex format.
7. Check that the program works well for other dividends and divisors as per following table
Sn. Dividend Divisor Quotient <ax) Remainder <dx>
<03013 – 03010> <03015 – 03014> DP0 – DP3 DP12 – DP15

1 000000FFh 00FFh 0001h 0000h

2 F000F000h FFFEh F002h D004h
3 FFF00000h FFFFh FFF0h FFF0h

8. Check that the program doesn’t work for the dividend = FFFFFFFFh and the divisor = FFFFh. Why?

Example – 6.17 [dividing an unsigned 10-digit BCD number by an unsigned 5-digit BCD number.]
Write and execute 8086 ASM codes to divide the BCD number 4026593280 by the 5-digit divisor 65534. Show
the quotient at DP0-DP5 and the remainder at DP10-P15 positions of the display unit of the MicroTalk-8086
Trainer.
Solution Hints: - read the input BCD data via memory locations – convert BCD into BINay – use div
instruction–convert BINay result into BCD– show the result (quotient and remainder) on the display device-
 Chapter - 6
388

6.7 (b) Division of Two Signed Binary Numbers by Formula

6.7.B1 Dividing a signed positive 16-bit dividend by a signed negative 8-bit divisor
In the functioning of the idiv (integer division) instruction, we observe that:
i. The dividend is always a signed positive 16-bit number. The range is from 00000 to
32767 and must be represented using 2’s complement form. Thus, the allowable range
in TC is: 0000h – 7FFFh. However, it must satisfy the criterion of Step-vii.
ii. The divisor is always a signed negative 8-bit number. The range is from –128 to +127
and must be represented using 2’s complement form. Thus, the allowable range in TC
is: 80h – 7Fh. However, it must satisfy the criterion of Step-vii.
iii. The dividend must be given using the ax-register.
iv. The divisor can be given via an 8-bit GPR or a memory location.
iii. The idiv (integer division) instruction is used to carry out the division process.
iv. The result (truncated quotient) enters into the al-register and the remainder enters into
the ah-register.
v. The sign of the remainder will follow the sign of the dividend.
vi. After the division process, all flag bits of the 8086 remain undefined.
vii. If the idiv instruction is involved with one of the following happenings, the 8086 will
automatically be interrupted and it will execute the user ISUR due to int 00h.
a. An attempt is made to divide a dividend by zero.
b. The quotient becomes greater that +127 (7Fh).
c. The quotient becomes less than –127 (81h).

Example – 6.18 [dividing a signed positive 16-bit number by a signed negative 8-bit number]
1. Dividend : + 6850 (1AC2h) via memory locations <03011 – 03010> of MicroTalk-8086
2. Divisor : - 77 (B3h) via memory location <03012>
3. Result :
Quotient : - 88 (A8h) at DP0-DP1 positions
Remainder : + 74 (4Ah) at DP3-DP4 positions
4. Download the program ….\mtk8086\P618.abs into the MicroTalk-8086 trainer starting at 01000h.
5. Manually convert the decimal values of the dividend and the divisor into 2’s complement codes.
6. Enter the 2’s formatted dividend and divisor into the memory locations as indicated above.
7. Execute the program starting at 01000h.
8. The DP0-DP1 positions of the display unit of the trainer show the quotient in 2’s complement format.
9. The DP3-DP4 positions of the trainer show the remainder as signed positive number.
10. Working Principles of idiv Instruction:
a. Before the actual division, the CPU removes the –ve sign of the divisor and extracts its unsigned
value.
b. The normal unsigned division is carried on the between the dividend and the divisor.
c. The quotient is taken as a negative number and its 2’s complement is extracted.
d. The remainder follows the sign of the dividend.
e. The al-register contains the quotient in 2’s complement form.
f. The ah-register contains the remainder as an unsigned number.
11. Remarks:
a. It is the responsibility of the programmer to extract the –ve BCD value for the quotient in the
following way:
- Subtract the quotient from 00h and then convert the result into BCD,
b. (+6850)/(-77) and (-6850)/(+77) are not equivalent from the viewpoint of the idiv instruction. This
proposition can be easily verified using the Example-6.18.
Division of Signed Binary Numbers by Formula 389

6.7.B2 Dividing a signed positive 32-bit number by a signed negative 16-bit number
The functioning of the idiv (integer division) instruction for 32-bit signed positive number are
related with the following facts:
i. The dividend is always a 32-bit signed positive number. This means that the dividend
can only be represented as: 00000000h – 7FFFFFFFh. The range is from 0000000000 to
2147483647 and must be represented using 2’s complement form.
ii. The divisor is always a 16-bit signed negative number with range from 8000h – 7FFFh
(- 32768 to +32767).
iii. The dividend must be given using the <dx, ax> register pair.
iv. The divisor can be given via a 16-bit GPR or by two consecutive memory locations.
iii. The idiv (integer division) instruction is used to carry out the signed division process.
iv. The 16-bit result (truncated quotient) enters into the ax-register and the 16-bit
remainder enters into the dx -register.
v. The sign of the remainder will follow the sign of the dividend.
vi. After the division process, all flag bits of the 8086 remain undefined.
vii. If the idiv instruction is involved with one of the following happenings, the 8086 will
automatically be interrupted and it will execute the user ISUR due to int 00h.
a. An attempt is made to divide a dividend by zero.
d. The quotient becomes greater that +32767 (7FFFh).
e. The quotient becomes less than – 32767 (8001h)

Example – 6.19 [dividing a signed positive 32-bit dividend by a signed negative 16-bit number]
1. Dividend : + 0581176750 (22A40DAEh) via locations <03013 – 03010> of MicroTalk-8086
2. Divisor : - 17745 (BAAFh) via location <03015 - 03014>
3. Result :
Quotient : - 32751 (8011h) at DP0-DP3 positions of the trainer
Remainder : + 10255 (280Fh) at DP12-DP15 positions of the trainer.
4. Download the program ….\mtk8086\P619.abs into the MicroTalk-8086 trainer starting at 01000h.
5. Manually convert the decimal values of the dividend and the divisor into 2’s complement codes.
6. Enter the 2’s formatted dividend and divisor into the memory locations as indicated above.
7. Execute the program starting at 01000h.
8. The DP0-DP3 positions of the display unit of the trainer show the quotient in 2’s complement format.
9. The DP12-DP15 positions of the trainer show the remainder as signed positive number.

6.7 (c) Division of Two Unsigned Binary Numbers by First Principles (LSS Method)
6.7.C1 Division by Left-shift Subtraction (LSS) Method by ‘Paper and Pencil Process’
A social worker has a sum of Tk 34/- in the form of one-taka notes. She wishes to distribute it
among seven orphans. How does she distribute it? She might adopt the following ways:
i. Assume that the social worker doesn’t know any arithmetic at all:
At the 1st round, she gives one-taka note to every recipient.
At the 2nd round, she gives another one-taka note to every recipient.
At the 3rd round, she gives another one-taka note to the recipients.
At the 4th round, she gives another one-taka note to the recipients.
At the 5th round, she starts giving (because she has few more notes in her hand) one-taka note to
the recipients. But, after giving notes to four recipients, the money is exhausted. She takes back
the notes and keeps as a remainder (Tk 6/-) with her.
 Chapter - 6
390

ii. Assume that the social worker knows the arithmetic of Table-6.1 [Multiplication Table P-359]
She will apply the rules of multiplication of Table-6.1 [P-359] and will give Tk 4/- to each orphan
straightforward.
She will notice that a sum of Tk 6/- is left to her as a remainder.

In the use of the multiplication table, the social worker, actually subtracted the figure 7 (equal to
the number of orphans) from the figure 34 (equal to the sum to be distributed) for as many times
as it can be. She found that the figure 7 could be subtracted only for 4 times and accordingly she
donated Tk 4/- to each orphan. This is to say that the social worker divided the sum of Tk 34/-
by the figure 7 and found that the quotient is 4 and the remainder is 6.

A human being can remember a multiplication table like Table-6.1 by virtue of the faculty of her
natural biological memory. A human being has the instinct to repetitively use a basic small-sized
multiplication table to carry out division on very large numbers. On the other hand, a computer
can be taught to memorize a limited-sized multiplication table, but it finds great difficulties in
applying the table repetitively for division process on large numbers. Therefore, we need to
search for a routine, which will successfully perform division process between numbers without
the help of a multiplication table.

In this section, we wish develop an algorithm for performing division process based on the
principles of ‘Left-Shift-Subtraction (LSS)’ method [18, P-284]. The actions involved in this
method are:
i. Assume 8-bit unsigned dividend of: 1010 0111 (+167) and unsigned 8-bit divisor of: 0000 0110 (6).

ii. Assume initial partial quotient as 0000 0000 and initial partial remainder as 0000 0000.

iii. Place the divisor underneath the dividend. We get -

1010 0111 : dividend
0000 0110 : divisor

iv. Align the divisor with the MS-bit of the dividend. We get -
1010 0111 : dividend
0000 0110 : divisor

v. Let us see if the divisor could be subtracted from the MS-bit of the dividend. To do so, we
arrange the Remainder, Dividend, Quotient and Divisor in the following way.
Remainder Dividend Quotient
0000 0000 1010 0111 0000 0000
0000 0110

vi. To carry out the above subtraction action let us, left-shift the dividend through the Remainder
bits. We get -
Remainder Dividend Quotient
0000 0001 010 0111 0000 0000
- 0000 0110
Division of Unsigned Binary Numbers by First Principles
391

The divisor cannot be subtracted from the dividend because it is greater than the dividend. So,
we insert 0 (marked as bold) as the MS-bit of the quotient. We get -
Remainder Dividend Quotient
0000 0001 010 0111 0000 0000

vii. To carry out the next subtraction action let us, left-shift the dividend through the Remainder bits.
We get -
Remainder Dividend Quotient
0000 0010 10 0111 0000 0000
- 0000 0110

The divisor cannot be subtracted from the dividend because it is greater than the dividend. So,
we insert 0 (marked as bold) as the MS-bit of the quotient. We get -
Remainder Dividend Quotient
0000 0010 10 0111 0000 0000

viii. To carry out the next subtraction action let us, left-shift the dividend through the Remainder bits.
We get -
Remainder Dividend Quotient
0000 0101 0 0111 0000 0000
- 0000 0110

The divisor cannot be subtracted from the dividend because it is greater than the dividend. So,
we insert 0 (marked as bold) as the MS-bit of the quotient. We get -
Remainder Dividend Quotient
0000 0101 0 0111 0000 0000

ix. To carry out the next subtraction action let us, left-shift the dividend through the Remainder bits.
We get -
Remainder Dividend Quotient
0000 1010 0111 0000 0000
- 0000 0110
0000 0100

The divisor can be subtracted from the dividend because it is smaller than the dividend. So, we
insert 1 (marked as bold) as the MS-bit of the quotient. Now, we have the following Remainder,
Dividend and Quotient structure:
Remainder Dividend Quotient
0000 0100 0111 0000 0001

x. To carry out the next subtraction action let us, left-shift the dividend through the Remainder bits.
We get -
Remainder Dividend Quotient
0000 1000 111 0000 0001
- 0000 0110
0000 0010
 Chapter - 6
392

The divisor can be subtracted from the dividend because it is greater than the dividend. So, we
insert 1 (marked as bold) as the MS-bit of the quotient. Now, we have the following Remainder,
Dividend and Quotient structure:
Remainder Dividend Quotient
0000 0010 111 0000 0011
xi. To carry out the next subtraction action let us, left-shift the dividend through the Remainder bits.
We get -
Remainder Dividend Quotient
0000 0101 11 0000 0011
- 0000 0110

The divisor cannot be subtracted from the dividend because it is greater than the dividend. So,
we insert 0 (marked as bold) as the MS-bit of the quotient. We get -

Remainder Dividend Quotient

0000 0101 11 0000 0110

xii. To carry out the next subtraction action let us, left-shift the dividend through the Remainder bits.
We get -
Remainder Dividend Quotient
0000 1011 1 0000 0110
- 0000 0110
0000 0101

The divisor can be subtracted from the dividend because it is greater than the dividend. So, we
insert 1 (marked as bold) as the MS-bit of the quotient. Now, we have the following Remainder,
Dividend and Quotient structure:
Remainder Dividend Quotient
0000 0101 1 0000 1101

xiii. To carry out the next subtraction action let us, left-shift the dividend through the Remainder bits.
We get -
Remainder Dividend Quotient
0000 1011 0000 1101
- 0000 0110
0000 0101

The divisor can be subtracted from the dividend because it is greater than the dividend. So, we
insert 1 (marked as bold) as the MS-bit of the quotient. Now, we have the following Remainder,
Dividend and Quotient structure:
Remainder Dividend Quotient
0000 0101 0001 1011

Now, there are no more bits left in the dividend. Therefore, this is the end of the division process.
The final quotient and the remainder are

Quotient : 0001 1011 (1Bh = 27)

Remainder : 0000 0101 (05h = 5)
Division of Unsigned Binary Numbers by First Principles
393

6.7.C2 Flow Chart for the Division Process of LSS Method

Data Structure and Computation Model:

Data Structure
04FFF

Output
04001 remainder
04000 quotient DSM
03FFF

Input
03011 Dividend
03010 Divisor
1537
Figure-6.20: Data Structure and Computational Model for LSS Method for Dividing 8-Bit Binary Numbers
Assembly Codes: Flow Chart:
START: nop

L1: ;--- initialization -------

Mov di, 3000h ; offset pointer

mov ah, 00h ; initial remainder

mov cl, 08h ; size of dividend
mov dl, 00h ; initial Quotient

mov ch, divisor

mov al, dividen

L2: shl ax, 01h

cmp ah, ch
js L7

L3: sub ah, ch

stc
rcl dl, 01h

L4: dec cl
jnz L2

L5: mov al, dl

call RESDISP

L6: hlt

L7: clc
rcl dl, 01h
jmp L4

Figure – 6.21: Flow Chart for Division by LSS Method

Example – 6.20 [dividing an unsigned 8-bit dividend by an unsigned 8-bit divisor by LSS method]
1. Dividend : + 255 (FFh) via memory locations <03011> of MicroTalk-8086
2. Divisor : + 6 (06h) via memory location <03010>
3. Result :
Quotient : +42 (2Ah) at DP0-DP1 positions of the trainer
Remainder : + 03 (03h) at DP3-DP4 positions of the trainer.
4. Download the program ….\mtk8086\P620.abs and execute. We must be able to see correct result.
 Chapter - 6
394

6.7 (d) Division of Two Unsigned Binary Numbers by ‘Count & Subtraction’ Method
This is, in fact, a ‘shift-right-subtraction (SRS)’ method of division. In this method, a dividend of
any size can be divided by an 8-bit divisor. The author developed this technique in connection
with the design of the ‘89S8252-Based Prepaid Energy Meter’, where the consumed ‘kwhr
quanta’ had to be extracted by dividing a large number by an 8-bit divisor. The author feels
pleasure to call it ‘GCR-Method (Count and Residual Method for Division and its credit goes to
Golam Mostafa)’.

Introduction: We wish to use an 8086 microprocessor to divide a 16-bit unsigned number (range:
0000H-FFFFH) by an 8-bit unsigned number (range: 00H – FFH). Let us assume that, we have the
following data:
(i) Divisor : y1y0 stored at location 03010h of the data structure shown right
(ii) Dividend : x3x2x1x0 located at memory locations <03012 – 03011>.
(iii) Remainder : will be stored by the program at memory location 03013h.
(iv) Quotient : as counts C2 for the quantity ‘x3 x2 0 0’ and stored at 03014h.
: as counts C1 for the quantity ‘x1 0’ and stored at 03015h.
: as counts C0 for the quantity ‘x0' and stored at location 03016h.

Philosophy of Division: Our aim is to compute:

X3x2x1x0
Y1y0
Dividing the number x3x2x1x0 by ‘y1y0’ means finding ‘how many times’ the number y1 y0
could be ‘deducted’ from ‘x3 x2 x1 x0’. Here, the highlighted message ‘how many times’ obviously
refers to ‘Counts’ and the highlighted message ‘deduction’ obviously refers to ‘Subtraction’. The
author wishes to apply these two clues (count and subtraction) to solve the division problem
using Intel’s 8086 microprocessors.

The author understands that some of the readers will see this ‘Counting & Subtraction (CAS)’
method as an inefficient (more time consuming in the execution of lengthy program) way for the
solution of the division problem. But, I also understand that the rest of the readers (may be only
0.000001%) must be saying that the so-called ‘efficient methods’ are the ‘synthesized methods’,
which could have never been conceived without the ‘crystal clear understanding’ of the CAS
method. Before the advent of the computing machineries, the people still divided objects among
them by following the most natural method, the CAS method. The CAS method is the simplest
method because it is natural but is not understood by many owing to their inability in slowing
down the ‘speed of the clock (the biological clock)’ with which they process thoughts. The
philosophers, the scientists and the poets say that they crank down their ‘biological clocks’ to a
speed of 1day for 1sec in order to read messages from the book of ‘Nature’.
The division process is opposite to the multiplication process. The multiplication process starts
from the right. Therefore, the CAS method for the division process would start from the left of
the dividend. The division process can still be performed started from the right of the dividend if
the processor supports DIV instruction (see SURY of 8751). Let us take the example of a decimal
number and try to understand the working principles of the CAS method. Once the CAS method
is well understood, it could easily be extended for the hexadecimal number.
(i) The dividend is : x3x2x1x0 = 1217 and the divisor is y1y0 =11.
(ii) The expected result is: Quotient is : 110 (C2=01), (C1=01), (C0=00) and the Remainder is: 7
Division Unsigned Binary Numbers by Count & Subtraction Method
395

CAS Procedures of Division:

1. We take the number x3x2 (12) and see how many times the y1y10 (11) could be subtracted. To
remove y1y0 from x3x2, the x3x2 must be greater than y1y0 or equal to y1y0.
2. In the given example, 12 > 11. So, 11 can be subtracted for only ‘one time’ from 12. The
highlighted messages ‘one time’ is the ‘count’ and let us save it at C2 of the data structure.
3. There is a remainder of ‘1’ from the quantity x3x2. This has to be borrowed down to the next
digit position, the x1. Because the remainder of x2 is 10 times of that of x1, we have now ‘1
packet of 10’ from which the divisor 11 has to be subtracted. We see that 11 cannot be
subtracted from the ‘1 packet of 10’. So, the C1 will be updated by 0 count. Now we add the
remainder ‘1 packet of 10’ with the x1 digit and get 11 (10+1 = 11). The divisor 11 is
subtracted once from the borrowed. The C1 is incremented by one. The readers may notice
that the result counter C1 is cumulatively updated in two ways:
(i) First from the ‘Number of Packets of 10 being borrowed from x2’.
(ii) From the additive value of the residual of the above packets and the digit x1.
Note Begins: If we had the dividend of 1417 and the divisor of 11 then we would get count 1 for the C1
and ‘3 packets of 10’ as borrow from the position x2. We would have exhausted these ‘3 packets of 10’ by
the following SURX:
00 → A-reg
while (number of packets not equal zero)
{
A + 10 → A
A ~ (y1y0) /* comparison and not subtraction */
if (A > y1y0 or A= (y1y0))
{
increment counter CX /* X=0,1,2 */
A – (y1y0) → A
goto
}
}
In the 1st pass of the above algorithm, we have no count for C1 because 10 <11. In the 2nd pass, we have
20 from which the 11 could be subtracted 1 time and accordingly the C1 will be updates to 01. In the 3rd
pass, we have 19 ((20-11)+10=19) from which the 11 can be subtracted for one time. The C1 is
incremented by one and it assumes the value of 2. The remainder 8 (19-11=8) is added with x1 (1) to get 9
(8+1=9) from which 11 cannot be subtracted.
Now, there are ‘9 packets of 10’, which are being borrowed from position x1 to position x0. We apply the
above-mentioned algorithm and collect a partial counts of 8 ((9x10)/11=8) for C0. The remainder 2
((9x10-8x11) = 2) is being added with x0 to get 9 (2+7), which contributes no count for C0. The final
remainder is: 9. Thus for the operation of 1417/11, we get the correct result of: Quotient = 128 and
remainder 9. This remainder can be borrowed down further as packets of 10 to get the
fractional values. Note Ends:
4. There is no remainder from the x1 position. So, the update of result counter C0 would be only
form the 2nd component (the step-3ii ). We have now 7 (0+x0 = 7) and from this the divisor 11
cannot be subtracted. So, the counter C0 is not incremented and contains 0.
4. The remainder of this division process is 7. The quotient is, in terms of the counts are: C2=01,
C1=01, C0=00. When the counts are merged, we get the quotient as: 110.
396 Chapter - 6

6. The above procedures, which are laid down by descriptive language may now be translated
into the following pseudo algorithm. The A and B are the arbitrary 8-bit registers.
Pseudo Algorithm:
L0: entry
L1: initialization (00 → C2, C1, C0)
divisor → B-reg; x3x2 → A-reg
L2: if (A>B or A=B)
{
C2 + 1 → C2
A-B → A
goto
}
L3: ; (A-B) = ‘number of packets of 10’ being borrowed down to position x1 from position x2.
; now updating the result counter C1
pass relevant parameters to the SURX
CALL SURX /* see the Assembly program below for coding */
/*
SURX:
00 → A-reg
while (number of packets not equal zero)
{
A + 10 → A
A ~ (y1y0) /* comparison and not subtraction */
if (A > y1y0 or A= (y1y0))
{
increment counter CX /* X=0,1,2 */
A – (y1y0) → A
goto
}
}
*/
add residual of SURX with X1 and extract additional counts for C1;
CALL SURY /* see the Assembly program below for coding */
/*
SURY:
00 → A-reg
while (number of packets not equal zero)
{
A ~ (y1y0) /* comparison and not subtraction */
if (A > y1y0 or A= (y1y0))
{
increment counter CX /* X=0,1,2 */
A – (y1y0) → A
goto
}
}
L4: repeat similar steps of L3 to update result counter C0;
L5: save the final remainder
L6: exit
Problems and Solutions 397

6.8 Problems and Solutions

1 Calculate the magnitudes f the following numbers:
(i) unsigned: 1010d (ii) unsigned: 1010b (iii) Signed Magnitude (SM): 1010b
(iv) unsigned octal: 1010o (v) unsigned: 1010h (vi) Two’s Complement (TC): 1010b
2 Remember that the 8086 treat all negative numbers in TC form. What will be he content of the al-register
at the end of the execution of the following instructions?
mov al, -4
inc al
3 Show your calculation to obtain the TC for the decimal number –7.
Ans: a. ignore the negative sign of the input number.
Now, we have got: 7
b. get the 8-bit binary code for 7
We have: 00000111
c. Invert all the bits of the above step, c.
We have: 11111000 (F8H)
d. Add, 1 with the value of step, c
We have: 11111001 (F9H)
e. This is the TC code for the negative number, -7.
4 Write the steps to be followed to find TC code for –32767 using the Calculator GUI-interface of the
IBMPC.
Ans: a. Set the Calculator in the Scientific Mode
b. Goto the Hex mode and set to Word mode.
c. Goto decimal mode and enter 32767. Click to the Hex radio button. We shall find: 7FFF.
d. Click on the C-button to clear the display window.
e. Now, subtract 7FFF from 0000.
f. We shall find: 8001.
g. 8001h is the TC code for –32767.
5 Write the steps to be followed to find negative decimal number for the TC code A23Ch. Ans: - 24004
6 Show your calculation to obtain the negative number for the TC number, F3H.
Ans: a. Get the 8-bit pattern for the given TC number. We get: F3H = 11110011b
b. Subtract, 1 form the value of step, b
We have: 11110010
c. Inver all the bits of the above step, b
We get: 00001101
d. Get the single decimal digit for the value of step, c
We get: 13
e. Now append a negative sign to the left of the value of step, d
f. Now have the value of -13d for the given TC number F3H
7 Given two unpacked HEX (uHEX) numbers: 02H and 07H. Write 8086-assembly program to convert
these two uHEX into a packed HEX (pHEX = HEX) number.
Ans: upHEX1 = 02h = 00000010b
upHEX2 = 07h = 00000111b
Instructions:
mov al, upHEX1
mov ah, upHEX2
mov cl, 04h
shl al, cl
or al, ah
al-egister contains pHEX = 27h
 Chapter - 6
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8 Given the pHEX number 27H. Write 8086-assembly program to convert it into two uHEX numbers of the
form 02H and 07H.
Ans: pHEX = 27H = 00101111b
Instructions:
mov al, pHEX
mov cl, 04h
ror al, cl
and al, 0Fh
mov ah, pHEX
and ah, 0Fh
al-register contains: 02
ah-register contains: 07
9 Write 8086 ASM program to add the numbers –3d and –8d. Ans: F5H
10 Given a three digit BCD number, BCD = HTU where H stands for ‘Hundred Digit (0-9)’, T stands for the
‘Ten Digit (0-9)’ and U stands for the ‘Unit Digit (0-9)’. Deduce the pseudo codes for converting this BCD
number into BINary.
Solution:
1. Analysis:
Input BCD range: 0000 – 0255
Output BINary range: 00h - FFh
2. Computation By Counting Method:
BCD = HTU
= Hundred Positional Value (HPV) + Ten Positional Value (TPV) +
Unit Positional Value (UPV)
= Hundred Positional Factor (HPF) x Hundred Positional Weight (HPW) +
Ten Positional Factor (TPF) x Ten Positional Weight (TPW) +
Unit Positional Factor (UPF) x Unit positional Weight (UPW)
= (HPF x HPW) + (TPF x TPW) + (UPF x UPW)
= (HPF x 100dD) + (TPF x 10D) + (UPF x 1D) ………………………………… (i)
= (HPF x 64h) + (TPF x 0Ah) + (UPF x 01h) ………………………………….(ii)
BIN = (HPW x 64h) + (TPF x 0Ah) + (UPF x 01h)
= add 64h with 00h cumulatively as many times as the HPF is +
add 0Ah with 00h cumulatively as many times as the TPF is +
add 01h with 00h cumulatively as many times as the UPF is
3. Hand Calculation:
Lets assume, BCD = 0255
The expected BINary output is, BIN = FF
BIN = 2 x 64h + 5 x 0Ah + 5 x 01h
= 5 x 01h + 5 x 0Ah + 2 x 64h
= add 01h with 00h for 5 times (UPV) + add 0Ah with UPV for 5 times (TPV) +
add 64h with TPV for 2 times
BCDBIN

00H + 01H = 01H

01H + 01H = 02H
02H + 01H =03H
03H + 01H = 04H
04H + 01H = 05H : UPV

05H + 0AH = 0FH

0FH + 0AH = 19H
19H + 0AH = 23H
23H + 0AH = 2DH
2DH + 0AH = 37H : (TPV + UPV)

37H + 64H = 9BH

9BH + 64H = FFH : (HPV + TPV + UPV) = BIN
Problems and Solutions
399

The Pseudo Codes:

L1: 00H → IPR (IPR = Initial Partial Result = al-register)
While (UPF != 0)
01h + IPR → IPR
L2: while (TPF != 0)
0Ah + IPR → IPR
L3: while (HPF !=0 )
64h + IPR → IPR
L3A: IPR → al
L4: al-register contains the BINary value for the given BCD.
L5: Display the input BCD at DP0-DP3 positions and the BIN at D10-DP11 positions of the
display unit of the MicroTalk-8086 trainer.
L6: end
11 Write 8086 ASM codes to convert the decimal number, 23 into binary, 17h by Counting Rule.
Ans: ; extract TPF and UPF
mov dl, BCD
and dl, 0Fh ; dl = UPF = 03

mov dh, BCD

mov cl, 04h
shr dh, cl ; dh = TPF = 02

; Compute UPV (unit positional value)

mov al, IPR ; IPR1 = 00h
AGN1: add al, UPW ; UPW = 01h
dec dl
jnz AGN1 ; al = UPV
; Compute TPV
mov ah, IPR2 ; IPR2 = 00h
AGN2: add ah, TPW ; TPW = 0Ah
dec dh
jnz AGN2 ; ah = TPV
add al, ah ; al = BInary
12 Given a BCD number of the range 0000 –0999. The pseudo codes to convert this number into BINary
are given below. Write 8086 ASM codes for it. Ans: BIN = 3E7H
Solution:
Assume that: BCD = HTU [ where, T for thousand]
L1: initialize everything as needed
L2: while (UPF !=0)
UPW (01H) + IPR → IPR
L3: while (TPF !=0)
{
IPR + TPW (0AH) → IPR
If (carry = 1)
{
increment the carry_counter
Goto L3
}
else
Goto L3
}
L4: The carry_counter contains 03, the upper part of the result and the
al-register contains E7, the lower part of the result.
 Chapter - 6
400

13 Explain the need and the meaning of the instruction, daa of the 8086 microprocessor.
Ans:
The full name of the mnemonics, daa is: Decimal Adjustment of the content of al-register after Addition.
Need of DAA Instruction:
a. The 8086 cannot perform arithmetic operations on decimal data. That is, the 8086 do not support
BCD data.
b. However, say we have submitted two decimal numbers, 17d and 14d to the 8086 via the registers al
and ah respectively. We have told the 8086 to add these numbers.
c. The CPU simply considers these two numbers as if these are unsigned binary (hex is a compact form
of binary). So, the result computed by the CPU is: 2Bh
d. But, we know that our input numbers are decimal and we expect a result of 31.
e. Now, we have to tell the CPU to adjust the incorrect result, 2B into correct result of 31.
f. The 8086 will politely do it by executing the instruction: daa.
g. Thus the instruction daa is used to obtain the correct BCD result if an arithmetic operation is done on
BCD numbers.
14 (a) Write a program using pseudo codes or 8086 assembly codes to add 17 and 13 .
Ans:
L1: 17 → al;
13 → ah;
L2: al + ah → c, al;
L3: if ((al3 – al0) > 9)
L3A: al + 06 → c, al
L4: al register contains the correct BCD result: 30
L5: Use MicroTalk-8086 trainer and display the result at DP0-DP1 positions of the display.
Question: 1. Why is it necessary to add 06 with al-register at Label L3A in the above solution?
Ans: a. We submitted to the CPU, the decimal symbols 17 and 13. These symbols have appeared to the
CPU as binary as follows: -
0001 0111 (17h)
0001 0011 (13h)
b. The CPU carried out binary addition on these bit patterns and produces: -
0010 1010 (2Ah)
c. But, we know that the numbers that we have submitted to the CPU are the decimal numbers. So,
the result that we expect after addition is the symbol 30 and not 2A. The result that the CPU has
produced is correct to itself but incorrect (not wrong! There is a difference between the words
‘incorrect’ and ‘wrong’) to us. Now, to get the symbol 30 out of 2A, there is no way but to add 06
with 2A. Thus we get; -
0010 1010 (2A): an incorrect symbol
+ 0000 0110
------------------------
= 0011 0000 (30): Expected symbol that corresponds to decimal 30.
Question: 2. Write a program using pseudo codes or 8086 assembly codes to add 83 and 21.
Ans: L1: 83 → al;
21 → ah;
L2: al + ah → c, al;
L3: if ((al7 – al4) > 9)
L3A: al + 60 → c, al
L4: c., al register contains the correct BCD result: 104
L5: Use MicroTalk-8086 trainer and display the result at DP0-DP2 positions of the display.
Question: 3. Write a program using pseudo codes or 8086 assembly codes to add 78 and 09.
Ans: L1: 78 → al; 09 → ah;
L2: al + ah → c, al;
L3: if (AC = 1)
Problems and Solutions 401

L3A: al + 06 → c, al
L4: al register contains the correct BCD result: 87
L5: Use MicroTalk-8086 trainer and display the result at DP0-DP1 positions of the display.

Questi4. 4. Write a program using pseudo codes or 8086 assembly codes to add 90 and 79.
Ans: L1: 90 → al;
79 → ah;
L2: al + ah → al;
L3: if (CY = 1)
L3A: al + 60 → al
L4: c, al register contains the correct BCD result: 169
15 Write a program using pseudo codes for adding two decimal numbers of the range (00 to 99). The
program will always provide the correct BCD results.
Ans: L1: BCD1 → al;
BCD2 → ah;
L2: al + ah → c, al
L3: if ((al3 – al0) > 9))
{
al + 06 → al;
Goto L4;
}
L4: if ((al7 – al4) > 9))
{
al + 60 → al;
Goto L5;
}
L5: if (AC = 1)
{
al+ 06 → al;
Goto L6;
}
L6: if (CY = 1)
{
al + 60 → al;
Goto L7;
}
L7: The result will be found at: -
Carry-bit of the CPU will contain the upper byte of the result
al-register of the CPU contains the lower byte of the result.
16 Pass two BCD numbers 18 and 79 into the al and ah registers of the 8086 CPU using suitable memory
locations. Now write 8086 assembly program to add these two numbers. The program length must not
exceed 10 instructions.
Solution:
(03012h) = 18; (03013h) = 79
mov ax, WORD PTR [bx+12h]
add al, ah [ al = 00011000 + 01111001 = 1001 0001 ; an auxiliary carry has generated ]
daa [ al = 1001 0001 + 00000110 = 97 ]
al-register contains the number: 97
17 (a) What are the four rules that the 8086 apply to obtain correct BCD result in response to daa
instruction?
(b) Write 8086 assembly codes to convert 0DH into 13.
(c) Calculate the decimal value for the following numbers:
(i) 1010 ; this is a Signed Magnitude number and base 2
 Chapter - 6
402

(ii) 1010; this is a 2’s complement code number and base 2

(iii) 1010; this is an unsigned number and base 8
(iv) 1010; this is an unsigned number and base 2.
18 Write pseudo codes and the flow chart to compute 02hx03hx04h using 8086 architecture.
Solution Hints:
L1: 02 → counter1 (cl) ;
03 → counter2 (ch);
04 → counter3 (ah);
00 → al (IPR)
L1A: if (cl = 0)
goto EXIT (L9)
L2: if (ch = 0)
goto EXIT (L9)
L3: if (ah = 0)
goto EXIT (L9)
L4: while (cl !=0)
IPR + 01h → IPR
L5: IPR → cl
00 → IPR
L6: While (ch !=0)
IPR + cl → IPR
L7: IPR → ch
00 → IPR
L8: While (ah !=0)
IPR + ch → IPR
L9: IPR → al (al = 18h, the result in binary)
19 Describe the principles of the Horner Rule and deduce the complete solution for the conversion of an
input BINary number (range: 00H – FFH) into equivalent BCD number (range: 0 – 255).
20 The circuit to the left side of the following diagram is a hardware based BCD to 7-segment converter.
Circuit to the right side is a software based BCD-to-CC Seven Segment converter. Write ASM codes to
output 23 on the display devices of these two circuits.
Problems and Solutions 403

21 Write Pseudo Code to convert a two-digit BCD (range: 00 – 99) number into equivalent BINary number
(range: 00h – 63h).
22 Write ASM codes to add the BCD numbers 97 and 23. Be sure that the final result is a correct BCD.
23 Write in Text all the four rules that must be applied to get correct BCD from an incorrect BCD result
that the 8086 produces after the addition of given BCD numbers.
24 Write Pseudo Codes for all the four rules that are represented by the daa instruction.
25 Write Pseudo Codes to convert a two-digit Binary number (range: 00h – 63h) into equivalent BCD
number (range: 00 – 99).
26 Convert the following Pseudo Codes into 8086 ASM codes.
i. if (al3 – al0) > 9 ii. if (al7 – al4) > 9
al + 06h → al al + 60h → al
27 Assume that we have a two-digit BCD number of the form BCD = TU. Now, write Pseudo Codes and
8086 ASM codes to convert this BCD number into equivalent Binary number.
28 Given that BCD1 = 79 and BCD2 = 35. Write 8086 ASM code to add these numbers. Be sure that the
result is a correct BCD number.
29 Write 8086 assembly codes to convert 37h into equivalent BCD of 55.
30 Given two BCD numbers 9999 and 2356. Add these two numbers and be sure that the result is a correct
BCD. Saves the result into two consecutive memory locations starting at 03010h.
Ans: mov ax, 9999h ; ah = 99 al =99
mov bx, 2356h ; bh = 23, bh = 56
add al, bl ; al = EF, cf=0

daa ; al = 55, cf = 1
mov dl, al ; dl = 55
mov al, ah
adc al, bh ; al = CC, cf=0
daa ; al = 32, cf=1

; final BCD result is: 13255 and is in: c, al, dl

31 Draw 8086-based Register Model to implement 32-bit BIN2BCD conversion routine using Horner Rule.
32 Consider the following parameters for the Chinese General Number (CGR) number system (the
Americans call it Residual Number System to inscribe their false claim). Find the decimal value for the
number, N.
Chinese General Base, CGB = N [3, 5, 7] = N [b2, b1, b0]
Chinese General Residual, CGR = N [0, 1, 4] = N [r2, r1, r0]
Solution Hints:
The notations cited above have been formulated by the author based on a brief text published in the
daily, the Protham Alo by Dr. Ataul Karim perhaps in the year 2006. Many years ago, a spy asked a
Chinese army general about the number of his soldiers. The general replied as: “If my soldiers are
arranged in 3 rows, there is no remains; when arranged in 5 rows, there is a remainder of one soldier;
when arranged in 7 rows, there is a remainder of 4. Now, guess the number of soldiers.” The author
offered this problem to the students of his ‘Microprocessor Class’ and two students came up with two
different formulas of which the most correct one is given below credited to Mr. Kawser. The 2nd
formula is still with my student Mr. Tanvir. The author wrote an 8051-based simulation program to
test the validity of the formula and found to be working for a certain range of numbers.
N = {b2 b1 b0 + b1 b0 (b2 – r2) + b0 b2 r1} % (b2 b1 b0)
= {3 x 5 x 4 + 5 x 7 (3 – 0) + 7 x 3 x 1} % (3 x 5 x 7)
= (60 + 105 +21) % (105) [% means modulo, the remainder is discarded]
= 186 % 105 = 81
 Chapter - 6
404

Reference: P-823 of Introduction to Algorithm by Thomas H. Cormen: Quote: [Around A.D. 100, the
Chinese mathematician Sun-Tsu solved the problem of finding those integers x that leave remainders
2, 3 and 2 when divided by 3, 5 and 7 respectively. One such solution is x = 23; all solutions are of the
form 23 + 105k for arbitrary integers k. The “Chinese remainder theorem” provides a correspondence
between a system of equations modulo a set of pairwise relatively prime moduli (for example 3, 5 and )
and an equation modulo their product (for example 105). UnQuote].
33 Find the decimal value for the binary umber: 101.001
Ans: BCD = 1x22 + 0x21 + 1x20 + 0x2-1 + 0x2-2 + 1x2-3
=4 +0 +1 +0 + 0.250 + 0.125
= 5.375
34 Draw data structure for the subroutines HEXCC and CCXDRAM, which have been used in the
program codes of Example-6.13.
a. HEX2CC Subroutine: Converting Hex –digit into CC-code
i. Purpose: This SUR consults a ROM-based ‘Lookup Table’ of the MicroTalk-8086 trainer to
find the 8-bit CC-codes for every digit (0 – F) of a given hexadecimal (or BCD) number.
ii. Input HEX: The input HEX number must be given via a RAM-based table as is shown
below. The beginning address of the HEX-Table is pointed by si-register. The number of
HEX bytes to be transformed is given via ch-register.
iii. Output CC: The output CC-codes are available via a RAM-based table as is shown below.
The beginning address of the CC-Table is pointed by di-register.
iv. Data Structure:

v. Pseudo Codes:
while (ch != 0)
{
read from location @si
convert upper digit into CC-code by consulting Lookup table
write CC-code at location @di
convert lower digit into CC-code by consulting Lookup Table
write the CC-code at location @di+01h
- - si
+ + di
}
Problems and Solutions 405

vi. Working Principles:

A Lookup Table (LUT) contains known data. The memory locations of the LUT of the
HEX2CC subroutine contains CC-codes data for the digits 0 – F in the following way:
Say, we wish to keep the CC-code (71) of digit F in memory. Then, at what memory location
should we keep it? Naturally, the digit F, somehow be included in the formation of the 20-bit
address of the ROM location. If so, the number F0h (or 0Fh) being a part of the address will
automatically point to the exact memory location that contains the CC-code for the digit F.
Similarly, 00h will point to a memory location for the CC-code of digit 0, 10h for the CC-code of
digit 1, 20h for the CC-code of digit 2, 30 for the CC-code of digit 3 and so on. We prefer to use
ROM because it is non-volatile and the data will always be found there.
Now, we read the hex byte (F0h) from memory location 00527h of the HEX-Table. The
following ASM codes correctly find the CC-codes for the digits F and 0 from the LUT.
L1: mov al, (00527h) ; al = F3
; now extract F0 from F3
and al, 0Fh ; al =F0
; now make F0h a part of the address FFEF0, which contains
; the CC-code 71h for the digit F
; FFEF0 = FFE00 + F0
mov dx, 0FFE0h
mov es, ax
mov ah, 00h
mov bx, ax ; ax = ah, al = 00, F0
; now read the CC-code from location FFEF0h
mov al, BYTE PTR es:[bx] ; al=71h = cc-code of F
; now read the hex byte (F3) again from location 00527h and
; extract 30h form F3
; ASM codes similar to above may now be exercised to read
; the CC-code of digit 3 from memory location FFE30h.
b. CCXDRAM Subroutine: Transferring CC-code into a desire DRAM (Display RAM) location

i. Working Principles: The desired DRAMX [X=0–F] is first selected by sending Cbyte [Table-
4.2, P-242] into CR of 8279. The CC-code is read from CC-Table pointed by di-register. It is
then written into the desired DRAMX location of 8279, which is pointed by DR. The data
from DRAMX is automatically displayed on the DPX position of the display.
406 Chapter - 6

35 Based on the theory of LSS method of Section-6.7 (c), design computation model and ASM codes to
divide an unsigned 32-bit number 87ABCDEFh (2276183535) by an unsigned 16-bit number 8CA1h
(36001). Test your program using MicroTalk-8086 trainer. The quotient F6F9h (063225) will appear at
DP0-DP3 positions and the remainder CDEFh (052719) will appear at DP12-DP15 positions of the
display unit of the trainer. Save the program as ….\mtk8086\P621.asm.

a. Working Principles: 32-bit by 16-bit unsigned division by LSS method is just and extension of the
8-bit by 8-bit unsigned division of Section-6.7 (c). Because, the remainder will never exceed the
size of the divisor, we have taken a 16-bit register to accommodate the IPRM (Initial Partial
Remainder).
Practically, it may happen that a 16-bit chunk has entered into the IPRM from the dividend, but it
is still not divisible by the divisor. Under this condition, one more bit from the dividend should
be pushed into the IPRM in such a way so that the IPRM15 (Bit-15) of the current IPRM enters
into the carry-bit. And then the computation would follow the same principles as that of basic 8-
bit by 8-bit division of the LSS method.
b. Assembly Codes:
START: nop
L1: ;--- initialization -------
mov bx, 3000h ; offset pointer
mov si, WORD PTR [bx+10h] ; 16it lower dividend CDEFh
mov di, WORD PTR [bx+12h] ; 16-bit upper dividend 87ABh
mov cx, WORD PTR [di+14h] ; divisor 8CA1h
mov ax, 0000h ; 16-bit IPRM
mov bx, 0000h ; IPQ=initial partial quotient

mov dl, 20h ; size of dividend

L2: rcl si, 01h

rcl di, 01h
rcl ax, 01h ; dividend is left-shifted
jc L3 ; 17-bit is LH
L2A: cmp ax, cx
jnge L7 ; ax < cx ; IPRM < divisor
L3: sub ax, cx ; ax > cx ; IPRM > divisor
L3A: stc
rcl bx, 01h ; LH at LSBX-bit of Quotient

L4: dec dl
jnz L2

L5: mov ax, bx ; quotient

mov dx, cx ; remainder
mov bx, 3000h
call RESDISP ; DP0 - DP3 = quotient ; DP12-DP15 = remainder
L6: hlt
Ttttttttttttttttttttttyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyyy-p0]]============== c`
L7: clc
rcl bx, 01h ; LL at LSBX-bit of IPQ
jmp L4
407