University of Technology – VNU-HCM 12 August 2021

Introduction
Computer Architecture • Language: a system of communication consisting of sounds, words, and grammar,
Chapter 2: MIPS or the system of communication used by people in a particular country or type of
work (Oxford Dictionary)

Adapted from Computer Organization the Hardware/Software Interface – 5th

Computer Engineering – CSE – HCMUT [Link]

Chapter 2: MISP - ISA 2

Introduction (cont.) Instruction Set Architecture (ISA)

• To command a computer’s hardware: speak its
language

[Link]
Chapter 2: MISP - ISA 3 Chapter 2: MISP - ISA 4

Chapter 2 – MIPS Instruction Set Architecture 1

University of Technology – VNU-HCM 12 August 2021

Von Neumann Architecture Computer Components

• Stored-program
concept
• Instruction category:
– Arithmetic
– Data transfer
– Logical
– Conditional branch
– Unconditional jump

Chapter 2: MISP - ISA 5 Chapter 2: MISP - ISA 6

Instruction Execution The MIPS Instruction Set

• MIPS architecture
• MIPS Assembly Inst.  MIPS Machine Instr.
• Assembly:
– add $t0, $s2, $t0
• Instruction fetch: from the memory
• Machine:
– PC increased
– 000000_10010_01000_01000_00000_100000
– PC stores the next instruction
• Only one operation is performed per MIPS
• Execution: decode and execute
instruction
Chapter 2: MISP - ISA 7 Chapter 2: MISP - ISA 8

Chapter 2 – MIPS Instruction Set Architecture 2

University of Technology – VNU-HCM 12 August 2021

IS Design Principles MIPS Operands

• Simplicity favors regularity • 32 32-bit registers
– $s0-$s7: corresponding to variables
• Smaller is faster
– $t0-$t9: storing temporary value
• Make the common case fast – $a0-$a3
• Good design demands good compromises – $v0-$v1
– $gp, $fp, $sp, $ra, $at, $zero, $k0-
$k1
• 230 memory words (4 byte): accessed only by data
transfer instructions (memory operand)
• Immediate
Chapter 2: MISP - ISA 9 Chapter 2: MISP - ISA 10

Arithmetic Instructions Design Principle 1

Opcode
Destination Source Source • Simplicity favours regularity
register register 1 register 2(*)
– Regularity makes implementation simpler
– Simplicity enables higher performance at lower
• Opcode: cost
– add: DR = SR1 + SR2
– sub: DR = SR1 – SR2
– addi: SR2 is an immediate (e.g. 20), DR = SR1 +
SR2
• Three register operands
Chapter 2: MISP - ISA 11 Chapter 2: MISP - ISA 12

Chapter 2 – MIPS Instruction Set Architecture 3

University of Technology – VNU-HCM 12 August 2021

Arithmetic Instructions: Example Data Transfer Instructions

• Q: what is MIPS code for the following C code • Move data b/w memory
f = (g + h) – (i + j); and registers
– Register
If the variables g, h, i, j, and f are assigned to the – Address: a value used to
register $s0, $s1, $s2, $s3, and $s4, delineate the location of
respectively. a specific data element
within a memory array
• A:
• Load: copy data from
add $t0, $s0, $s1 # g + h memory to a register
add $t1, $s2, $s3 # i + j • Store: copy data from a
sub $s4, $t0, $t1 # t0 – t1 register to memory
Chapter 2: MISP - ISA 13 Chapter 2: MISP - ISA 14

Data Transfer Instructions (cont.) Data Transfer Instructions (cont.)

• Opcode:
Memory
Opcode Register
address – lw: load word
– sw: store word
– lh: load half ($s1 = {16{M[$s2+imm][15]},M[$s2 + imm]})
• Memory address: offset(base register) – lhu: load half unsigned ($s1 = {16’b0,M[$s2 + imm]})
– sh: store half
– Byte address: each address identifies an 8-bit byte – lb: load byte
– “words” are aligned in memory (address must be – lbu: load byte unsigned
multiple of 4) – sb: store byte
– ll: load linked word
– sc: store conditional
– lui: load upper immediate $s1 = {imm,16’b0}
Chapter 2: MISP - ISA 15 Chapter 2: MISP - ISA 16

Chapter 2 – MIPS Instruction Set Architecture 4

University of Technology – VNU-HCM 12 August 2021

Memory Operands Memory Operand Example 1

• Main memory used for composite data • C code:
– Arrays, structures, dynamic data
• To apply arithmetic operations g = h + A[8];
– Load values from memory into registers – g in $s1, h in $s2, base address of A in $s3
– Store result from register to memory
• Compiled MIPS code:
• MIPS is Big Endian
– Most-significant byte at least address of a word – Index 8 requires offset of 32
– c.f. Little Endian: least-significant byte at least address • 4 bytes per word
lw $t0, 32($s3) # load word
add $s1, $s2, $t0

Chapter 2: MISP - ISA 17 Chapter 2: MISP - ISA 18

Memory Operand Example 2 Exercise

• Show the effects on memory and • a) lw $t1, 0($t0)
• C code: registers of the following • b) lw $t2, 4($t0)
instructions. Suppose a portion of • c) lb $t3, 0($t0)
A[12] = h + A[8]; memory contains the following
data • d) lb $t4, 4($t0)
– h in $s2, base address of A in $s3 • e) lb $t5, 3($t0)
• f) lh $t6, 4($t0)
• Compiled MIPS code: • g) sw $s0, 0($t0)
• h) sb $s0, 4($t0)
– Index 8 requires offset of 32 • And register $t0 contains • i) sb $s0, 7($t0)
lw $t0, 32($s3) # load word 0x10000000 and $s0 contains
0x01234567. Assume each of the
add $t0, $s2, $t0 following instructions is executed
independently of the others,
sw $t0, 48($s3) # store word starting with the values given
above

Chapter 2: MISP - ISA 19 Chapter 2: MISP - ISA 20

Chapter 2 – MIPS Instruction Set Architecture 5

University of Technology – VNU-HCM 12 August 2021

Exercise Registers vs. Memory

• Convert the following C statements to • Registers are faster to access than memory
equivalent MIPS assembly language if the • Operating on memory data requires loads and
variables f, g, and h are assigned to registers stores
$s0, $s1, and $s2 respectively. Assume that – More instructions to be executed
the base address of the array A and B are in • Compiler must use registers for variables as
registers $s6 and $s7, respectively. much as possible
• 1) f = g + h + B[4] – Only spill to memory for less frequently used
variables
• 2) f = g – A[B[4]] – Register optimization is important!

Chapter 2: MISP - ISA 21 Chapter 2: MISP - ISA 22

Immediate Operands The Constant Zero

• Constant data specified in an instruction • MIPS register 0 ($zero) is the constant 0
addi $s3, $s3, 4 – Cannot be overwritten
• No subtract immediate instruction • Useful for common operations
– Just use a negative constant
– E.g., move between registers
addi $s2, $s1, -1
add $t2, $s1, $zero
• Design Principle 3: Make the common case
fast
– Small constants are common
– Immediate operand avoids a load instruction

Chapter 2: MISP - ISA 23 Chapter 2: MISP - ISA 24

Chapter 2 – MIPS Instruction Set Architecture 6

University of Technology – VNU-HCM 12 August 2021

Unsigned Binary Integers 2s-Complement Signed Integers

• Given an n-bit number • Given an n-bit number
n−1 n−2
x = xn−12 + xn−2 2 + + x12 + x0 2
1 0
x = − x n−1 2n−1 + x n−2 2n−2 +  + x1 21 + x 0 20
• Range: 0 to +2n –1 ◼ Range: –2n – 1 to +2n – 1 – 1
• Example • Example
– 0000 0000 0000 0000 0000 0000 0000 10112 – 1111 1111 1111 1111 1111 1111 1111 11002
= 0 + … + 1×23 + 0×22 +1×21 +1×20 = –1×231 + 1×230 + … + 1×22 +0×21 +0×20
= 0 + … + 8 + 0 + 2 + 1 = 1110 = –2,147,483,648 + 2,147,483,644 = –410

• Using 32 bits • Using 32 bits

– 0 to +4,294,967,295 – –2,147,483,648 to +2,147,483,647
Chapter 2: MISP - ISA 25 Chapter 2: MISP - ISA 26

2s-Complement Signed Integers Signed Negation

• Bit 31 is sign bit • Complement and add 1
– 1 for negative numbers
– 0 for non-negative numbers – Complement means 1 → 0, 0 → 1
• –(–2n – 1) can’t be represented x + x = 1111...1112 = −1
• Non-negative numbers have the same unsigned and
2s-complement representation x + 1 = −x
• Some specific numbers • Example: negate +2
– 0: 0000 0000 … 0000 – +2 = 0000 0000 … 00102
– –1: 1111 1111 … 1111
– –2 = 1111 1111 … 11012 + 1
– Most-negative: 1000 0000 … 0000
– Most-positive: 0111 1111 … 1111 = 1111 1111 … 11102

Chapter 2: MISP - ISA 27 Chapter 2: MISP - ISA 28

Chapter 2 – MIPS Instruction Set Architecture 7

University of Technology – VNU-HCM 12 August 2021

Sign Extension
• Representing a number using more bits
– Preserve the numeric value
• In MIPS instruction set
– addi: extend immediate value
– lb, lh: extend loaded byte/halfword
– beq, bne: extend the displacement
• Replicate the sign bit to the left
– c.f. unsigned values: extend with 0s
• Examples: 8-bit to 16-bit
– +2: 0000 0010 => 0000 0000 0000 0010
– –2: 1111 1110 => 1111 1111 1111 1110

Chapter 2: MISP - ISA 29

Chapter 2 – MIPS Instruction Set Architecture 8