Lecture 1: Introduction,
Embedded Systems, Product
Life-Cycle, ARM Programming
Dr. Nguyen Chi Ngoc 1-1
Agenda
qCourse Description
vBook, Labs, Equipment
vGrading Criteria
vExpectations/Responsibilities
vPrerequisites
qEmbedded Systems
qMicrocontrollers
qProduct Life Cycle
vAnalysis, Design, Implementation, Testing
vFlowcharts, Data-Flow and Call Graphs
qARM Architecture
qProgramming
qIntegrated Development Environment (IDE)
1-2
Useful Info
• No labs this week!
• Lab lectures start this Friday
• F 4–5, M 6:30–7:30 and 7:30-8:30 (ECJ 1.202)
• Office hours: see Canvas for most recent?
• TAs have office hours too
• They are not there to do your work for you
• One course == common exams and HW
• 2/23 7–8:30 (15%) 4/6 7–8:30 (20%) Final TBD (25%)
• Most of the learning is in the labs
• 10 labs 30% of grade
• HW is important too so 10% for motivation
• Read the book and lab manual!
• Canvas, Piazza, and
[Link]/~valvano/Volume1/
1-3
Action Items
• Come introduce yourselves
• Take stock of resources
• Class Website (Volume1)
• Piazza for class discussions
• Email to reach TAs+Me
• E-Book: Search “Valvano e-book”
• Order board
• Install SW
• Read Chapters 1 & 2 of book
1-4
DOs and DON’Ts
DO DON’T
•Read •Don’t cheat!
• Book, lab, datasheets •Never look at
•Try before seeking help another student’s
•Follow Piazza/Canvas code (current or
previous)
•Discuss material with
others •Don’t let your partner
do all the work
•Homework (not labs) in
groups •Don’t copy software
from book or web
•Consult the web without attribution
•Track due dates •Don’t expect
handholding
1-5
EE306 Recap: Digital Logic
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q AND, OR, NOT
q Flip flops
q Registers
Positive logic: Negative logic :
True is higher voltage True is lower voltage
False is lower voltage False is higher voltage
1-6
EE306, Also
• Problem solving
• Programming
• Debugging
1-7
EE302 Recap: Ohm’s Law
V=I*R Voltage = Current * Resistance
I=V/R Current = Voltage / Resistance
R=V/I Resistance = Voltage / Current
*"#"'()+I
"
!"##$B&
# ! &#'()& !"#"A%!
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•P = V * I Power = Voltage * Current
•P = V2 / R Power = Voltage2 / Resistance 1 amp is 6.241×1018
•P = I2 * R Power = Current2 * Resistance electrons per second =
1 coulomb/sec
1-8
!"#A%C'
Embedded System
()*+I+*A-"
q Embedded Systems are
.+II)/A%C*A+/M
!A'A*C13
everywhere
v Ubiquitous, invisible
v Hidden (computer inside)
v Dedicated purpose
q Microprocessor
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.+IM)I"1
v Intel: 4004, ..8080,..
x86
v Freescale: 6800, ..
MP8LSSLSA)9)ELP 9S12,.. PowerPC
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v ARM, DEC, SPARC, MIPS,
[Link]+I1.O
PLI41-+I1.O PowerPC, Natl. Semi.,…
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CD
q Microcontroller
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I/O Ports (Interfaces)
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1-9
Microcontroller
q Processor – Instruction Set + memory + accelerators
q Ecosystem
q Memory
v Non-Volatile
o ROM
o EPROM, EEPROM, Flash
v Volatile
o RAM (DRAM, SRAM)
q Interfaces
v H/W: Ports
v S/W: Device Driver
v Parallel, Serial, Analog, Time
q I/O
v Memory-mapped vs. I/O-instructions (I/O-mapped)
1-10
Texas Instruments TM4C123
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1-11
LaunchPad Switches and LEDs
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q The switches on the LaunchPad
vNegative logic
vRequire internal pull-up (set bits in PUR)
q The PF3-1 LEDs are positive logic
1-12
I/O Ports and Control Registers
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" " GPIO_PORTF_DATA_R
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GPIO_PORTF_DIR_R
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The input/output direction of a bidirectional port
is specified by its direction register.
GPIO_PORTF_DIR_R , specify if
corresponding pin is input or output:
v 0 means input
v 1 means output
1-13
I/O Ports and Control Registers
Address 7 6 5 4 3 2 1 0 Name
400F.E608 - - GPIOF GPIOE GPIOD GPIOC GPIOB GPIOA SYSCTL_RCGCGPIO_R
4002.53FC - - - DATA DATA DATA DATA DATA GPIO_PORTF_DATA_R
4002.5400 - - - DIR DIR DIR DIR DIR GPIO_PORTF_DIR_R
4002.5420 - - - SEL SEL SEL SEL SEL GPIO_PORTF_AFSEL_R
4002.551C - - - DEN DEN DEN DEN DEN GPIO_PORTF_DEN_R
• Initialization (executed once at beginning)
1. Turn on clock in SYSCTL_RCGCGPIO_R
2. Wait two bus cycles (two NOP instructions)
3. Unlock PF0 (PD7 also needs unlocking)
4. Set DIR to 1 for output or 0 for input
5. Clear AFSEL bits to 0 to select regular I/O
6. Set PUE bits to 1 to enable internal pull-up
7. Set DEN bits to 1 to enable data pins
• Input/output from pin
6. Read/write GPIO_PORTF_DATA_R 1-14
Product Life Cycle
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Analysis (What?) Implementation(Real)
vRequirements -> vHardware, Software
Specifications Testing (Works?)
Design (How?) vValidation:Correctness
vHigh-Level: Block Diagrams vPerformance: Efficiency
vEngineering: Algorithms, Maintenance (Improve)
Data Structures, Interfacing
1-15
Data Flow Graph
Lab 8: Position Measurement System
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1-16
Call Flow Graph
Position Measurement System
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1-17
Structured Programming
Common Constructs (as Flowcharts)
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1-18
Flowchart
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Coding in assembly and/or high-level language (C)
1-19
Flowchart
q Example 1.3. Design a flowchart for a system that performs two independent
tasks. The first task is to output a 20 kHz square wave on PORTA in real time
(period is 50 ms). The second task is to read a value from PORTB, divide the
value by 4, add 12, and output the result on PORTD. This second task is repeated
over and over.
C'() D
void SysTick_Handler(void){
*)+I-.)./0#C A !"#$% PORTA = PORTA^0x01; >
" } #
PORTB
PORTA 1 > void main(void){ D
PORTA:7 unsigned long n;
).1.O)345678 B while(1){
# n = PORTB; A
n = (n/4)+12; B
PORTD = n; C
9I-+I-.).-# }
PORTD C
}
1-20
ARM Cortex M4-based System
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q ARM Cortex-M4 processor
q Harvard architecture
v Different busses for instructions and data
1-21
ARM Cortex M4-based System
q RISC machine
v Pipelining effectively provides single cycle operation for many instructions
v Thumb-2 configuration employs both 16 and 32 bit instructions
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1-22
ARM ISA: Thumb2 Instruction Set
q Variable-length instructions
vARM instructions are a fixed
length of 32 bits
vThumb instructions are a fixed
length of 16 bits
vThumb-2 instructions can be
either 16-bit or 32-bit
q Thumb-2 gives approximately 26%
improvement in code density over
ARM
q Thumb-2 gives approximately 25%
improvement in performance over
Thumb
1-23
ARM ISA: Registers, Memory-map
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Condition Code Bit s Indicates
N negative Result is negative TI TM4C123
Z zero Result is zero
V overflow Signed overflow Microcontroller
C carry Unsigned overflow
1-24
LC3 to ARM - Data Movement
LEA R0, Label ;R0 <- PC + Offset to Label
ADR R0,Label or LDR R0,=Label
LD R1,Label ; R1 <- M[PC + Offset]
LDR R0,=Label ; Two steps: (i) Get address into R0
LDRH R1,[R0] ; (ii) Get content of address [R0] into R1
LDR R1,R0,n ; R1 <- M[R0+n]
LDRH R1,[R0,#n]
LDI R1,Label ; R1 <- M[M[PC + Offset]]
; Three steps!!
ST R1,Label ; R1 -> M[PC + Offset]
LDR R0,=Label ; Two steps: (i)Get address into R0
STRH R1,[R0] ; (ii) Put R1 contents into address in R0
STR R1,R0,n ; R1 -> M[R0+n]
STRH R1,[R0,#n]
STI R1,Label ; R1 -> M[M[PC + Offset]]
; Three steps!!
1-25
LC3 to ARM – Arithmetic/Logic
ADD R1, R2, R3 ; R1 <- R2 + R3
ADD R1,R2,R3 ; 32-bit only
ADD R1,R2,#5 ; R1 <- R2 + 5
ADD R1,R2,#5 ; 32-bit only, Immediate is 12-bit
AND R1,R2,R3 ; R1 <- R2 & R3
AND R1, R2, R3 ; 32-bit only
AND R1,R2,#1 ; R1 <- Bit 0 of R2
AND R1, R2, #1 ; 32-bit only
NOT R1,R2 ; R1 -> ~(R2)
EOR R1,R2,#-1 ; -1 is 0xFFFFFFFF,
; so bit XOR with 1 gives complement
1-26
LC3 to ARM – Control
BR Target ; PC <- Address of Target
B Target
BRnzp Target ; PC <- Address of Target
B Target
BRn Target ; PC <- Address of Target if N=1
BMI Target ; Branch on Minus
BRz Target ; PC <- Address of Target if Z=1
BEQ Target
BRp Target ; PC <- Address of Target if P=1
No Equivalent
BRnp Target ; PC <- Address of Target if Z=0
BNE Target
BRzp Target ; PC <- Address of Target if N=0
BPL Target ; Branch on positive or zero (Plus)
BRnz Target ; PC <- Address of Target if P=0
No Equivalent
1-27
LC3 to ARM – Subs,TRAP,Interrupt
JSR Sub ; PC <- Address of Sub, Return address in R7
BL Sub ; PC<-Address of Sub, Ret. Addr in R14 (Link Reg)
JSRR R4 ; PC <- R4, Return address in R7
BLX R4 ; PC <-R4, Return address in R14 (Link Reg)
RET ; PC <- R7 (Implicit JMP to address in R7)
BX LR ; PC <- R14 (Link Reg)
JMP R2 ; PC <- R2
BX R2 ; PC <- R14 (Link Reg)
TRAP x25 ; PC <- M[x0025], Return address in R7
SVC #0x25 ; Similar in concept but not implementation
RTI ; Pop PC and PSR from Supervisor Stack…
BX LR ; PC <- R14 (Link Reg) [same as RET]
1-28
ARM is a Load-Store machine
Code to set (to 1) bit 5 of memory address x400FE608
SYSCTL_RCGCGPIO_R EQU 0x400FE608
; EQU psedo-op allows use of
; symbolic name to represent a constant
LDR R1, =SYSCTL_RCGCGPIO_R ; R1 holds x400FE608
LDR R0, [R1] ; R0 holds contents of
; location x400FE608
ORR R0, R0, #0x20 ; bit5 of R0 is set to 1
STR R0, [R1] ; write R0 contents back to
; location x400FE608
1-29
SW Development Environment
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!*=#+-/&E :A"B&;;"A
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Start
; direction register 4&8#.
LDR R1,=GPIO_PORTD_DIR_R !&;;*"S <&="A>
LDR R0,[R1]
ORR R0,R0,#0x0F
; make PD3-0 output ?@T
STR R0, [R1]
F#*+EDI-A.&/DM1OP
T89&B/DB"E& C&-+ :A"B&;;"A
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0x00000142
0x00000144
4912
6808
4"RS+"-E
0x00000146 F040000F <&="A>
0x0000014A 6008 !/-A/
4&8#.
!&;;*"S ?@T
AEEA&;;DDD4-/-
1-30
