EE141
EECS141
EE141 Lecture #28 1
Hw 8 due Today
Hw 9 posted
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Technology 45 32 22 16 11 8
Node (nm)
Integration 8 16 32 64 128 256 512 1024
Capacity (BT)
Delay Scaling >0.7 ~1?
Energy Scaling ~0.5 >0.5
Transistors Planar 3D, FinFET
Variability High Extreme
ILD ~3 towards 2
RC Delay 1 1 1 1 1 1
Metal Layers 8-9 0.5 to 1 Layer per generation
THE OPTIMISTIC PERSPECTIVE
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Cost
Energy!
0.12
0.11
0.1
0.09
EOP (fJ)
0.08
0.07
0.06
0.05
0.04
0.03
20 30 40 50 60 70 80 90
Technology node (nm)
Size
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THE IT PLATFORM OF THE NEXT DECADE
Infrastructural
core
Sensory
swarm
Mobile
access
TRILLIONS OF
[J. Rabaey, ASPDAC’08]
CONNECTED DEVICES
The Age of CyberPhysical Systems
Looking Beyond the Devices
Complex collections of sensors,
controllers, compute and storage
nodes, and actuators that work
together to improve our daily lives
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It’s All About Energy
Mobiles
ud
Compute
Clo
Smart
grid
ory
Sens m
r
Swa
Energy
among
the
most
compelling
Avionics
concerns
of
distributed
IT
pla8orm
and
its
applica9ons
Human-‐centric
Intelligent
energy
management
at
systems
ALL
LEVELS
AND
SCALES
offers
tremendous
opportunity.
It Is All About Energy …
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DATACENTER
ENERGY
EFFICIENCY
Barroso
&
Hölzle,
2009
Dyer,
ITHERM
2006
Datacenter
energy
overhead,
ASHRAE
Data and Compute Centers
“The IT workhorses”
[Barroso, Holzle, 2007]
Doing Nothing
Well!
Major Opportunity is in Power Management
Requires Top-Down System Level Solution
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Mobiles
“The home of the user interface”
Most “tricks” already in use! (multi-core,
heterogeneity, accelerators, SoC, …)
Opportunity: system and
application considerations
Always-connected
Perceptual processing
4)
fo pad
(9
UCB
In
Mobile µProc Anno 2015
[Courtesy A. Peleg, Intel]
The Sensory Swarm
“Adding senses to the Internet”
The driver for
Telos Mote Ultra-Low Energy
design for past
Philips Sand module
decade
UCB PicoCube
IMEC e-Cube
UCB mm3 radio
[Ref: Ambient Intelligence, W. Weber Ed., 2005]
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Yet … True Immersion Still Out of Reach
Microscopic Wireless
Artificial Skin Interactive Surfaces
Smart Objects “Microscopic” Health Monitoring
Another leap in size, cost and energy reduction
Example: Microscopic Wireless to Power
Brain-Machine Interfaces (BMI)
The Age of Neuroscience
BMI – The Instrumentation of Neuroscience
• Learning about operation of the brain
• Enabling advanced prosthetics
• Enabling innovative human-machine
interfaces
mm3 nodes
remotely powered
uWs to 1 mW
power budget
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The Dream: Observing Living Cells
10-100
µm
Combines sensing,
processing, communication
and energy harvesting and
storage in volumes far less
than 1 mm
[Courtesy, Hillenius3 et al, 07]
The Holy Grail:
Reducing the Energy/Operation
CMOS digital
Non-CMOS
digital
Interfaces and
periphery
Long term musings
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Energy Limits in Digital
Shannon-Von Neumann-
Landauer Bound:
Minimum energy/
operation = kTln(2)
= 4.10-21J/bit at room
John Von Neumann temperature Claude Shannon
More than 4 orders of magnitude
below current practice (65 nm at 1V)
Technology Scaling Not the Solution
0.12
0.11
0.1
EOP (fJ)
0.09
0.08
0.07
0.06
0.05
0.04
0.03
20 30 40 50 60 70 80 90
Technology node (nm)
[Based on actual and predictive models]
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Lowering Supply Voltage Only Option
(recoup performance through parallelism)
BUT: CMOS Has Minimum Energy Point Set by Leakage
12x
Energy (norm.)
0.1
0.01
0.3V
0.001
0 0.2 0.4 0.6 0.8 1 1.2
VDD (V)
Sub-Threshold Operation Leads to Minimum
Energy/Operation Energy-Aware FFT Processor
[Chang, Chandrakasan, 2004]
Opti
ma
Supply Voltage
l (V dd
, V th
Energy
)
(VDD)
self-contained processors
Threshold Voltage (Vth)
Subliminal µprocessor for
retinal implants
3 pJ/inst @ 350 mV
[Blaauw, VLSI’07]
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How About Mechanical Computing?
ON: VGS > VPI – Low on resistance
OFF: VGS < VPI – Zero Leakage
NEMS Relay
[Courtesy: TJ King, E. Alon, UCB]
NEMS Relays Versus CMOS
Energy/op vs. Delay/op across Vdd
32-bit adder CMOS Relay
V
1V dd: Supply 0.5 V 0.32 - 0.9 V
0.5 Voltage
V
Load Cap 25 fF 25 fF
per Output
9x
Total Gate 4.0 pF 125 fF
Cap
10x Area 600 µm2 480 µm2
Enables the parallelism concept anew!
[CMOS Adder: D. Patil, ARITH'07]
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It May Even Work …
Operational XOR/ CarryGen
[E. Alon, TJ King et al, To be Published, ISSCC 2010]
Digital IC Design has been a tremendous success
story
Fueled by Moore’s Law
Design complexity has increased accordingly
Has been addressed by raising abstraction levels
Custom -> ASIC -> IP and System-on-a-Chip
Before: Area & Performance
Now: Area, Energy and Performance
Any successful system designer must have
insight in the design trade-off space
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