TPS54626

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4.5V to 18V Input, 6.5-A Synchronous Step-Down SWIFT™ Converter with ECO-Mode™
Check for Samples: TPS54626

1FEATURES DESCRIPTION
23 • D-CAP2™ Mode Enables Fast Transient The TPS54626 is an adaptive on-time D-CAP2™
Response mode synchronous Buck converter. The TPS54626
enables system designers to complete the suite of
• Low Output Ripple and Allows Ceramic Output various end equipment’s power bus regulators with a
Capacitor cost effective, low component count, low standby
• Wide Vin Input Voltage Range: 4.5 V to 18 V current solution. The main control loop for the
• Output Voltage Range: 0.76 V to 5.5 V TPS54626 uses the D-CAP2™ mode control which
provides a very fast transient response with no
• Highly Efficient Integrated FET’s Optimized for external components. The adoptive on-time control
Lower Duty Cycle Applications –36 mΩ (High supports seamless operation between PWM mode at
Side) and 28 mΩ (Low Side) heavy load condition and reduced frequency
• High Efficiency, less than 10 μA at shutdown operation at light load for high efficiency. The
TPS54626 also has a proprietary circuit that enables
• High Initial Bandgap Reference Accuracy
the device to adopt to both low equivalent series
• Adjustable Soft Start resistance (ESR) output capacitors, such as SP-CAP
• Pre-Biased Soft Start and ultra-low ESR ceramic capacitors. The device
• 650-kHz Switching Frequency (fSW) operates from 4.5-V to 18-V VIN input power supply
voltage. The output voltage can be programmed
• Cycle By Cycle Over Current Limit between 0.76 V and 5.5 V. The device also features
• Power Good Output an adjustable soft start time and a power good
• Auto-Skip Eco-mode™ for High Efficiency at function. The TPS54626 is available in the 14 pin
Light Load HTSSOP package, designed to operate from –40℃
to 85℃.
APPLICATIONS
Io = 50 mA – 6.5 A
• Wide Range of Applications for Low Voltage S/R = 0.35 A/μs
System Vo (50 mV/div)
– Digital TV Power Supply
– High Definition Blu-ray Disc™ Players
– Networking Home Terminal Io (2 A/div)

– Digital Set Top Box (STB)

U1
TPS54626PWP

Time (100 μs/div)

L004_SLVSC34

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 D-CAP2, Eco-mode are trademarks of Texas Instruments.
3 Blu-ray Disc is a trademark of Blu-ray Disc Association.
PRODUCTION DATA information is current as of publication date. Copyright © 2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS54626
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION (1)

(2) (3)
TA PACKAGE ORDERABLE PART NUMBER PIN TRANSPORT MEDIA
TPS54626PWP Tube
–45°C to 85°C PWP 14
TPS54626PWPR Tape and Reel

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) All package options have Cu NIPDAU lead/ball finish.

ABSOLUTE MAXIMUM RATINGS

(1)
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
MIN MAX
VIN1, VIN2, EN –0.3 20 V
VBST –0.3 26 V
VBST (10 ns transient) –0.3 28 V
VI Input voltage range VBST (vs Sw1, SW2) –0.3 6.5 V
VFB, VO, SS, PG –0.3 6.5 V
SW1, SW2 –2 20 V
SW1, SW2 (10 ns transient) –3 22 V
VREG5 –0.3 6.5 V
VO Output voltage range
PGND1, PGND2 –0.3 0.3 V
Vdiff Voltage from GND to POWERPAD –0.2 0.2 V
Human Body Model (HBM) 2 kV
ESD rating Electrostatic discharge
Charged Device Model (CDM) 500 V
TJ Operating junction temperature –40 150 °C
Tstg Storage temperature –55 150 °C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

THERMAL INFORMATION
TPS54626
THERMAL METRIC (1) UNITS
PWP (14 PINS)
θJA Junction-to-ambient thermal resistance 40.5
θJCtop Junction-to-case (top) thermal resistance 28.7
θJB Junction-to-board thermal resistance 24.2
°C/W
ψJT Junction-to-top characterization parameter 0.8
ψJB Junction-to-board characterization parameter 23.9
θJCbot Junction-to-case (bottom) thermal resistance 2.4

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

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RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VIN Supply input voltage range 4.5 18 V
VBST –0.1 24
VBST (10 ns transient) –0.1 27
VBST (vs SW) –0.1 6.0
SS, PG –0.1 5.7
VI Input voltage range EN –0.1 18 V
VO, VFB –0.1 5.5
SW1, SW2 –1.8 18
SW1, SW2 (10 ns transient) –3 21
PGND1, PGND2 –0.1 0.1
VO Output voltage range VREG5 –0.1 5.7 V
IO Output Current range IVREG5 0 5 mA
RPG Power Good resistor 25 150 kΩ
TA Operating free-air temperature –40 85 °C
TJ Operating junction temperature –40 150 °C

ELECTRICAL CHARACTERISTICS
over operating free-air temperature range, VIN = 12V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
VIN current, TA = 25°C, EN = 5 V,
IVIN Operating - non-switching supply current 950 1400 μA
VVFB = 0.8 V
IVINSDN Shutdown supply current VIN current, TA = 25°C, EN = 0 V 3.6 10 μA
LOGIC THRESHOLD
VENH EN high-level input voltage En 1.6 V
VENL EN low-level input voltage EN 0.6 V
REN EN pin resistance to GND VEN = 12 V 200 400 800 kΩ
VFB VOLTAGE AND DISCHARGE RESISTANCE
VFB voltage light load mode, TA = 25°C,
772
VO = 1.05 V, IO = 10mA
TA = 25°C, VO = 1.05 V, continuous mode 757 765 773
VFBTH VFB threshold voltage TA = 0°C to 85°C, VO = 1.05 V, continuous mV
753 777
mode (1)
TA = –40°C to 85°C, VO = 1.05 V, continuous
751 779
mode (1)
IVFB VFB input current VVFB = 0.8 V, TA = 25°C 0 ±0.15 μA
RDischg VO discharge resistance VEN = 0 V, VO = 0.5 V, TA = 25°C 100 150 Ω
VREG5 OUTPUT
TA = 25°C, 6 V < VIN < 18 V,
VVREG5 VREG5 output voltage 5.2 5.5 5.7 V
0 < IVREG5 < 5 mA
IVREG5 Output current VIN = 6 V, VVREG5 = 4 V, TA = 25°C 20 mA
MOSFET
Rdsonh High side switch resistance TA = 25°C, VBST-SW1,2 = 5.5V 36 mΩ
Rdsonl Low side switch resistance TA = 25°C 28 mΩ

(1) Not production tested.

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ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range, VIN = 12V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CURRENT LIMIT
Iocl Current limit L = 1.5 μH (2), 7.2 8.2 9.5 A
THERMAL SHUTDOWN
(2)
Shutdown temperature 165
TSDN Thermal shutdown threshold (2)
°C
Hysteresis 35
ON-TIME TIMER CONTROL
TON On time VIN = 12 V, VO = 1.05 V 150 ns
TOFF(MIN) Minimum off time TA = 25°C, VFB = 0.7 V 260 310 ns
SOFT START
ISSC SS charge current VSS = 1.0 V 4.2 6.0 7.8 μA
ISSD SS discharge current VSS = 0.5 V 1.5 3.3 mA
POWER GOOD
VVFB rising (good) 85% 90% 95%
VTHPG PG threshold
VVFB falling (fault) 85%
IPG PG sink current VPG = 0.5 V 2.5 5 mA
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VOVP Output OVP trip threshold OVP detect 120% 125% 130%
TOVPDEL Output OVP prop delay 10 μs
UVP detect 60% 65% 70%
VUVP Output UVP trip threshold
Hysteresis 10%
TUVPDEL Output UVP delay 0.25 ms
TUVPEN Output UVP enable delay Relative to soft-start time X 1.7
UVLO
Wake up VREG5 voltage 3.45 3.75 4.05
VUVLO UVLO threshold V
Hysteresis VREG5 voltage 0.13 0.32 0.48

(2) Not production tested.

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DEVICE INFORMATION
PWP PACKAGE
(TOP VIEW)

VO 1 14 VIN2

VFB 2 13 VIN1

VREG5 3 12 VBST

SS 4 POWER PAD 11 SW2

GND 5 10 SW1

6
PG 9 PGND2

EN 7 8 PGND1

PIN FUNCTIONS
PIN
DESCRIPTION
NAME NUMBER
VO 1 Connect to output of converter. This pin is used for output discharge function.
VFB 2 Converter feedback input. Connect with feedback resistor divider.
5.5V power supply output. A Capacitor (typical 1µF) should be connected to GND. VREG5 is not active
VREG5 3
when EN is low.
SS 4 Soft start control. An external capacitor should be connected to GND.
GND 5 Signal ground pin.
PG 6 Open drain power good output
EN 7 Enable control input. EN is active high and must be pulled up to enable the device.
PGND1, Ground returns for low-side MOSFET. Also serve as inputs of current comparators. Connect PGND and
8, 9
PGND2 GND strongly together near the IC.
Switch node connection between high-side NFET and low-side NFET. Also serve as inputs to current
SW1, SW2 10,11
comparator.
Supply input for high-side NFET gate driver (boost terminal). Connect capacitor from this pin to respective
VBST 12
SW1,SW2 terminals. An internal PN diode is connected between VREG5 and VBST pin.
VIN1,VIN2 13,14 Power Input and connected to high side NFET drain.
Supply Input for 5V internal linear regulator for the control circuitry
Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Should be connected to
PowerPAD™ Back side
PGND

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FUNCTIONAL BLOCK DIAGRAM (HTSSOP)

-35% UV

VIN
VIN2
14

VIN1
OV 13
1
VO +25%
VREG5

VBST
12
Control logic

Ref
SS 1 shot
SW2 VO
11
2
VFB XCON SW1
10
VREG5
SGND VREG5 Ceramic
3 Capacitor

SS PGND2
9
1mF 4
8
PGND1
Softstart SW
PGND SS ZC
PGND
5 GND
SW
OCP
SGND Ref VIN
PGND
6
PG -10%
UV

VREG5 OV Protection
UVLO UVLO Logic
EN
7
EN TSD
Logic REF Ref

OVERVIEW
The TPS54626 is a 6.5-A synchronous step-down (buck) converter with two integrated N-channel MOSFETs and
auto-skip Eco-mode™ to improve light lode efficiency. It operates using D-CAP2™ mode control. The fast
transient response of D-CAP2™ control reduces the output capacitance required to meet a specific level of
performance. Proprietary internal circuitry allows the use of low ESR output capacitors including ceramic and
special polymer types.

DETAILED DESCRIPTION

PWM Operation
The main control loop of the TPS54626 is an adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP2™ mode control. D-CAP2™ mode control combines constant on-time control with
an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low ESR and ceramic output capacitors. It is stable with virtually no ripple at the output.

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At the beginning of each cycle, the high-side MOSFET is turned on. The MOSFET is turned off after the internal
one-shot timer expires. The one-shot timer is set by the converter input voltage, VIN, and the output voltage, VO,
to maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control.
The one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below
the reference voltage. An internal ramp is added to reference voltage to simulate output ripple, eliminating the
need for ESR induced output ripple from D-CAP2™ mode control.

PWM Frequency and Adaptive On-Time Control

TPS54626 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The
TPS54626 runs with a pseudo-constant frequency of 650 kHz by using the input voltage and output voltage to
set the on-time one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the
output voltage. Therefore, when duty ratio is VOUT/VIN, the frequency is constant.

Auto-Skip Eco-Mode™ Control

The TPS54626 is designed with Auto-Skip mode to increase light load efficiency. As the output current
decreases from heavy load condition, the inductor current is also reduced and eventually comes to point that its
rippled valley touches zero level, which is the boundary between continuous conduction and discontinuous
conduction modes. The rectifying MOSFET is turned off when its zero inductor current is detected. As the load
current further decreases the converter run into discontinuous conduction mode. The on-time is kept almost the
same as is was in the continuous conduction mode so that it takes longer time to discharge the output capacitor
with smaller load current to the level of the reference voltage. The transition point to the light load operation
IOUT(LL) current can be calculated in Equation 1.

IOUT(LL) =
1 (V -V )×VOUT
× IN OUT
2×L×fSW VIN (1)

Soft Start and Pre-Biased Soft Start

The soft start function is adjustable. When the EN pin becomes high, 6 μA current begins charging the capacitor
which is connected from the SS pin to GND. Smooth control of the output voltage is maintained during start up.
The equation for the slow start time is shown in Equation 2. VFB voltage is 0.765 V and SS pin source current is
6 μA.
CSS (nF) x VREF ´1.1 CSS (nF) x 0.765 ´1.1
t (ms) = =
SS I (mA) 6
SS (2)
TPS54626 contains a unique circuit to prevent current from being pulled from the output during startup if the
output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft-start
becomes greater than feedback voltage VFB), the controller slowly activates synchronous rectification by starting
the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a cycle-by-
cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter. This
scheme prevents the initial sinking of the pre-bias output, and ensure that the out voltage (VO) starts and ramps
up smoothly into regulation and the control loop is given time to transition from pre-biased start-up to normal
mode operation.

Power Good
The TPS54626 has power good open drain output. The power-good function is activated after soft start has
finished. The power good function becomes active after 1.7 times soft-start time. When the output voltage
becomes within –10% of the target value, internal comparators detect power good state and the power good
signal becomes high. Rpg resistor value, which is connected between PG and VREG5, is required from 25kΩ to
150kΩ. If the feedback voltage goes under 15% of the target value, the power good signal becomes low.

Output Discharge Control

TPS54626 discharges the output when EN is low, or the controller is turned off by the protection functions (OVP,
UVP, UVLO and thermal shutdown). The device discharges the output using an internal 100-Ω MOSFET which is
connected from VO to PGND. The internal low-side MOSFET is not turned on during the output discharge
operation to avoid the possibility of causing negative voltage at the output.

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Current Protection
The output over-current protection (OCP) is implemented using a cycle-by-cycle valley detect control circuit. The
switch current is monitored by measuring the low-side FET switch voltage between the SW pin and GND. This
voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature
compensated.
During the on time of the high-side FET switch, the switch current increases at a linear rate determined by Vin,
Vout, the on-time and the output inductor value. During the on time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current Iout. If the measured voltage is
above the voltage proportional to the current limit, then the device constantly monitors the low side FET switch
voltage, which is proportional to the switch current, during the low-side on-time.
The converter maintains the low-side switch on until the measured voltage is below the voltage corresponding to
the current limit at which time the switching cycle is terminated and new switching cycle begins. IN subsequent
switching cycles, the on-time is set to fixed value and the current is monitored in the same manner.
There are some important considerations for this type of over-current protection. The load current one half of the
peak-to-peak inductor current is higher than the over-current threshold. Also, when the current is being limited,
the output voltage tends to fall as the demanded load current may be higher than the current available from the
converter. This may cause the output under-voltage protection circuit to be activated. This protection itself is non-
latching.

Over/Under Voltage Protection

TPS54626 detects over and under voltage conditions by monitoring the feedback voltage (VFB). This function is
enabled after approximately 1.7 x times the softstart time.
When the feedback voltage becomes higher than 125% of the target voltage, the OVP comparator output goes
high and the circuit latches and both the high-side MOSFET driver and the low-side MOSFET driver turn off.
When the feedback voltage becomes lower than 65% of the target voltage, the UVP comparator output goes
high and an internal UVP delay counter begins. After 250us, the device latches off both internal top and bottom
MOSFET.

UVLO Protection
Under voltage lock out protection (UVLO) monitors the voltage of the VREG5 pin. When the VREG5 voltage is lower
than UVLO threshold voltage, the TPS54626 is shut off. This is protection is non-latching.

Thermal Shutdown
Thermal protection is self-activating. If the junction temperature exceeds the threshold value (typically 165°C),
the TPS54626 is shut off. This protection is non-latching.

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TYPICAL CHARACTERISTICS
VIN = 12 V, TA = 25 °C (unless otherwise noted)
Vin CURRENT Vin SHUTDOWN CURRENT
vs vs
JUNCTION TEMPERATURE JUNCTION TEMPERATURE
1200 14
EN = 0 V

12
1000

10

Shutdown Current (A)

800
Supply Current (A)

8
600
6

400
4

200
2

EN = 5 V Vin = 12 V Vin = 12 V
0 0
±50 0 50 100 150 ±50 0 50 100 150
Junction Temperature (ƒC) Junction Temperature (ƒC)
C001 C002

Figure 1. Figure 2.

EN CURRENT 1.05V OUTPUT VOLTAGE

vs vs
EN VOLTAGE OUTPUT CURRENT
50 1.100
Vin = 12 V Vo = 1.05 V
45

40
1.075
35
EN Input Current (A)

Output Voltage (V)

30

25 1.050

20

15
1.025
10
Vin = 5 V
5
Vin = 12 V
Vin = 18 V
0 1.000
0 5 10 15 20 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
EN Input Voltage (V) Output Current (A)
C003 C004

Figure 3. Figure 4.

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TYPICAL CHARACTERISTICS (continued)

VIN = 12 V, TA = 25 °C (unless otherwise noted)
1.05V OUTPUT VOLTAGE
vs
INPUT VOLTAGE 1.05 V 0.05A to 6.5A LOAD TRANSIENT RESPONSE
1.10
Io = 50 mA – 6.5 A
S/R = 0.35 A/μs
1.09
Vo (50 mV/div)
1.08

1.07
Io (2 A/div)
Output Voltage (V)

1.06

1.05

1.04

1.03

1.02

Io = 10 mA
1.01
Io = 1 A
1.00
0 5 10 15 20 Time (100 μs/div)
L004_SLVSC34
Input Voltage (V)
C005

Figure 5. Figure 6.

STARTUP WAVEFORM EFFICIENCY vs OUTPUT CURRENT

100
EN (10 V/div) Vi = 12 V

90

VREG (5 V/div)
80
Efficiency (%)

70

Vo (0.5 V/div)
60

50
Io = 0 A Vo = 1.8 V
Css = 8200 pF Vo = 3.3 V
Vo = 5 V
40
Time (1 ms/div) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5
L003_SLVSC34
Output Current (A)
C006

Figure 7. Figure 8.

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TYPICAL CHARACTERISTICS (continued)

VIN = 12 V, TA = 25 °C (unless otherwise noted)
LIGHT LOAD EFFICIENCY SWITCHING FREQUENCY
vs vs
OUTPUT CURRENT INPUT VOLTAGE (IO=1A)
100 850
Vi = 12 V
90 800

80
750

Switching Frequency (kHz)

70
700
60
Efficiency (%)

650
50
600
40
550 Vo = 1.05 V
30 Vo = 1.2 V
500 Vo = 1.5 V
20
Vo = 1.8 V
Vo = 1.8 V 450 Vo = 2.5 V
10
Vo = 3.3 V Vo = 3.3 V
Vo = 5 V Vo = 5 V
0 400
0.001 0.01 0.1 0 5 10 15 20
Output Current (A) Input Voltage (V)
C007 C008

Figure 9. Figure 10.

SWITCHING FREQUENCY
vs
OUTPUT CURRENT VFB VOLTAGE vs JUNCTION TEMPERATURE
900 0.780
Vin = 12 V
Io = 1 A
800
0.775
700
Switching Frequency (kHz)

600 0.770
VFB Voltage (V)

500
0.765
400

300 0.760

200
Vo=1.05V 0.755
100 Vo=1.8V
Vo=3.3V VFB
0 0.750
0.01 0.1 1 10 ±50 0 50 100 150
Output Current (A) Junction Temperature (ƒC)
C009 C010

Figure 11. Figure 12.

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TYPICAL CHARACTERISTICS (continued)

VIN = 12 V, TA = 25 °C (unless otherwise noted)
OUTPUT CURRENT
vs
AMBIENT TEMPERATURE VOLTAGE RIPPLE AT INTPUT (IO=6.5A)
7
Vo = 1.05 V
Io = 6.5 A
6
Vi (50 mV/div)

5
Output Current (A)

3 SW (5 V/div)

2 Vo = 1.05 V
Vo = 1.8 V
1 Vo = 2.5 V
Vo = 3.3 V
Vo = 5 V
0
0 20 40 60 80 100 Time (1 ms/div)
L001_SLVSC34
Ambient Temperature (ƒC)
C011

Figure 13. Figure 14.

VOLTAGE RIPPLE AT OUTPUT (IO=6.5A)

Vo = 1.05 V
Io = 6.5 A

Vo (10 mV/div)

SW (5 V/div)

Time (100 μs/div)

L002_SLVSC34

Figure 15.

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DESIGN GUIDE

Step By Step Design Procedure

To begin the design process, you must know a few application parameters:
• Input voltage range
• Output voltage
• Output current
• Output voltage ripple
• Input voltage ripple

U1
TPS54626PWP 1.05V, 6.5A

Figure 16. Schematic

Output Voltage Resistors Selection

The output voltage is set with a resistor divider from the output node to the VFB pin. It is recommended to use
1% tolerance or better divider resistors. Start by using Equation 3 to calculate VOUT
To improve efficiency at very light loads consider using larger value resistors, too high of resistance will be more
susceptible to noise and voltage errors from the VFB input current will be more noticeable.
R1
VOUT = 0.765 • 1 + −
R2 ( ) (3)

Output Filter Selection

The output filter used with the TPS54626 is an LC circuit. This LC filter has double pole at:
1
FP =
2p LOUT ´ COUT (4)
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the TPS54626. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls
off at a -40 dB per decade rate and the phase drops rapidly. D-CAP2™ introduces a high frequency zero that
reduces the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade above the
zero frequency. The inductor and capacitor selected for the output filter must be selected so that the double pole
of Equation 4 is located below the high frequency zero but close enough that the phase boost provided be the
high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the
values recommended in Table 1

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Table 1. Recommended Component Values

Output Voltage (V) R1 (kΩ) R2 (kΩ) C4 (pF) (1) L1 (µH) C8 + C9 (µF)
1 6.81 22.1 5 - 220 1.0 - 1.5 - 4.7 22 - 68
1.05 8.25 22.1 5 - 220 1.0 - 1.5 - 4.7 22 - 68
1.2 12.7 22.1 5 - 100 1.0 - 1.5 - 4.7 22 - 68
1.5 21.5 22.1 5 - 68 1.0 - 1.5 - 4.7 22 - 68
1.8 30.1 22.1 5 - 22 1.2 - 1.5 - 4.7 22 - 68
2.5 49.9 22.1 5 - 22 1.5 - 2.2 – 4.7 22 - 68
3.3 73.2 22.1 5 - 22 1.8 - 2.2 – 4.7 22 - 68
5 124 22.1 5 - 22 2.5 - 3.3 – 4.7 22 - 68

(1) Optional

For higher output voltages at or above 1.8 V, additional phase boost can be achieved by adding a feed forward
capacitor (C4) in parallel with R1.
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 5,
Equation 6 and Equation 7. The inductor saturation current rating must be greater than the calculated peak
current and the RMS or heating current rating must be greater than the calculated RMS current. Use 650 kHz for
fSW.
Use 650 kHz for fSW. and also use 1.5µH for LO Make sure the chosen inductor is rated for the peak current of
Equation 6 and the RMS current of Equation 7.
VOUT VIN (max) - VOUT
Ilp - p = V¾ · ¾
L ·f
IN (max) O SW (5)
Ilp - p
Ilpeak = IO + 
2 (6)
−
√
ILo(RMS) = IO2 + − 1 Ilp - p2
12 (7)
For this design example, the calculated peak current is 7.01 A and the calculated RMS current is 6.51 A. The
inductor used is a TDK SPM6530-1R5M100 with a peak current rating of 11.5 A and an RMS current rating of 11
A.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS54626 is intended for use
with ceramic or other low ESR capacitors. Recommended values range from 22µF to 68µF. Use Equation 8 to
determine the required RMS current rating for the output capacitor
VOUT • (VIN - VOUT)
ICO(RMS) =−−
√12 • VIN • LO • fSW (8)
For this design two TDK C3216X5R0J226M 22µF output capacitors are used. The typical ESR is 2 mΩ each.
The calculated RMS current is 0.284 A and each output capacitor is rated for 4 A.

Input Capacitor Selection

The TPS54626 requires an input decoupling capacitor and a bulk capacitor is needed depending on the
application. A ceramic capacitor over 10 uF. is recommended for the decoupling capacitor. An additional 0.1 µF
capacitor from pin 14 to ground is recommended to improve the stability of the over-current limit function. The
capacitor voltage rating needs to be greater than the maximum input voltage.

Bootstrap Capacitor Selection

A 0.1-μF ceramic capacitor must be connected between the VBST to SW pin for proper operation. It is
recommended to use a ceramic capacitor.

VREG5 Capacitor Selection

A 1-μF ceramic capacitor must be connected between the VREG5 to GND pin for proper operation. It is
recommended to use a ceramic capacitor.
14 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated

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 TPS54626
www.ti.com SLVSC34 – AUGUST 2013

THERMAL INFORMATION
This PowerPad™ package incorporates an exposed thermal pad that is designed to be directly to an external
heatsink. The thermal pad must be soldered directly to the printed board (PCB). After soldering, the PCB can be
used as a heatsink. In addition, through the use of thermal vias, the thermal pad can be attached directly to the
appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be attached to a
special heatsink structure designed into the PCB. This design optimizes the heat transfer from the integrated
circuit (IC).
For additional information on the PowerPAD™ package and how to use the advantage of its heat dissipating
abilities, refer to Technical Brief, PowerPAD™ Thermally Enhanced Package, Texas Instruments Literature No.
SLMA002 and Application Brief, PowerPAD™ Made Easy, Texas Instruments Literature No. SLMA004.
The exposed thermal pad dimensions for this package are shown in the following illustration.
14 8

Thermal Pad
2.46

°
1 7
2.31

Figure 17. Thermal Pad Dimensions

Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 15

Product Folder Links: TPS54626
TPS54626
SLVSC34 – AUGUST 2013 www.ti.com

LAYOUT CONSIDERATIONS
1. A top side area should be filled with ground as much as possible due to relatively higher current output
device.
2. The ground area under the device thermal pad should be large as possible and directly connect to the
thermal pad. Also 2nd, 3rd and 4th PCB layer should be connected to ground directly from the thermal pad.
3. Keep the input switching current loop as small as possible.
4. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and
inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the
feedback pin of the device.
5. Keep analog and non-switching components away from switching components.
6. Make a single point connection from the signal ground to power ground.
7. Do not allow switching current to flow under the device.
8. Keep the pattern lines for VIN and PGND broad.
9. Exposed pad of device must be connected to PGND with solder.
10. VREG5 capacitor should be placed near the device, and connected PGND.
11. Output capacitor should be connected to a broad pattern of the PGND.
12. Voltage feedback loop should be as short as possible, and preferably with ground shield.
13. Lower resistor of the voltage divider which is connected to the VFB pin should be tied to SGND.
14. Providing sufficient via is preferable for VIN, SW and PGND connection.
15. PCB pattern for VIN, SW, and PGND should be as broad as possible.
16. VIN Capacitor should be placed as near as possible to the device.

VIN
Additional
Thermal VIN
Vias VIN OVER
CURRENT INPUT
STABILITY
CAPACITOR BYPASS
CAPACITOR

FEEDBACK EXPOSED
RESISTORS VOUT POWERPAD VIN2
AREA

VFB VIN1
BOOST
VREG5 VBST CAPACITOR
VOUT
BIAS SS SW1
CAP
GND SW2 OUTPUT
INDUCTOR OUTPUT
PG PGND1
SLOW FILTER
START CAPACITOR
CAP EN PGND2
Connection to
POWER GROUND
on internal or ANALOG Additional
bottom layer GROUND Thermal
TRACE Vias

To Enable
Control
POWER GROUND

VIA to Ground Plane

Etch on Bottom Layer
or Under Component
Figure 18. PCB Layout for PWP Package
16 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated

Product Folder Links: TPS54626

 PACKAGE OPTION ADDENDUM

www.ti.com 22-Aug-2013

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (3) (4/5)

TPS54626PWP ACTIVE HTSSOP PWP 14 90 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 PS54626
& no Sb/Br)
TPS54626PWPR ACTIVE HTSSOP PWP 14 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 PS54626
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 22-Aug-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS54626PWPR HTSSOP PWP 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 22-Aug-2013

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS54626PWPR HTSSOP PWP 14 2000 367.0 367.0 35.0

Pack Materials-Page 2
 IMPORTANT NOTICE
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