D-A ANDA-D CONVERTERS

10.1 INTRODUCTION
Most of the real-world physical quantities such as voltage, current,temperature, pressure
and time etc. are availablein analog form. Even though an analog signal represents a real
physical parameter with accuracy,it is difficult to process, store or transmit the analog
signal without introducing considerable error because of the superim-position of noise as in
the case of amplitude modulation. Therefore, for processing, transmission and storagepurposes,
it is often convenient to express these variables in digital form. It gives better accuracyand
reduces noise. The operation of any digital communication system is based upon analog to
digital (AD) and digital to analog (D/A) conversion.
Figure 10.1 highlightsa typicalapplication within which A/D and D/A conversion is used.
The analog signal obtained from the transducer is band limited by antialiasing filter. The
signal is then sampled at a frequency rate more than twice the maximum frequency of the
band limited signal. The sampled signal has to be held constant while conversion is taking
place in AD [Link] requires that ADC should be preceded by a sample and hold
(S/H) circuit. The ADC output is a sequence in binary. digit. The micro-computer or digital
signal processor performs the numerical calculations of the desired control [Link]
D/A converter is to convert digital signal into analog and hence the function of DAC is
exactly opposite to that of [Link] D/A converteris usually operated at thesame frequency
as the ADC. The output of a D/A converter is commonly a staircase. This staircase-like
digital output is passed through a smoothing filter to reduce the effect of quantizationnoise.

Sensor or Analog Band limited

Analog to Discrete
Antialíasing Sample Discrete,

Transducer filter analog & hold digital

signal signal analog
converter digital
Computer
or digital
signal
PLANT
processor
Staircase signal Digital binary
Analog signal Smoothing D-A signal
filter
converter

Fig. 10.1 Circuit showing application of A/D and D/A converter

 The scheme given in Fig. 10.1 is used either in fullor in part in applications such as
digital audio recording and playback, computer, music and video synthesis, pulse code
modulation transmission, data acquisition, digital digital
multimeter, direct digital control,
signal processing,
microprocessor based instrumentation.
Both ADC
and DAC are also known as data converters and are available in I Torm.
may be mentioned here that for slowly varving signal sometimes sample and hold crcub
may be avoided without considerable error The A-D conversion usually makes use of a
D-A converter so we shall first discuss
DAC followed by ADC.
L0.2 BASIC DAC TECHNIQUES 10
The schematic of a DAC
is shown
in Fig. 10.2.
o Va
The input is an n-bit
binary word D and is combined
with Chapter
(MSB)
a reference voltage V
to give an
d,

Analog output [Link]

output of Binary
DAC
DAC can be either a voltage or Word D
d, d
current. For a voltage output DAC, (LSB)
he D/A converter ismathematically
described as Fig. 10,2 Schematic of a DAC
V, = KVs(d,2+d,2 +...+ d,2) (10.1)
where, V =óutpút voltage
Vs = full scale output voltage
K= scaling factor usually adjusted to unity
d,d... d,=n-bit binary fractional word with the decimal
point located at the left
d, =most significant bit (MSB)with a
weight of Vrs/2
d, = least significantbit (LSB)
with a weight of Vrs/2"
There are various ways to implement Eq.
(10.1). Here we shall discuss the
following
esistive techniquesonly:
Weighted resistor DAC
R-2R ladder
Inverted R-2R ladder

0.2.1 Weighted Resistor DAC

ne of the simplest
eighted
circuits shown in Fig. 10.3 (a) uses a summing

resistor network. It has n-electronicswitches d, dg,

put word. These switches are single pole double
amplifier with a bìnary
d controlled by binary
throw (SPDT)type. If the binary input to
,
articular switch is 1, it connects the resistanee to the reference
voitage And if the (-).
Put bit is 0, the switch connects the resistor to the ground. Fron Fig. i0,3 (a), the output
I,for an ideal op-amp can be written
.t
Trent tS

I, = I, + I, +

VRd
2R t22R 2" R
 R

$2'R
2'R
GiMse)
d,(LSB)

(a)
andno
boje

0o 001 010 011 100 101 110 111

Digital input code t

(b)

Fig. 10.3 (a) A simple weighted resistor DAC (b) Transfer characteristics of a 3-bit DAC

VR (d,2-l + d,2-2 +...+ d,2-n)

R
The output voltage

V, =1R,= VR
R -(dh 2-1+ d, +...+d, (10.2)
R 2-2 2-")

Comparing Eq. (10.1) with Eq. (10.2), it can be seen that if R =R then K = 1 and

VFS = VR:
The circuit shown in Fig. 10.3 (a) uses a negative reference voltage. The analog output
voltage is therefore positive staircase as shown in Fig. 10.3 (b) for a 3-bit weighte resistor

DAC. It may be noted that

(1) Although the op-amp in Fig. 10.3 (a) is connected in inverting mode, it cat also be
connected in non-inverting mode.
(ii) The op-amp is simply working as.a current to voltage converter.
(i1i) The polarityof the referencevoltage is chosen in accordance with the type of the switeh
used. For example, for TTL compatible switches, the reference voltage should be +5
and the output will be negative.
 The accuracy and stability of a DAC depends upon the accuracy of the resistors and the
tracking ot each other with temperature. There arehowever a number of problems associated
with this type of [Link] of the disadvantages of binary weighted type DAC is the wide
range of resistor values required. It may be observed that forbetter resolution, the input
binary word length has to be [Link], as the number of bit increases, the rangeof
resistance value [Link] 8-bit DAC, the resistors reauired are 2'R, 2'R, 2R, .., 2K.

The largest resistor is 128 times the smallest one for only 8-bit DAC. For a 12-bit DAC, the
largest resistance required is 5.12 MQ
if the smallest is 2.5 ko. The fabrication of such a
large resistance in IC is not practical. Also the voltage drop across such a large resistor due
to tne bias current would also affect the accuracy. The choice of smallest resistor value as 10
2.0 k2is reasonable;otherwise loading effect wil be there. The difficulty of achieving and
mantaining accurate ratios over such a wide range especially in monolithic form restricts
the use of weighted resistor DACs to below
8-bits.
The switches in Fig. 10.3 (a) are in series with resistors and therefore,their on
resistance Chapter

must be very low and they should have zero offset voltage. Bipolar transistorsdo not
perform
well as voltage switches, due to the inherent offset voltage
when in saturation. However, by
using MOSFET, this can be achieved.
Different types of digitally controlled SPDT electronic switches are available of
which two
are shown in Fig. 10.4. A totem-pole MOSFET driver in Fig.
10.4 (a)feeds each resistor
connected to the inverting input terminal 'a' of Fig. 10.3 (a).
The two complementary gate
inputs Q and Q come from MOSFET S-R flip-flop or a binary cell
of a register which holds
one bit of the digital information to be converted to an
analog number. Assume a negative
logic, i.e. logic 1 corresponds to -
10 V and logic '0 corresponds to zero volt. If there is 1
in the bit line, S= 1 and R =
0 so that and Q Q=1 =
0. This drives the transistor Q, on,
thus connecting the resistor R, to the reference
voltage -V
whereas the transistor Q2
remains off. Similarly a 0
at the bit line connects the resistor R, to the ground
terminal.
Another SPDT switch of Fig. 10.4(b) consists of CMOS
inverter feeding an op-amp voltage
follower which drives R,from a very low output
resistance. The circuit is using a positive
logic with V(1) = V= =
+5 V and V(0) 0 V. The complement Q of the bit under consideration
is applied at the input. Thus Q =
0 makes transistor off and on. The output of the
CMOS inverter is at logic 1, that is, 5V
is applied to resstor F through the
voltage follower.
|And if Q =1 the output of the CMOS inverter is 0 V cinzsng the
reitance2 to und.

V(-10v)

Bit line

R R,
R
Wa
Op-amp
input line Op-amp
input line
(a)

(b)

Fig. 10.4 (a) A totem pole MOSFET switch (b) CMOS Inverter as Switch
10.2.2 R-2R Ladder DAC
resistor type DAC,
Wide range of are required in binary weighted
resistors This can
are be
avoided by using R-2R ladder type DAC where only two values of resistors required. It
1S well suited for integrated circuit realization. The typical value of K ranges from 25
to 10 kQ.
For simplicity, consider a 3-bit DAC as shown in Fig. 10.5 (a), where the switch
position

d, dy d, corresponds tothe binary word 100. The circuit can be simplified to the
equivalent
form 10.5 (b) and Then, voltage at node C can be
of Fig. to finally Fig. 10.5 (c). easily

calculated by the set procedure of network analysis as

2R + R
3
4

The output voltage is

-2R( VES
V, =
R 4 2 2

2R

R
R R
+ <
Vo
2R 2R 2R $2R
(LSB) (MSB)
d,-0 d,=0 d,=1

-o -V
(a)

w
2R
R R CR
2R 2R 2R Vo
2R

(b)

2R R
2R

Fla, 10.5 (a) R-2R ladder

(c)
R
DAC (b) Equlvalent circult of (a), (c) Equlvalent circuit of (b)
 The switch position corresponding to the binary word 001 in 3 bit DAC is shown in Fig
10.6 (a).1he circuit can be simplified to the eguivalent form of Fig. 10.6 (b). The voltages
at the nodes (A, B, C) formed by resistor branches are easilv calculated in a similar fashion
and the output voltage becomes

2R
V, =( R VRVES
16 8

2R 10

Š2R 2R
,d,-1
R

TT 2R
R

d,=0
S2R
d,=0
R

+ V -VR
2R
A

2R
R

2R
R

2R
R
2R

Chapter

-o -VR
(a) (b)

Fig. 10.6 (a) R-2R ladder DAC for switch positions 001 (b)Equivalent circuit

In a similar fashion, the output voltage for R-2R ladder type DAC corresponding to
other
3-bit binary words can be calculated.

10.2.3 Inverted R-2R Ladder

In weighted resistor type DAC and R-2R ladder type DAC, current flowing in the resistors
changes as the input data changes. More power dissipation causes heating, which in turn,
creates non-linearity in DAC. This is a serious problem and can be avoided
completely in
Inverted R-2R ladder type DAC. A 3-bit Inverted R-2R ladder type DAC is shown in Fig.
10.7 (a) where the position of MSB and LSB is interchanged. Here
each input binary word
Connectsthe corresponding switch either to ground or to the inverting input terminal of the
op-amp which is also at [Link] both the ierminals of switches d,are at ground
potential, current flowing in the resistancesis constant and independent of switch pOsition
ie. independent of input binary word. in Fig. 10.7 (a), when switch d, is at logical
the left. the current through 2R resistor flows to the ground and when
ie. to 0
the switch d is at
logical 1' ie.. to the right, the current through 2R sinks to the virtuai
ground. The cireuit
has the important property that the current divides equally at each of the nodes. This is
because the equivalent resistance tothe right or to the left of any node is exactly 2 R.
The
division of the current is shown in Fig. 10.7 (b). Consider a reference current of 2 mÀ.
hust
to the right of node A, the equivalent
resistor is 2 R. Thus 2 mA of reference input current

divides equally to value 1 mA at node [Link] to the right of node B, the eguivalent
resistor is R. Thus 1 mA
2 current further divides to value 0.5 mA at node
of
B. Similarly,
urrent divides equally at node C to 0.25 [Link] equal division of current in successiw
nodes remains the samne in the inverted R-2R ladder irrespective of the
input binary word.
hus the currents remain constant in each branch of the adder. Since constant curent
nplies constant voltage, the ladder node voltages remain constant at V/2°, V/21, V/92 Tho
rcuit works on the principleof summing currents and is also said to operate in the cument
 [Link] most important advantage of the current mode or inverted ladder is that since
the ladder node voltages remain constant even with changing input binary words (codes), the
performance of the
stray capacitances are not able to produce slow-down effects on the
circuit.

It may be noted that the switches used in Fig. 10.7 (a) are the SPDT switches discussed

earlier. Acording to bit d, the corresponding switch gets connected either to ground for d,
=0or to V for d, = 1. The current flows from inverting input terminal to –VR for = d 1

and from ground to -V for d; = 0. Regardless of the binary input word, the current in the
resistive branches of the inverted ladder circuit
remains always constant as explained in Fig.
10.7(6). However, the current through the feedback resistor is the summing current R
10.7 (b) shows
depending upon the input binary word. It may further be mentioned that, Fig.
only the current division for making the analysis simple, though it is a voltage driven
DAC.

-Vo
R R 2R

$2R 2R 2R
ld,(MSB) d (d,(LSB) R

(a)

A R B R 2R

2 mA 1 mA w 0.5 mA 0.25 mA
R
2R 2R
W2 mA 2R
1 mA d,=1
0.5 mA [d,=0 0.25 mA d,-0

(b)

Fig. 10.7 (a) Inverted R-2R ladder DAC (b) Inverted R-2R ladder DAC showingdivision
of current for digital input word 001

10.2.4 Multiplying DACS

Adigital to analog converter which uses a varying reference voltage V is called a multiplying
DIA converter (MDAC). Thus if in the Eq. (10.1), the reference voltage vg is a sine wavegiven
by
URlt) = Vim cos 2nft

Then, v,(t) = Vom cOs (2ft + 180°)

where Vom will vary from 0V to (1-2") depending upon the input code. When used
V,im, like

this,MDAC behaves as a digitally controlled audio attenuator because the output V, is a

 D-A and A-D Converters 355
fraction
of the
controlled by voltage representing the input digital code and the attenuator setting can be
digital logic.
programmable If by an op-amp integrator, the MDAC provides digitally
followed
oscillators, integration which can be used in the design of digitally
flters. programmable
10.2.5
MonolithicDAC
Monolithic
8, 10, DACS
12, 14 and 16
consisting of R-2R
with a current bìt ladder, switchesand the feedback
resistor are availablefor
resolution from
are hybrid [Link] various manufacturers. The MC 1408L is a 8-bit DAC
DIA SE/NE 5018 is also a 8-bit DAC but with
output.
converters available in
a voltage output. There 10
A
DATEL DAC-HZ series for current as well as
typical voltage
8-bit
ns is
shown in DAC 1408
2 mà referenceFig. 10.8(a). Itcompatible
with TTL and
has
CMOS logic with settling time around 300
(VEE Can range currentfor full input eight
data lines d,(MSB) through d,
(LSB). It requires
from -5 V to -15scale input and two power supplies Vcc = +5 V and VRE

Chapter
Rsa and
voltage V). The total reference V -5
match the referenceVR current source is determined by
and is equal to V/R4 =5 V/2.5 resistor
input
impedance of the kQ=[Link] resistor R1s F R14
reference source. The output current I,
is calculated as
VR

For full
R4 4-0or1
scale input
(i.e. dg through
d, = 1)

5V
I, = 2.5 kQ = 2 mA (255/256)= 1.992 mA
i=1

The output is 1 LSB less

than the full scale
V, for the full reference currentof 2
scale input is mA. So, theoutput voltage
V, = 2 mÀ (255/256)x 5
kQ
9.961 V =
In general, the output
voltage V, is given by

V,= dg
2 4 8 256
The 1408 DAC can be
calibrated for bipolar range from
(5 k2) between VR and output pin 4 -5 V to +5V by adding resistor Re
as shown in Fig. 10.8 (b). The
(E V/R)current resistor Rp supplies 1 mA
to the output in the opposite
direction of the current
Signal. Therefore the output
generated by the input

,
current for the bipolar operation I is

8
=I,- (V/Rg) = (Vg/R,)d
i=1
2

For binary input word = 00000000, i.e. zero input,the output becomes,

V,=I(R, =(I, – Vg/Rg)R = (0–5 V/5 k2) x 5 k =-5V

356 Linear Integrated Circuits

= 10000000, output V, becomes

For binary input word
V, =I,-VR)R, = (VRj)(d,/2) – (VRRy)lRt
= ((5 V/2.5 k2) (1/2) – (5V/5 k)l 5 kQ =(1 mA – 1 mA) x 5 k2 = 0 V
For binary input word = 11111111, output V, becomes
Vo = [VR)(255/256) - (V/R)JR, = (1.992 mA - 1 mA) x 5 k2
=0.992 mA x 5 kQ = +4.960 V

Vec(+5 V)

R14
13
(MSB)d, 5 14 woVg(+5

V)
2.5 k2
6

da 7
8 R
1408
ds9
d- 10
Out
5k2
d,11 4
d,12
16 3 1 2 15 741

15peH Rys 2.5 k2

Vea5V)
(a)

R44
14 -o Va(+5V)
2.5 kQ
5 kQ
Ra
R
1408
1 mA
Out 5 kQ

V,
16 3 1 215

ŽRis
15 pF S2.5 k2

VE(-5 V) (b)

Fig. 10.8 1408 D/A converter (a) Voltage output in unipolar range (b) Modified circuit for bipolar output

Example 10.1
The basic step of a 9-bit DAC is 10.3 mV. If 000000000 0 V, what
represents output b
produced if the input is 101101111?
 Solution
The output voltage for
input 101101111 is
= 10.3
= 10.3 mv (1x 2*+0x
mV (367) = 3.78 V
27+1 x 26 + 1x25 +0 x 24+ 1X 28 + 1 X 22 +1 x 2 +1x2)
Example 10.2

Ualculate the values of the LSB, MSB and full scale output for an 8-bit DACfor the 0 to 10 v
range.

Solution 2 10

LSB = 128 1 1 4114!1

256
V
= 10
Chapter
For 10 V range, LSB =39 mV
256

and MSB full scale = 5V

Full scale output = (Full scale voltage - 1 LSB)

= 10 V - 0.039 V= 9.961 V
Example 10.3
0
What output voltage would be produced by a D/A converter whose output range
is to

10V and whose input binary number is

i) 10 (for a 2-bit D/A converter)
(ü)0110 (for a 4-bit DAC)
(üi) 10111100 (for a 8-bit DAC)

Solution

0 V,=10v 1x,+0x;}-5v
1 1
1
+0X,4
(9 V, =10 VV0x1xtlx
=3.75V
+ 1 x 1/25
+ 1 x 1/2* + 1 x 1/2
=10 V(1 x 1/2 + 0 x 1/2

+ 0 x 1/2)
+ x 1/g6 + 0 x 1/27 + 1/32 + 1/64) = 7.34 V
1

10 (1/2 + 1/8
V
+ 1/16
3 A-D CONVERTERS the function just opposite
to that
10.9 provides word d,d,..d,
eblock ADC shown in
of
Fig.
V and
an output binary
produces
schematic
input voltage
ADAC. It accepts an analog
358 Linear Integrated Circuits

Start EOC
of functionalvalue D, so that
D = d, 21+d, 22+..,+ d,2 (10.3)
d, MSB
where d, is the most and d, is
significant bit the least d,
significant bit. An ADC usually has two additional Analog ADC Digital

control lines: the START input to tell the ADC when to

output
input v,

start the conversion and the E0C (end of conversion) d,

output to announce when the conversion is complete.
Depending upon the type of application,ADCs are
V(Reference)
designed for mieroprocessor interfacing or to directly
drive LCD or LED displays. Functional diagram of ADc
Fig. 10.9
ADCs are classifiedbroadly into two groups according
to their conversion technique. Direct type ADCs and
a given analog signal with the internally
Integratingtype ADCs. Direct type ADCs compare
generated equivalent signal. This group includes
Flash (comparator) type converter
Counter type converter
Tracking or servo converter
Successive approximation type converter
by first changing the
Integrating type ADCs perform conversion in an indirect manner
or frequency and then to a digital code. The
analog input signal to a linear functionof time
two most widely used integrating type converters are:
G)Charge balancing ADC
(ii) Dual slope ADC
The most commonly used ADCs are successiveapproximation and the integratortype. The
successive approximation ADCs are used in applications such as data loggers and
and
instrumentation where conversion speed is important. The successive approximation
accurate than integratingtype converters. The
comparator type are faster but generallyless
flash (comparator)type is expensive for high degree of [Link] integratingtype converter
is used in applicationssuch as digital meter, panel meter and monitoring systems where the
conversion accuracy is critical.

DIRECT TYPE ADCs

10.3.1 The Parallel Comparator (Flash) A/D Converter

Thís ís the simplest possible A/D converter. It is at the same time, the fastest and most
expensive technique. Figure 10.10 (a) shows a 3-bit A/D converter. The circuit consists of a
resistive dívider network, 8 op-amp comparators and a 8-line to 3-line encoder (3-bit priority
encoder). The comparator and its truth table is shown in Fig. 10.10 (b). A small amount of
hysteresis is built into the comparatot to resolve any problems that might occur if both
inputs were of equal voltage as shown in the truth table. Coming back to Fig. 10.10 (a), at
each node of the resistive divider, a comparison voltageis available. Since all the resistors
are of equal value, the voltage levels available at the nodes are equally divided between the
reference voltage VR and the ground. The purpose of the circuit is to compare the analog
input voltage V, with each of the node voltages. The truth table for the flash type AD
converter is shown in Fig. 10.10 (c). The circuit has the advantage of high speed as the
 Analog
9+Va(Reference voltage)
input V,

ŽR

SR

R 8-line

to
Yz(MSB)
Y,
3-line

priority
111 Y,(LSB)
SR encoder

R X.

R X

ov

Fig. 10.10 (a)Basic circuit of a flash type A/D converter

Voltage nput Logic output X

Vo
V,> Va
X= 1
X
X= 0 Vso
V, = Va Previous value

Fig. 10.10 (b)Comparator and its truth table

Input voltage Va

0. to Va/8 0 0 0 0 0 1 0 0
VJ8 to Va/4 0 0 0 0 0 0 1 1 0 0 1

V,/4to 3Vy/8 0 0 0 0 1 1 1 0 1

3 VJ8 to V2 0 0 1 1 1 1 1

VJ2 to 5 V/8 0 0 1 1 1 1 1 1 0
5 V/8 to 3 V/4 0 1 1 1 1 11 1 0 1

3 V/4 to 7 VJ8 0 1 1 1 1 1 1 1 11 0

7 V/8 to V 1 1 1 1 1 1 1 1 1 1 1

Fig. 10.10 (c) Truth table for a flash type A/D converter
360 Linear Integrated Circuits

time is 100
rather than sequentially. Typical conversion
conversiontake place simultaneously
by the speed of the comparator and of the
priority
ns or less. Conversion time is limited only a T1147 priority
Devices AMD 686A comparator and
encoder. By using an Advanced Micro
of 20 ns can be obtained.
encoder, conversion delays of the order required almost
This type of ADC has
the disadvantage that the number of comparators
comparators, 3-bit ADC needs 8,
whereas
doubles foreach added bit. A
2-bit ADC requires 4
required are 2
In general, the number of comparators
4-bit requires l6 comparators.
Hence the number of comparators approximately
where n is the desired number of bits, complex is the priority
doubles for each added bit.
Also the larger the value of n, the more
encoder.

10.3,2 JHe Counter Type A/D Converter

around to provide the inverse function
A to D
The to A converter can easily be turned
D
output comes
DAC's input code until the DAC's
[Link] principle is to adjust the form.
V, which is to be converted to binary digital
within t (/2) LSB to the analog input
logic circuitry to perform the code search
and
Thus in addition to the DAC, we need suitable
to announce when the DAC output has come within
a
of adequate quality
comparator
+ (12)LSB to Va: in Fig. 10.11 (a). The
A 3-bit counting ADC based upon the above principle is shown
Upon the release of RESET,the clock pulses
counter is reset to zero count by the reset pulse.
the AND gate which is enabled
arecounted by the binary counter. These pulses go through
by the voltage comparator high output.
The number of pulses counted increase with time.
this count is used as the input of a DIA converter whose
The binary word representing

output is a staircase of the type sbown in Fig. 10.11 (b). The

analog output of DAC is V
of the comparator
compared to the analog input V, by the comparator. If V, > Va, the output
the AND gate enabled to allow the transmission of the clock pulses to
becomes high and is

the counter. When V, < Va, the output of the comparator becomes low and the
gate is AND
disabled. This stops the counting at the time V,s Va and the digital output of the counter

represents the analog input voltage V. For a new value of analog input Va, a second
reset

pulse is applied to clear the counter. Upon the end of the reset, the counting begins again

Volts

Reset o
Counter stops
Clock Binary
cOunter MSB
Digital
output
Comparator V 123 4
O1 DAC
LSB 0 5 6 7 8 9 10 012
Analog input Clock
reset
LULLLLL
(a)
End Begin End
reset reset
reset
(b)

Fig. 10.11(a) A counter type A/D converter (b) D/A output staircase waveform
 as shown in Fig. 10.11 (b).The counter freguency must be low enough to give
sufficient time
for the DAC to settle and for the comDarator to
respond. Low speed is the most serious
drawback of this method. The conversion time can be as long as (2"-
1) clock periods
depending upon the magnitude of input voltage V. For instance, a
l2-bit system with
1 MHz clock frequency,the counter will

input.
take (212- 1) us 4.095 ms to convert a full scale =
If the analog input voltage varies with time, the input signal
is sampled, using a sample
and hold circuit before it is applied to the comparator. If the
maximum value of the analog
voltage is represented by n-pulses and if the clock period is
T seconds, the minimum interval
between samples is nT seconds.
10
10.3.3 Servo Tracking A/D Converter
An improved version of counting ADC is the tracking or a servo converter shown in Fig.
10.12 (a). The circuit consists of
an up/down counter with the comparator controlling Chapter

direction of the count. The analog output of

the
the DAC is V, and is compared with the
input Va: If the input V, is greater than analog
the DAC output signal, the output of the
goes high and the counter is caused to comparator
count up. The DAC output increases with
incoming clock pulse and when it becomes more than each
V., the counter reverses the direction
and counts down (but only by one count,
LSB). This causes the control to count up and the
count increases by 1 LSB. The process goes on
being repeated and the digital output
back and forth by +1 LSB around the changes
correct value. As long as the analog
slowly, the tracking A/D
input changes
willbe within one LSB of
the correct value. However, when the
analog input changes rapidly, the tracking A/D
cannot keep up with the change and error
0ccurs as shown in Fig. 10.12 (b).

The tracking ADC has the advantage of being

simple. The disadvantage, however, is the
time needed to stabilize as a new conversion value is
directly proportional to the rate at
which the analog signal changes.

Clock
Tracking error

Up-down
Up-down
counter
control
MSB Analog signal
Digital (dark line)
Comparator output with D/A output
V ¬LSB superimposed
DAC
Up/Down input
to counter

(Up=1, Dn=0)
Analog input

(a) (b) Time

Fig. 10.12 (a) A tracking A/D converter (b)Waveforms associated with a tracking A/D converter

10.3.4
Successive Approximation Converter
The
successive
approximation technique uses avery efficient code seareh strategyto complete
oohconversion in justn-clock periods. An eight bit converter would require eight clock pulses
obtain a
digital output. Figure 10.13 shows an eight bit converter. The cireuit uses a
362 Linear Integrated Circuits

EOC
o
successiveapproximation register (SAR) to
Start

find the required value of each bit by trial

and error. The circuit operates as follows.
With the arrival of the START command, SAR o CLK
=
the SAR sets the MSB d, 1 with allother
d, d,
bits to zeroso that the trial code is 10000000.
d,(MSB)
The output Va of the DAC is now compared d,
with analog input V If V, is greaterthan
the DAC output V, then 10000000 is less
than the correct digital representation. The
MSB is left at '1' and the next lower signifi

cant bit is made 1' and furthertested.

However, if V,is less than the DAC output, DAC

then 10000000 is greater than the correct
digital representation. So reset MSB to 0
and go on to the next lower significant bit. diagram of the successive
Fig. 10.13 Functional
This procedure is repeated for all subsequent approximation ADC
bits, one at a time, until all bit positions
have been tested. Whenever the DAC output crosses V,, the comparator changes state and this
can be taken as the end of conversion (EOC) command. Figure 10.14 (a) shows a typical
conversion sequence and Fig. 10.14 (b)

Correct digital Successive approximation register output Comparator output

representation V, at different stages in conversion

11010100 10000000 1 (initial output)

11000000 1

11100000
11010000
11011000
11010100
11010110
11010101
11010100

Fig. 10.14 (a) Successive approximation conversion sequence for a typical analog input

One conversion cycle

Load output
register
Actual analog
256
signal V,
192F

128

123 56789 4
Time
Fig. 10.14 (b) The D/A output voltage is seen to become successively closer
to the actual analog input voltage
 D-A and A-D Converters 363

hows the associated wave forms. It can be seen that the D/A output voltage becomes successively
nser to the actual analog input voltage. It requires eight pulses to establish the accurate
of the value ofthe analog
regardless input. However,one additional clock pulse is used
output
the output register and reinitialize the circuit.
to load
A comparison of the speed of an eight bit tracking ADC and an eight bit successive
ADC is 10.15. Given the same clock frequency, we see that the
made in Fig.
approximnation
tracking circuit is faster only for small changes in the input. In general, the successive
discussed so far.
approximation technique is more versatile and superiorto all other circuits
Successive approximation ADCs are available as self contained ICs. The AD7592 (Analog
10
Devices Co.)a 28-pin dual-in-line CMOS package is a 12-bit A/D converter
using successive

approximation technique.
Conversion time for a tracking
A/D is directly proportional to
the relative change in input value

Chapter
from one conversioncycle to the next
required
Conversion time for a successive approximation
A/D is always the same,regardless of input value
cycles
clock
of

24 6 1012 14 16 Input change

(Numberof increments)
Number
approximation
TrackingSuccessive
device device faster
faster

of conversion times for tracking and successive approximation A/D devices

Fig. 10.15 Comparison

Integrating Type of ADCs

a S/H circuit at the input. If the input changes
The integrating type of ADCs do not require value of the input
code will be proportional to the
during conversion, the ADC output
period.
averaged over the integration

10.3.5 Charge Balancing ADC

input signal to a frequency
The of charge balancing ADC is to first convert the
principle a counter
This frequency is then measured by
using a voltage to frequency (V/F) converter. advantage of
analog input. The main
and converted to an output code proportional to the or in
transmit frequency even in noisy environment
these convertersis that it is possible to of V/F converter
of the circuit is that the output
isolated form. However, the limitation
cannot be easily maintained with temperature and
depends upon an RC product whose value dual slope conversion.
by the
time. drawback of the charge balancing ADC is eliminated
The

10.3.6 Dual-Slope ADC

The
Figure 10.16 (a) diagram of the dual-slope or dual-ramp converter.
shows the functional
buffer Aj, precision integrator
analog part of the circuit consists of a high input impedance
the analog input signal V, for
A, anda voltage [Link] converter first integrates
an internal
in Fig. 10.16 (b). Then it integrates
a fixed duration of 2" clock periods as shown
364 Linear Integrated Circuits

R
Integrator
output voltage

SW. CMP V, T
Autozero
Autozero N-cycles

SW,
T,2T4 t
Time
1

od, V.
Start Control n-stage -od, Integrate
logic COunter tegrate
EOC -od,

(b)
(a)

output
diagram ofthe dual slope ADC (b) Integrated
Fig. 10.16 (a) Functional

waveform for the dual slope ADC

the integratoroutput is zero. The

number N of
reference voltage V toofreturn
opposite
the
polarity until

integrator to zero is proportional

to the value of V, averaged
clockcycles required tode. The circuit operates
Nrepresents the desired output
over the integration period. Hence
as follows: ground and SW,is
the switch SW, is connected to
Before the START command arrives, appears
after integration,
in the A,, A,, comparator loop
closed. Any offset voltage present The capacitor Caz
of the comparator is achieved.
across the capacitor Caz till the threshold all the three amplifiers.
for the input-offset voltages of
thus provides automatic compensation required to keep the offset
acts as a memory to hold the
voltage
Later, when SW2 opens, CAZ
t1, the control logic opens SW,
= and
command at t
nulled. At the arrival of the START circuit uses an n-stage
the counter starting from zero. The
connects SW, to V, and enables 2" pulses. The analog
ripple counter and therefore the
counter resets to zero after counting
the counter
number 2" counts of clock pulses after which
voltage V, is integrated for a fixed 2" x T and =
is T, the integration takes place for a time T
resets to zero. If the clock period
as shown in Fig. 10.16 (b).
the output is a ramp going downwards SW, is
end of the interval T, and the switch
The counter resets itself to zero at the have a positive
(- V). The output voltage v, will now
connected to the reference voltage the control logic
output of the comparator is positive and
slope. As long as U, is negative,the the =
when v, becomes just zero at time t t

allows the clock pulse to be counted. However, pulses enter

(EOC)command and no further clock
control logic issues an end of conversion the
reading of the counter at ty is proportional to
the counter. It can be shown that the
analog input voltage V.
In Fig. 10.16 (b)
2" counts (10.4)
T = - = clock
ty ty
rate

digital count N (10.5)

and clock rate

For an integrator,
(10.6)
Au, = (-1/RC) V(A)
The voltage u, will be equal to u at the instant t, and can be written as
 D-A and A-D Converters 365

D = (-1/RC)V\t, -t)
The voltage v is also given by
ator
oltago = (-/RC) (- V)(ty-
U ta)

V,(ty -t)= Vaty - t)

Autozoro
So,
,N-cycles,
tozero,
e-T,2'Te: Time
Putting the values of (t, - = 2" and (ty -t) =N, we get
t;)

V,(2") =(V)N
or,
V,= (V)(/2")
Integrato - Integrate
-VR
The followingimportant observationscan

N
and is independent of R, C and T.
be made:
1. Since VR and n are constant,the analog voltage V, is
proportional to
(10.7)

the count reading

10
(b)

output
2. he dual-slope ADC integrates the input signal for a fixed time, hence it provides
Dc (b) Integrated
excellent rejection of ac signals whose periods are integral
noise multiples of the

Chapter
integration time T,. Thus ac noise superimposed on the input signal such as 50 Hz
output is zero. The number N of power line pick-upwill be averaged during the input integration time. So choose lock
rtional to the value ofV, averaged period 7, so that 2"T is an exact integral multiple of the line period (1/50)second 20 =
operates ms.
output [Link] circuit

3. The main disadvantage of the dual-slope ADC isthe long conversion time. For instance,
connected to ground and SW, is if 2" T- = V50 is used to reject line pick-up, the conversion time will be 20 ms.
or loop after integration, appears
Dual-slope convertersare particularly suitable for accurate measurement. of slowlyvarying
or is achieved. capacitor CAZ
The signals,such as thermocouples and weighing scales. Dual-slope ADCs also form the basis of

pltages of all the three amplifiers.

digital panel meters and multimeters.
-oltage required to keep the offset
Dual-slope converters are available in monolithic form and are available both in
the control logic opens SW and
microprocessor compatible and in display oriented versions. The former provide the digital
zero. The circuituses an n-stage
code in binary form whereas the display oriented versions present the output code in a
er counting 2" pulse. The analog format suitable for the direct drive of LED displays. The Datel Intersil ICL7109 is a monolithic
ck pulses afterwhich the counter
12-bit dual-slope ADC with mieroprocessor compatibility .
place for a time T =
2" x T and
s
10.16 (b).
Example 10.4
erval T and the switch SW, is A dual slope ADC uses a 16-bitcounter and a 4 MHz clock rate. The maximum input voltage
have a positive
is +10 V. The maximum integrator output voltage should be -8 V when the counter has
Lage v, will now

or is positive and the control logic

cycled through 2" counts. The capacitor used in the integrator is 0.1 uF. Find the value of
comes just zero at time t tg, the = the resistor R of the integrator.
and no furtherclock pulses enter
the Solution
nter at t is proportional to
65536
Time period (tg - t) in Fig. 10.16 (b) = 4 216
MHz 4 MHz
-=16.38ms

For the integrator

(10.4) Au, =
(-1/RC) (tg - t) V,

So, RC =-(10V/- 8 V) 16.3 ms = 20.47 ms

R= 20.47uFms =204.7 k2=205 k2
(10.5)

0.1

(10.6) Example 10.5

can be If theanalog signl V, is +4.129 Vin the example 10.4, find the equivalent digital number.
written as
366 Linear Integrated Circuits

Solution

Since, V,= Vg(N/2") which the binary

So the digital count N=
2" (V/V») = 65536 (4.129 V/8 V) = 33825 for

equivalent is 1000010000100001.

10.4 DAC/ADC SPECIFICATIONS

The various
Both D/A and AD converters are available with wide range of specifications.
are analyzed.
specified by the manufacturers
important specifications of convertersgenerally voltage which may be
is the smallest change in
Resolution: The resolution of a converter converter has
8-bit D/A
of the converter. For example, an
produced at the output (or input) voltage is (1/255) of the full
2-1 255 equal intervals. Hence the smallest change in output
= is the value of the LSB.
scale output range. In short, the resolution

Resolution (in volts) = 2rVES

-1
1 LSB increment (10.8)

ways. An 8-bit DAC is said to have

However, resolution is stated in a number of different

:8 bit resolution
: a resolution of 0.392 of full-scale
a resolution of 1 part in 255
in analog
is defined as the smallest change
Similarly,the resolution of an A/D converter an 8-bit AD
As an example, the input range of
input for a one bit change at the output. 39.22 mV
for a 10 V input range is
converter is divided into 255 intervals. So the
resolution
bit DACs.
(= 10VI255). Table 10.1 gives the resolution for 6-16
Table 10.1 Resolution for 6-16 bit DACs

Intervals LSB sze LSB sze

Bits
(% of Full Scale) (10 V Full Scale)

63 1.588 158.8 mV
6

256 39.2 mV
8 0.392
1023 0.0978 9.78 mV
10
4095 0.0244 2.44 mV
12
16383 0.0061 0.61 mV
14
65535 0.0015 0.15 mV
16

Linearity: The linearity of an A/D or

D/A converter is an important measure of
its accuracy and tells us how close
the 4

converter output is to its ideal transfer 8

characteristics. In an ideal DAC, equal
increment in the digital input should
signal
produce equal increment in the analog
output and the transfer curve should be
Analog
linear. However, in an actual DAC, output
voltages do not fallon a straight line becAUse
111
000 001 010 011 100 101 110
of gain and offset errors as shown by the
solid line curve in Fig. 10.17. The static Digital word

performance of a DAC is determined by error for 3-bit DÁC

Flg. 10.17 Linearity
ftting a straight line through the measured output [Link] linearity error measures the
deviation of the actual output from the fitted line and is given by e/A as shown in Fig. 10.17.
The error is usually expressed as a fraction of LSB increment or percentage of full-scale

voltage. A good converter exhibits alinearity error of less than (112) LSB. +
Accuracy: Absolute accuracy is the maximum deviation between the actual converter
output and the ideal converter output. Relative accuracy is the maximum deviation afer
gain and offset errors have been removed. Data sheets normally specify relative accuracy
rather than absolute accuracy. The accuracy of a converter is also specified in terms of LSB
increments or percentage of full scale voltage.
10
Monotonicity: A monotonic DAC is the one whose analog output increases for an increase
in digital input. Figure 10.18 represents the
transfer curve for a non-monotonic DAC,
since the output decreases when input code
43Vs

Chapter
changes from 001 to 010. A monotonic
characteristic is essential in control 8
applications, otherwise oscillations can 2
[Link] successive approximation ADCs,
a non-monotonic characteristicmay lead to
signal
missing codes.
If a DAChas to be monotonic, the error
Analog
should be less than ±(1/2) LSB at each 000 001 010 011 100 101 110 11

output All the commercially available

level. Digital word

DACs are monotonic because the linearity Fig. 10.18 A non-monotonic 3-bit DAC
error never exceeds ±(1/2) LSB
at each

output level.
is the settling time. It represents
Settling time: The most important dynamic parameter
specified band +(1/2)LSB of its final
value
the time it takes for the output to settle within a
following a code change at the input (usually
a full scale change). It depends upon the
due to internal parasitic capacitances and inductances.
switching time of the logic circuitry used.
us depending on word length and type of circuit
Settling time ranges from 100 ns to 10
with temperature, age and power supply
Stability: The performance of converter changes
such as offset, gain,linearity error and monotonicity
[Link] all the relevant parameters
ranges.
must be over the full temperature and power supply
specified

A brief overview of ADC and DAC selection guide is given below:

AD converters: 10-bitbinary multiplying type

7530
AD 7520/AD
12-bitbinary multiplying type
AD 7521/AD 7531
8-bit ADC
ADC 0800/0801/0802
D/A converters: 8-bit DAC
DAC 0800/0801/0802
microprocessor compatible 8-bit DAC
DAC 0830/083/0832 12-bit DAC
DAC 1200/1201
DAC 1208/1209/12 10
12-bit microprocessor compatible DAC
 REVIEW QUESTIONS
10.1. Classify DACs on
the basis of their output.
10.2. Name the essential parts of a DAC.
10.3. Describe the various types of electronic switches used in D/A converter.
10.4. How many resistors are required in a 12-bit weighted resistor DAC?
10.5. Why is an
inverted R-2R ladder network DAC better than R-2R ladder DAC?
10.6. List the various AD
conversion techniques.
10.7. Which is the fastest ADC and why? 10
10.8. Give the conversion time for (i) counting ADC (i1) successive approximation ADC
(ii) dual-slope ADC.
10.9. Explain the operation of Dual-slope ADC.
Chapter
10.10. Explain how Dual-slope ADC provides noise rejection.
10.11. Explain the important specifications of DIA and AD converters.
PROBLEMS
a two-bit DAC? What is its resolution if the output
10.1. How many levels are possible in

range is 0 to 3 V?
D/A converter is available. Assume that 00000 corresponds to an output
of
10.2. A 5-bit
what output
+10 V and that the D/A converter is connected for –0.1 V
per increment,
for 11111?
voltage will be produced mV of
of 0 to 10 V and is always within
1

10.3. If a 10-bit D/A converter spans a range

linearity as a per cent of full-scale
range?
its ideal output. What is its
the output ofa 5-bit R-2R ladder DAC.
10 4 Find the voltage at all nodes 0, 1, 2, ... and at =-10 V
are equal to 0. Assume V
The least significant bit is and all other bits
1

and R =
10 k2.
resistor D/A converter.
10.5. The Fig. P. 10.5 shows a binary weighted of the digital word and that
(i) Show output resistance is independent
that the
2N-1
R,=
analog output
(ii) Show that theMSB is
R
the
voltage for
2N-1
VR 2R
2N -1

analog output
(iii) Show that theLSB is R
for the
voltage

2'R
the circuit diagram of a

(a) Draw DAC.

10.6. 6-bit inverted R-2R ladder
the
(b) For V(1) = 5V, what is
Fig. P. 10.5
maximum output voltage?
370 Linear Integrated Circuits

(c) What is the minimum voltage that can be resolved?

10.7. The analog input signal ranges for -5 to +8V in a nine bitAD converter.
()How many quantization levels are available with this AD converter?
(ii) What isthe resolution in volt per increment?
(iüi) What binary number will be produced when the analog input is zero volt?
10.8. A counting A/D converter uses a 7-bit DAC. The MSB of DAC output voltage is +5V.
(i) If the analog input voltage is +6.85 V, what will be the R-2R 1ladder output
voltage when the clock stops?
(ii) What is the number of clock pulses that occur between the release of reset and
stopping of the clock?

10.9. The ADC in problem 10.8 uses a 100 kHz clock. How long did it take to digitize
6.85 V?
10.10. What is the conversion time of a 10-bit successiveapproximation converter if its AD
input clock is 5 MHz?
10.11. A dual slope ADC uses a 18-bit counter with a 5 MHz clock. The maximum input
voltage is +12 V and the maximum integratoroutput voltage at count is -10 V. 2
If R =
100 k2, find the size of the capacitor to be used for integrator.
10.12. The dual slope ADC of problem 10.11 has an input voltage of +5.237 V. Determine the
digital number in binary which represents the count in the register.

Experiment 10.1
To construct a 4-bit R-2R ladder type D/A converter. Plot the transfer characteristics, that

is, binary input vs output voltage. Calculate the resolution and linearity of the converter
from the graph.
(i) Choose R =
10 k2, 2R =
20 kQ of tolerance or less. 1%
(iü) For logic "0' short to ground and logic 1 connect to a +5V supply.

PROCEDURE

1. Set-up the circuit shown in Fig. E. 10.1.

[Link] all inputs (d, to d)
shorted to ground, adjust the 20 k-pot until the output is
0 V. This will nullify any offset voltage at the input of the op-amp.
2R
20 k2
+15V
2R R R R R 1
7
W

10 k2 2 6
741
3
2R 2R 2R 2R
20 k2w
100K) O_15V
100 kQ
(LSB) (MSB) -15 V
Digital input

Fig. E. 10.1 A 4-bit R-2R ladder D/A converter

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