Digital Communications Lab III B.

Tech II Semester

Dept of ECE, Aditya College of Engineering 1

Digital Communications Lab III B.Tech II Semester

BLOCK DIAGRAM:

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Digital Communications Lab III B.Tech II Semester

EXP No: Date:

TIME DIVISION MULTIPLEXING & DEMULTIPLEXING
AIM: -
1.Study of 4 channel Analog Multiplexing and Demultiplexing Techniques.
2.Study of the effect of sampling frequency variation on the output.
3.Study of input signal amplitude on the output.
APPARATUS:
1. TIME DIVISION MULTIPLEXING & DEMULTIPLEXING TRAINER.
2. Oscilloscope – 30 MHz Dual Channels.
3. Patch cards.

THEORY:

The TDM is used for transmitting several analog message signals over a communication channel
by dividing the time frame into slots, one slot for each message signal. The TDM, divides the available
time into slots as shown in fig. The four input signals, all band limited by the input filters are sequentially
sampled, the output of which is a PAM waveform containing samples of the input signals periodically
interlaced in time. The samples from adjacent input message channels are separated by Ts/M, where M is
the number of input channels is called a frame and is shown in the figure. The clock pulse generator output
is a 20% duty cycle (for 4 message signals) square wave at 8 KHz. And an eight message system would
require 10 % duty cycle and a 2.5 % quiet time between pulses.

PROCEDURE:-

MULTIPLEXING: -

1. Connect the circuit as shown in diagram.

2. Switch ON the power supply.
3. Set the amplitude of each modulating signal as 5V peak to peak.
4. Monitor the outputs at test points 5,6,7,8. These are sampling PAM outputs..
5. Observe the outputs by varying the duty cycle pot (P5). The PAM outputs will vary with 10% to
50% duty cycle.

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Digital Communications Lab III B.Tech II Semester

MODEL GRAPH:

OBSERVATIONS:

Frequen
Amplitude Time Period cy

Channel 3

Channel 4

Demultiplexed CH3

Demultiplexed CH 4

Clock

TDM O/P CH3

TDM O/P CH4

TON= TOFF=
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Digital Communications Lab III B.Tech II Semester

Try varying the amplitude of modulating signal corresponding each channel by using amplitude pots
P1, P2, P3, P4. Observe the effect on all outputs.

6. Observe the TDM output at pin no. 13 (at TP9) of 4052, all the multiplexed channels are
observed during the full period of the clock (1/32KHz).
DEMULTIPLEXING & LOW PASS FILTER: -

1. Connect the circuit as shown in diagram.

2. Observe the demultiplexed outputs at test points 13.14,15,16 respectively.
3. Observe by varying the duty cycle pot P5 and see the effect on the outputs.
4. Observe the low pass filter outputs for each channel at test points 17,18,19,20 and at sockets
channels CH1, CH2, CH3, CH4. These signals are true replica of the inputs.
5. These signals have lower amplitude.
RESULT:

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Digital Communications Lab III B.Tech II Semester

BLOCK DIGRAM

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 III B.Tech II
Digital Communications Lab Semester

EXP No: Date:

PULSE CODE MODULATION & DEMODULATION

AIM: -
1. To study the pulse code modulation and demodulation.

2. To study the effect of A-Law PCM and Linear modulation by varying the input signal
amplitude.

APPARATUS:

1. PCM Modulation & Demodulation Trainer Kit.

2. 30 MHz Dual Channel CRO.
THEORY:

In analog communication systems, the limitation is that once noise is introduced at any place along
the channel, we are „stuck‟ with it. To overcome such a situation, a process known as „Quantisation‟ is
introduced in which the analog signal is approximated to the nearest whole number of small steps of each
size S. This process of quantization is done during every sampling interval. Sampling of the Analog signal
however is done at a rate keeping in view of the Nyquist criterion.

In the process of quantization, approximation is made to make the number of steps a whole
number resulting in an approximation error of ± S/2. The approximation noise or quantization noise is
reproduced in the demodulation and is inseparable from the original signal.

The quantized steps represented a binary number (of pulses) is transmitted to the receiver, This
whole process of sampling, quantization and conversion into Binary code is known as Pulse code
Modulation (PCM). Thus in PCM the code represented at a particular time slot (sampling period) is
representative of the instantaneous amplitude of the Analog signal.

PROCEDURE: 1.To study the Pulse Code Modulation and Demodulation.

Switch on the power supply. Connect the CRO probe at TP2 and set CRO in mode then vary the pot P2,
observe the variable DC voltage (-2.5v to +2.5v).

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Digital Communications Lab III B.Tech II Semester

MODEL GRAPH:

OBSERVATIONS:

For DC input:

Linear PCM: -
Receiver
S.No DC Level shifter PCM O/P
. I/P
O/P
O/p
TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17
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Digital Communications Lab III B.Tech II Semester

1. Connect the patch cord from TP2 to MOD. Input. Observe the level shifter output at
TP7, which is shifted by +2.5v
2.
Keep pot P2 –2.5v side (fully anticlock wise), now observe all LED‟s OFF. Now turn P
2
slowly clock wise and observe LED‟s glowing. Observe the serial data at TP9.

3. Connect CRO channel 1 probe at TP2 and Channel 2 probe at Demod. Output
TP21. Vary pot P2; observe that same DC voltage should appear at two points.
4. Keep some DC voltage, select one type of Encoding method by selecting toggle
switch (A-Law or Linear) then observe LED‟s. Identify the bit pattern between Linear
and A-
Law modulation. The 8-bit compressed A-Law values for 13-bit input values given in
table no.
5. Remove DC from input and connect 1KHz sine wave at TP1.
6. Observe sampling rate clock at TP8 by changing sampling rate at toggle switch
(4KHz and 8KHz).
Observe LPF output at TP6, level shifter output at TP7.

7. Observe the Sampling clock at TP8 by changing SAMPLING RATE switch and
also observe A/D QUANTIZER output at TP9 (Serial data output).
8. Observe the Demodulated output at TP21. Identify the difference between output
waveforms when sampling frequency is 4KHz and 8 KHz.
9. By changing Amplitude of sine wave observe Demodulated outputs. Observe the
DC voltage at TP7, it is +2.5v. This is origin for ADC (single supply). Any input signal
applied at MOD. Input shifted to this voltage level. This voltage is indicating on output
LED‟s when no input is applied.

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 III B.Tech II
Digital Communications Lab Semester

A- Law PCM:

Receiver
DC Level shifter PCM O/P
S.No. I/P
O/P
O/p
TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17

For AC input:
Linear PCM

DC
Amplitude Time period Frequency shift

AC signal

Level Shifter

Receiver O/P

Clock

PCM O/P=

A-Law PCM:

DC
Amplitude Time period Frequency shift

AC signal

Level Shifter

Receiver O/P
 Clock

PCM O/P=

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Digital Communications Lab III B.Tech II Semester

2. To Study the effect of A-Law in PCM:

1. Connect Mod. Input from external input at TP4. Connect external sine wave from
function generator at TP4. Maximum amplitude of this waveform is 5Vp-p.
2. Connect CRO ch1 at TP4 and ch2 at TP21. Set input amplitude 200mV p-p in function
generator. Keep sampling rate switch in 8 KHz and keep encoding switch in A-Law.
3. Observe Demodulated utput at TP21. Now change encoding switch to Linear, observe
Demodulated output at TP21. Identify deference between A-law PCM and linear
modulation. In linear modulation Demodulated output is not same as input in shape. In
A-Law PCM output is same as input in shape. Repeat this process for decreasing input
amplitude and varying frequency.
4. Now connect the input signal to audio input at TP5 and connect a patch cord at TP21
to audio output. Connect two telephone sets to telephone sockets.
5. Keep encoding switch in A-law side. One person speaks at telephone audio input and
listen another person at audio telephone output. Observe clarity of voice. Now change
encoding switch to linear side, repeat above process and observe clarity of voice. You
can observe clarity of voice is better when switch position is in A-Law.
RESULT:

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Digital Communications Lab III B.Tech II Semester

BLOCK DIAGRAM

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Digital Communications Lab III B.Tech II Semester

EXP No: Date:

DELTA MODULATION & DEMODULATION

AIM: -

To study the Delta Modulation and Demodulation.

APPARATUS: -
1. Delta Modulation & Demodulation Trainer Kit.
2. Oscilloscope – 30 MHz dual channels.
3. Patch Cards

THEORY:

In Delta Modulation, the incoming signal is over sampled (much higher than Nyquist rate) to
purposefully increase the correlation between adjacent samples of the signal. In DM, a staircase
approximation to the over sampled version of the message signal is shown in fig.

The difference between the input and the approximation is quantized into only two levels (± Δ)
corresponding to positive and negative differences respectively. Thus if the approximation falls below the
signal at any sampling epoch, it is increased by are if approximation lies above the signal, it is
. Provided the signal does
diminished by not change too rapidly from sample to sample, the
approximation remains within ±Δ of the input signal.

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Digital Communications Lab III B.Tech II Semester

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Digital Communications Lab III B.Tech II Semester

In DM system the rate of information transmission simply equal to the Sampling rate,multiplied by No of
bits per sample .The DM may be generated by applying the sampled version of the incoming message to
modulator that involves a comparator, quantizer and accumulator interconnected as shown in fig.

Low – pass
Decoder out
Σ put

input | filter

Delay Ts

Accumulator

The comparator computes the difference between its two inputs. The quantizer consists of a hard
limiter with an input – output relation, which is a scaled version of signum function.

The quantizer output is then applied to an accumulator to produce.

mq (nTs) = Σ eq

(its) i = 1

Thus at the sampling instant nTs, the accumulator incremented the approximation by a step in a
positive or negative direction depending on the algebraic sum sign of the error signal e(nTs).

In the receiver shown in fig the staircase approximation mq(t) is reconstructed by passing the
sequence of positive or negative pulses , produced at the decoder output ,through an accumulator in a
manner similar to that used in the transmitter . the out of land quantization noise in the high frequency
staircase waveform mq(t) is rejected by passing it through a low pass filter , with a band with equal to the
original message bandwidth.
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Digital Communications Lab III B.Tech II Semester

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Digital Communications Lab III B.Tech II Semester

The DM is subjected to two types of quantization error,

1) Slope overload distortion and 2) Granular Noise. The maximum slope of the staircase approximation m q
(t) is fixed by the step size Δ, increases and decreases in m q (t) tend to occur along straight lines. A delta
modulator using a fixed step size is referred to as a Linear Delta Modulator. The Granular noise occurs
when the step size is too large relative to the local slope characteristics of the input waveform m(t) causing
the stair case approximation mq (t) to hunt around a relatively flat segment of the input waveform as shown
in fig.

This granular noise is similar to quantization noise in PCM system.

Thus a large step size is required for accurate representation of relatively low – level signals. As a
compromise we need to make the delta modulator “ADAPTIVE”, that is the step size is made to vary in
accordance with the input signal.

PROCEDURE: -

1. Switch ON the power supply.

2. Connect TX clock from TP2 to TX clock input TP6. The clock frequency should be 32KHz.
3. In order to ensure for correct operation of the system, we first take the input to 0v from DC variable
at TP3 so connect the „+‟input of the delta modulator‟s VOLTAGE COMPARATOR to
0v.

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Digital Communications Lab III B.Tech II Semester

MODEL GRAPH:

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Digital Communications Lab III B.Tech II Semester

Observe the output of integrator at TP9 and the output of the level change the TP8

If the Transmitter‟s LEVEL CHANGER output has equal positive and negative output levels,
Integrator‟s output will be a triangle wave centered around „0‟volts,as shown in fig. However, if the
level changer‟s negative level is greater than the positive level, the integrator‟s output will appear as
shown in fig. Should the level changer‟s positive output level be the greater of the two levels, the
integrator‟s output will resemble that shown in fig.

4. The relative amplitudes of the level changer‟s positive and negative output levels can be varied
by adjusting the LEVEL ADJUST present in the BISTABLE AND LEVEL CHANGER
CIRCUIT.
5. The output from the Transmitter‟s BISTABLE circuit (tp7) will now be a stream of alternate „.
1‟and „0‟s,this is also the output of the delta modulator itself. The delta modulator is now said
to be balanced for correct operation.
6. Disconnect the voltage comparator‟s „+‟ input from 0V, and reconnect it to the 2KHz sine wave
from TP1.
7. Observe the integrator output by varying the amplitude.
8. Observe the Bitable output together with the analog input at TP4, and note that the 2KHz sine
wave has effectively been encoded into a stream of data bits at the Bistable‟s output.
9. Connect the modulation output to the integrator input at TP10 and observe the output at TP11.

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Digital Communications Lab III B.Tech II Semester

OBSERVATIONS:
For AC Input:

Time
Amplitude Frequency DC Shift
Period

AC Signal

Integrator O/P

DeltaModulatedO/P

Demodulated O/P

For DC Input:

Frequen
Amplitude Time period cy

TXN Clock

INTEGRATOR O/P

DELTA MODULATED
O/P

DEMODULATED O/P
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Digital Communications Lab III B.Tech II Semester

10. Now connect TP11 to the low pass filter input TP12 and observe the output.
11. Connect TP13 to the amplifier input TP14 and observe the demodulation output at TP15.

RESULT:

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Digital Communications Lab III B.Tech II Semester

BLOCK DIGRAM

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 III B.Tech II
Digital Communications Lab Semester

EXP No: Date:

FSK MODULATION & DEMODULATION

AIM: -
1. To generate FSK Modulation.
2. To Demodulate the FSK signals,
3. To generate (NRZL), RZ, NRZ (M), BIPHASE (MARK), BIPHASE (MANCHESTER).

APPARATUS:-
1. Fsk Modulation & Demodulation Trainer Kit.
2. C.R.O.30 MHz Dual Channel.
3. Patch Cards.

THEORY:

Binary FSK is a form of constant – amplitude angle modulation and the modulating signal is a
binary pulse stream that varies between two discrete voltage levels but not continuous changing analog
signal. In FSK, the carrier amplitude (Vc) remains constant with modulation and the carrier radian
frequency (Wc) shifts by an amount equal to ± ΔW/2. The frequency shift (ΔW/2) is proportional to the
amplitude and polarity of the input binary signal. For example, a binary 1 could be +1 volt and a binary
zero could be -1 volt producing frequency shifts of + ΔW/2 and - ΔW/2 respectively. The rate at which the
carrier frequency shifts is equal to the rate of change of the binary input signal Vm (t) (that is the input bit
rate). Thus the output carrier frequency deviates (shifts) between Wc + ΔW/2 and Wc - ΔW/2 at the rate
equal to fm.

FSK TRANSMITTER:

With binary FSK, the center or carrier frequency is shifted (deviated) by the binary input data .As
the binary input signal changes from a logic 0to a logic 1 and vice versa, the FSK output shifts between
two frequencies : a mark or logic 1 frequency and a space or logic 0 frequency . The output rate of change
is equal to the input rate of change. In the binary FSK, the input and output rates of changes are equal. If
the fundamental frequency of the input is considered, the highest modulating frequency is equal to one –
half the input bit rate.

The frequency of the VCO is chosen so that falls half way between the mark and space frequencies. In
binary FSK, f is the peak frequency deviation of the carrier and is equal to the difference between the rest
frequency and either mark or space frequency. In a binary digit signal , the frequency deviation is constant
and always at its maximum value , as logic is have the same voltage and all logic 0s have the same
voltage .
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Digital Communications Lab III B.Tech II Semester

MODEL GRAPH:

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 III B.Tech II
Digital Communications Lab Semester

The output of FSK modulator is related to binary input , a logic 0

corresponds to space frequency fs and
a logic 1 corresponds to mark frequency fm and fc is thee carrier the
frequency

1 0 1 1

FSK
MODULATOR

Tm Ts

2tb

The required peak frequency deviation Δf

ΔF = (|fm – fs|)/ 2 = 1 / 4 tb (minimum)

Where tb is the time of one bit and fm = fc – Δf = fc – (1/4tb)

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Digital Communications Lab III B.Tech II Semester

= fc – Δf = fc + (1/4tb)

FSK thus consists of two pulsed sinusoidal waves of frequency fm and fs.

The bandwidth for FSK = BW = fm – fs +(2/tb)

FSK RECEIVER:

As shown in fig, the incoming FSK signal is multiplied by a recovered carrier signal which has
same frequency and phase as the transmitter carrier (the two transmitted frequencies – mark and space are
not continuous. Due to practical difficulty in reproduction of a local reference, this detection is not used).

The most common circuit for demodulating binary FSK signals is the phase – Locked Loop (PLL) as
shown in fig.

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Digital Communications Lab III B.Tech II Semester

OBSERVATIONS

Frequen
Amplitude Time Period cy

Data Clock

Data Selection

FSK O/P

Logic 1

Logic 0

Demodulation

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Digital Communications Lab III B.Tech II Semester

As the input to the PLL shifts between the mark and space frequencies, the D.C. error voltage at the output
of the phase comparator follows the frequency shift. As there are only two input frequencies (mark and
space), there are also only two output errorvoltage. One represents a logic 1 and the other a logic 0.
Therefore the output is a two level (binary) representation of the FSK input. Generally the natural
frequency of the PLL is made equal to the center frequency of the FSK modulator. As result the changes in
the D.C error voltage follow the changes in the analog input frequency and are symmetrical around 0 volts.

Binary FSK has a poorer error performance than PSK or QAM and is not used for high
performance digital radio systems and its use is restricted to low performance, low cost and asynchronous
data modems.

PROCEDURE: -Modulation: -

1. Switch ON the power supply.

2. Set the Data selection switch (DATA SELECTION) to the desired code (say11001100).
3. Set the switch (DATA ON-OFF) ON position. Observe the 8 Bit Word pattern at TP12.

4. Observe the Data Clock at TP1 and also observe the NRZ (L) at TP2, RZ at TP3, NRZ9M) at
TP4, BIPHASE (MARK) at TP5, BIPHASE (MANCHESTER) at TP6.
5. Connect the patch cord as shown in diagram1. Observe the corresponding FSK output at (when Data
is logic „1‟, the frequency is high and Data is logic “0” the frequency is low) TP8.

6. Repeat the step 5 for other inputs. (Like NRZ (M), RZ, BIPHASE). Observe the
corresponding FSK output
7. Now change the Data selection and repeat the above steps 3 to 6 and observe the corresponding
FSK outputs.
DEMODULATION: -
1. Connect the patch cords as shown in diagram.
2. The incoming FSK input is observed at TP9.
3. The output of „Square wave converter‟ is available at TP10. The serial Data output is a available at
TP11.
4. Repeat the above steps 1,2,3 for other serial data outputs. The outputs are truw replica of the
original inputs.
RESULT:

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Digital Communications Lab III B.Tech II Semester

BLOCK DIAGRAM:

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Digital Communications Lab III B.Tech II Semester

EXP No: Date:

PSK MODULATION AND DEMODULATION

AIM: -
T study the operation of PHASE SHIFT KEYING modulation and demodulation
Techniques.
APPARATUS:
1. Psk Modulation and Demodulation Trainer Kit.
2. Oscilloscope 30 MHz, Dual Channel.
3. Patch chords.
THEORY:

The PSK is a form of angle modulated, constant amplitude digital modulation. In BPSK, two
output phases are possible for a single carrier frequency. As the input digital signal changes state, the
phase of the output carrier shifts between 180º out of phase.

As shown in BPSK modulator in fig A and B the balanced modulator acts as a phase reversing
switch. Depending on the logic condition of the digital input, the carrier is transferred to the output either
in phase or 180º out of phase with reference carrier oscillators and for proper operation, the digital input
voltage must be much greater than the peak carrier voltage as it has to control ON – OFF state of diodes

Balance
d Bandpass
Analog PSK
Binary data output
Modulat Filter

Reference
carrier

Oscillator

A) BPSK Modulator
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Digital Communications Lab III B.Tech II Semester

MODEL GRAPH:

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Digital Communications Lab III B.Tech II Semester

PROCEDURE:
1. Now switch ON the trainer and see that the supply LED glows.
2. Observe the carrier output at TP1.
3. Observe the data outputs (D1, D2, D3, D4).
4. Now, connect the carrier output TP1 to the carrier input of PSK modulator TP2 using
patch chord.
5. Connect the D1 to data input of PSK modulator TP3.
6. Observe the Phase shifted PSK output waveform on CRO on channel1 and
corresponding data output on channel 2.
7. Repeat the steps 4,5,6 for data outputs D2, D3, and D4 and observe the PSK outputs.
8. Connect the carrier output TP1 to the PSK input of demodulation TP4.
9. Connect the carrier output TP1 to the carrier input of PSK demodulation TP5.
10. Now, observe the PSK demodulated output at TP7 on CRO at channel1 and
corresponding data output on channel2.
11. The demodulated output is true replica of data output.
12. Repeat the steps 8 to 10 for other data outputs D2, D3, D4.

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Digital Communications Lab III B.Tech II Semester

OBSERVATIONS: -

For Data 1:

Ph
Amplitude Time period ase

Carrier i/p

Data i/p

PSK o/p
Logic 1:
Logic 0:

Demodulated o/p

For Data 2:

Ph
ase
Amplitude Time period

Carrier i/p

Data i/p
PSK o/p
Logic 1:
Logic 0:
Demodulated o/p
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Digital Communications Lab III B.Tech II Semester

RESULT:

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Digital Communications Lab III B.Tech II Semester

BLOCK DIAGRAM:-

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Digital Communications Lab III B.Tech II Semester

EXP No: Date:

DPSK MODULATION & DEMODULATION

AIM: -
To study the operation of Differential Phase Shift Keying modulation & demodulation Techniques &
plot the corresponding waveforms.

EQUIPMENT: -
1. Hi-Q Electronics, Dpsk Modulation & Demodulation Trainer.
2. Oscilloscope 30MHz,Dual Channel.
3. Patch chords.
THEORY:

The DPSK is a non-coherent version of PSK. In coherent detection, the carrier wave‟s phase reference
should be known for obtaining optimum error performance. The DPSK eliminates the need for a coherent
reference signal at the receiver by combining two basic operations at the transmitter:

1) Differential Encoding of the input binary wave

2) Phase-shift keying
And hence the name differential phase shift keying. Thus to send and hence the name differential phase
advance the current signal waveform by 180º and to send 1, we have the phase of the current signal
waveform unchanged. The receiver is equipped with a storage capability so that it can measure the relative
phase difference between the waves forms received during two successive bit intervals. Provided that the
unknown phase θ contained in the received wave varies slowly (slow enough and considered essentially
constant over two bit intervals), the phase difference between waveforms received in two successive bit
intervals will be independent of θ.

If the phase shift versus frequency is linear, delay is constant with frequency. If all frequencies are
not delayed by the same amount of time , the phase frequency relationship is not linear and the received
signal is distorted. The DPSK is an example of non – coherent orthogonal modulation when it is
considered over two bit intervals.

The average probability of error or bit error rate for DPSK provide 3 – db over non – coherent FSK
for the same Eb/No.

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 III B.Tech II
Digital Communications Lab Semester

OBSERVATIONS: -

Amplitude Time Period Phase

1.Clock Input

2.Data Input

3.Differential Data

4.Carrier

5.DPSK O/P

Logic – 1:

Logic – 0:

6. Demodulated O/P

MODEL WAVEFORMS
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Digital Communications Lab III B.Tech II Semester

PROCEDURE: -
1. Now switch ON the trainer and see that the supply LED glows.
Connect Data output from 4(D1, D2, D3, D4) data outputs to the Data input of the DPSK
MdulatorTP7.

2. Connect clock output TP1 to the clock input of the DPSK modulator TP8.
3. Now Connect carrier output TP2 to the carrier input of the DPSK modulator TP10.
4. Observe the Differential Data output on the CRO at TP9 test point as shown on the front panel.
5. Observe the Phase shifted DPSK output waveform on the CRO corresponding to the differential
data output.
6. Connect DPSK MODULATOR output TP11 to the DPSK input of the DEMODULATOR TP12.
7. Connect carrier output TP2 to the Carrier input of the DPSK Demodulator TP13.
8. Also connect clock output TP1 to the clock input of the DPSK demodulator TP14.
9. Now observe the DPSK demodulated output waveform TP15 on the CRO.
RESULT:

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Digital Communications Lab III B.Tech II Semester

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Digital Communications Lab III B.Tech II Semester

EXP No: Date:

COMPANDING
Aim

To note down the dynamic range of the signal and S/Q without companding and with companding
(both A-law and the u-law) and to observe the improvement in dynamic range and the noise performance
with companding.

APPARATUS:
1. Companding Trainer.
2. Oscilloscope – 30 MHz Dual Channels.
3. Patch cards.
Theory

While coding the signal we give higher resolution at low levels and and lower resolution at
higher levels. This makes the signal compressed in the code domain.

By applying the reverse mapping at the decoding end we get back the original signal.

By allocating more bits at lower signal levels we can reduce the quantization noise (the noise created by
the LSB).

The -law and A-law algorithms encode 14-bit and 13-bit signed linear PCM samples (respectively) to
logarithmic 8-bit samples. Thus, the G.711 encoder will create a 64 kbit/s bit stream for a signal sampled
at 8 kHz.[1]

G.711 -law tends to give more resolution to higher range signals while G.711 A-law provides more
quantization levels at lower signal levels.

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Digital Communications Lab III B.Tech II Semester

A-Law Binary Encoding Table

A-Law Binary Decoding Table

-Law Binary Encoding Table

-Law Binary Decoding Table

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Digital Communications Lab III B.Tech II Semester

The Basic Building Blocks of The Companding

Signal Generator:

The kit generates -3 to +3 DC Voltage at the input by using the UP/DOWN keys in DC
mode. The kit also generates a fixed ac waveform when the switch is in AC Mode.

A/D Convertor:

This is a 16 bit A/D convertor, for Companding we need the following sizes of A/D, for linear 8 bit, for A
law 13 bit, for u law 14 bit.

The most significant bit is used for signal sign, bit is 1 means negative.

From the 16 bit convertor we get the sign bit and 15 bit magnitude

For linear case we take the most significant 7 bits from the magnitude and the sign bit to sign bit.
For A law we take sign bit sign bit, most significant 12 bit as magnitude of the input.

For u law we are showing only the magnitude bits on LEDS. The sign bit is not shown.

The compressor:

The compressor converts the 12 bit magnitude to coded 7 bits (A law). These 7 bits along with the sign
bit go out on the channel of communication.

The Expander:

The expander converts the 7 coded magnitude back to the original 12 bit magnitude (A law).

D/A:

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The D/A is 16 bit implementation, the expander output sign bit gets loaded as sign bit, the magnitude
12 bits get loaded to the most significant 12 bits of the D/A.

The Key switches and controls on the Panel

UP/DOWN KEYS: In dc experiment mode, when up key is pressed once the dc level goes up by one step
as per the experiment table. Similarly one press of DOWN key reduces the dc level by one step. When you
want bring the dc level back to start value of 0 Press Reset Key once.

Reset Key: Puts the kit in the dc experiment mode with the starting dc level set at 0

AC/DC Slide Switch: This switch puts the kit either in DC mode or AC mode. In DC mode user can give
apply a given DC with up/down keys. Whereas in AC mode the kit generates a sample AC wave form at
the input and passes the same through the signal chain, user has to observe the AC waveform at the
output in normal/companded mode.

Normal/Compand Switch: This slide switch puts the signal chain for normal 8 bit transmit channel or
companded 8 bit chl. In normal mode the upper 8 bits of the A/D and D/A are used, the lower bits are ignored.
In companded mode as per the Companding law A/u law the 13/14 bits of A/D and D/A are used.

For the same input the user can change the signal chain from Normal to Compand and observe
the difference in the output.

Demo Key:

When this key is pressed the kit goes into dc demo mode. In this mode input changes in steps
automatically and the corresponding A/D, Channel, D/A Leds are shown and the analogue output
is obtained. To come out of this mode press the Reset key once.

SelfTest Key:

When this key is pressed the kit goes into Self Test mode. In this mode ALL LEDs are tested, keys are
tested and analogue chain is calibrated. This mode is normally used in the factory for testing and
calibration. However if the user doubts the LEDS he can use this mode check out if all LEDS are able
to glow or not. To come out of this mode press reset key once.

A-law/u-Law Switch:

This switch come into effect when companding is ON, once companding is ON this switch selects the
companding law to be used.).
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Observations Table

For u law

I/P DC A/D Ch1 Code Ch1 Code D/A O/P Error Q/S
Voltage O/P W/O With I/P Voltage Digital
12 bit Compdr Compdr 12 bit
u-law
A B C D E F E-B (E-B)/B

For A-law:

Ch1
I/P DC A/D Code Ch1 Code D/A O/P Error Q/S
O/
Voltage P W/O With I/P Voltage Digital
12
12 bit Compdr Compdr bit
A-law
A B C D E F E-B (E-B)/B

0.000 0 000 0 00 0 00
0.012 0 010 0 00 0 10
0.023 0 01F 0 00 0 1F
0.034 0 02E 0 01 0 17
0.045 0 03E 0 01 0 1F
0.070 0 060 0 03 0 28
0.091 0 07C 0 03 0 2F
C
0.750 0 400 0 20 0 0
3
1.453 0 7C0 0 E 0 6F
1.500 0 800 0 40 0 70
2.250 0 C00 0 60 0 78
7
2.906 0 F80 0 C 0 7F
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Procedure:

1. First observe the communication blocks in the signal chain

2. Apply a given dc voltage at the input by using the up/down keys, measure this with multi meter.
3. Note down the codes and the voltages as per the table given below.
4. Do this for both the linear mode and companded mode (A Law
5. Observe that higher Quantisation error Q/S in the case of linear mode compared to the
companded mode.
6. Observe the quality improvement of a companded channel for a low level ac signal given by the kit
itself in AC mode.
7. Observe the improvement in waveshape for a low level ac waveform by putting the kit in AC mode.
8. Compare the waveforms.
9. Connect I/P wave form to DSO channel-1 (trigger source ch 1)
10. Connect O/P waveform to DSO channel-2
11. Observe the variation in channel-2, by putting the mode switch in companding and normal 8 bit
linear chl mode.
RESULT:

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EXP No: Date:

SOURCE ENCODER AND DECODER

AIM

To select an information having in-equal probability of occurrence of each symbol or having

redundancy in the information and applying a source code using one of the technique i.e Huffman coding,
observing the size of the coded information, sending the minimized packet, decoding at the receiving end
getting back the full information sent.

Theory

Source Coding is a technique of compressing the source information size based on the probability
of occurrence of each information symbol. Decoding is the reverse process to get back the full source
information.

In every day we employ this in transferring big files, particularly image/voice files by zipping them and
transferring to the destination and unzipping at the destination.

Example: Huffman coding

When we have to transmit a set of symbols over a communication channels, normally choose no. of bits to

accommodate all the symbols for example 8 symbols can be coded using 3 bits, because 3 bits give us 2 3
=8 combinations. With this type of normal binary representation we can transfer any combination of
symbols in any order. However if our information to be transmitted has a set of symbols but the occurrence
of symbols with different frequencies, we can employ a coding technique whereby we choose less no of
bits for the frequently occurring symbol and more bits for the less occurring symbol. This way we can
represent our information which is a sequence of symbols with less no.of bits i.e. reduced size. In everyday
language, we call this zipping.

Huffman coding is based on the frequency of occurrence of a data item (pixel in images). The principle is
to use a lower number of bits to encode the data that occurs more frequently. Codes are stored in a Code
Book which may be constructed for each image or a set of images. In all cases the code book plus encoded
data must be transmitted to enable decoding.

The Huffman algorithm is now briefly summarized:

A bottom-up approach

1. Initialization: Put all nodes in an OPEN list, keep it sorted at all times (e.g., ABCDE)
2. Repeat until the OPEN list has only one node left:
a) From OPEN pick two nodes having the lowest frequencies/ probabilities, create a parent node of them.
 b) Assign the sum of the children‟s frequencies/probabilities to the parent node and insert it into OPEN.

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c) Assign code 0,1 to the two branches of the tree, and delete the children from OPEN.

The following points are worth noting the about the above algorithm:

Decoding for the above two algorithms is trivial as long as the coding table (the statistics) is sent
before the data. (There is a bit overhead for sending this, negligible if the data file is big.)
If prior statistics are available and accurate, then Huffman coding is very good.

In the above example:

Number of bits needed for Huffman Coding is: 87/39=2.23

Examples

Let us take an example that we wish to transmit a word ABRAKADABRA which has 5 types of
symbols A, B, R, K, D

In normal coding to represent one of the 5 symbols we need 3 bits.

To transmit this 11 chars we will need 3 11=33 bits.

However by employing Hoffman source coding as below we can transmit the information using
only 23 bits.

B = 100

K = 1010

D = 1011

R = 11

BR K D BRA = 01001101010010110100110

This is eleven letters in 23 bits.

A fixed – width encoding would require 3 bits for five different letters, or 33 bits for 11 letters.
Notice that the encoded bit string can be decoded!

The Decoding Process

The decoding process is just the reverse process (table look up process) i.e. if we receive a pattern 1010
its is decoded as letter C, however one important point is to be noticed that if the input symbols are
concatenated i.e put in continuous sequence we should be able to distinguish the no of bits corresponding
to each symbol, this is possible only if the code is chosen such that the
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Observations

Information Information Information Decoded

text Bits Bits information
Without With coding
coding
ABRAKADABRA

DABRAKAABRA

Note the difference in the length of bits required without coding and with coding.
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confusion does not arise, Let us apply the decoding process for the above example sequence received
is 01001101010010110100110

Let us pick the first bit which is 0. Is there a symbol for only one bit as 0? Yes there is a symbol-A for this
code. So let us separate this as one symbol so it becomes 0,100. Then further there is no symbol with
single bit 1, there is no symbol with 2 bits 10 going further we take 100. There

is a symbol B assigned for 100. So we separate this as 0,100, we continue like this and decode the whole
pattern.

If there are errors in the received sequence that we can not decode all the subsequent symbols following
the error.

Experiment Procedure

1. observe the signal chain.

2. Then verify how many bits are taken to transmit ABRAKADABRA in normal and source coded
mode
3. To send an input symbol, push any one of the input symbol keys, to transmit a letter A, student has
to press the key marked A
4. Observer how many bits are being transmitted for this key. And the bit code for the same., and
note down the bits being transmitted on the LEDS (1 =Red, 0 =Green)
5. Observe if the corresponding output LED glows corresponding to the symbol pressed at the input.

RESULT:

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Digital Communications Lab Semester

EXP No: Date:

LINEAR BLOCK CODES ENCODER & DECODER

Aim

To observe that the errors received through a noisy channel can be removed/minimized
by employing the error detection and correction code.

Theory

This topic comes under channel coding techniques which are employed for the purpose of
detecting and correcting errors occurring in the communication channel. When information is represented
in blocks of k bits we can add few extra bits increasing the block size to n bits and employ block coding
techniques to detect and correct errors in the reception.

We can add a few extra bits to the information bits i.e. provide some redundancy and
detect/correct the errors from the received data. More redundancy we provide more correction we can
have. By using hamming coding technique with given no. of extra bits we can extract maximum advantage
of detection and correction.

Hamming code (n, k) places symbols represented by n bits having k information bits at a
maximum distance from each other allowing us to detect more errors and correct more errors. The decoder
if it finds the errors which cannot be corrected, it shows the O/P but indicates that the same with error LED
at the output. Normally if in applications using command and control the decoded O/P having errors is not
used it is discarded.

Procedure

1. Observe the signal chain, i.e. the input stage, coding stage, transmission stage and the decode
stage.
2. Put the mode selection switch in NORMAL mode and see the process and observe output
3. Student selects input message that is to be coded, by shifting the bits 0/1 by means of pressing the
keys 0, 1, CLEAR.
4. Student codes this input message by pushing the key „CODE A BIT‟ or by pushing „ CODEALL‟
5. Now the message is coded and displayed in the transmission path. Student can now introduce an
error in the transmission channel by means of pressing the keys BITSEL and ERRSET. On every
push of the BITSEL one bit is selected in the channel code, the selected bit will be completely in
OFF mode at this stage, if the student presses ERRSET key, the OFF mode bit will be inverted to
make it as an error.
6. Now the student pushes the DECODE key, the channel code is decoded and displayed as the
Output message. If an error is detected in the channel code ERRDETECTED LED glows, if an
error is corrected from channel code then the ERRCORRECTED LED glows in the decoder
Output stage.
7. Now put mode selection in CODE mode and repeat the process and observe the output changes.
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Observations Table

NORMAL SYSTEM WITHOUT CODING

I/P Normal Errors in
Data Transmission Transmission
Set

Cha1 O/P Cha1 O/P

data Data data Data

1010 1010 1010 1000 1000

SYSTEM WITH BLOCK CODING

Cha1 O/P Cha1 O/P

data Data data Data

1010 101x0yz 1010 100x0yz 1010

xyz in the channel data above indicates the hamming encoded bits of corresponding data.

From the above observations, we can conclude and record the following points.
Errors in the transmission channel can be detected and corrected with linear block coding.
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8. Observe how the error detection and correction in code mode and hence the implementation
of Linear Block encoder and decoder.
9. Pushing Demo mode switch will give a brief description of implementation of KITIn
this experiment hamming code (7.4) is employed

Building Blocks of the Linear Block Code

The uC reads the input switch positions and codes them if NORM/CODE switch is in CODE
position.

The 16 i/ps have to be captured into 16 bit parallel in and serial out shift register. Adjacent to the switch an
LED should show the bit state we have set.

The coded bits are transferred through the transmission channel bit by bit with each push of SENDBIT
key.

The 16 O/Ps have to be latched into 16 bit serial in parallel shift register.

While the bits are being transferred the user can introduce error by putting the ERRADD SWITCH in ON
position and while SENDBIT is pressed.

If the decoded Output has error as per decoding procedure then LEDERR is glows. If decoder has
corrected an error then the LED error corrected also will glow.

One reset key will reset the system to initial state.

Demo mode facilitates the basic idea of kit implementation

At Startup self-test process occurs with glowing all LED‟s such that malfunctioned components can be
identified.

Result:

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M 3 M 2 M1M 0C2C1C0

M 3 M 2 M1M 0C2C1C0
III B.Tech II
Digital Communications Lab Semester

EXP No: Date:

BINARY CYCLIC CODES ENCODER AND DECODER

Aim

To observe that the errors received through a noisy channel can be removed/ minimized by
employing the error detection and correction code, by using an algebraic structure.

Theory

In coding theory cyclic codes are the sub-class of linear block error correcting codes that have
convenient algebraic structures for efficient error detection and correction. A linear code is called cyclic
code if every cycle shift of code vector produces some other code vector i.e. the cycle shift to the data in
an array should also represent the data in the same array.
Example: arr {(0000), (0101), (1010), (1111)}

There are two cyclic codes encoding techniques:

Nonsystematic: Encoded data is obtained by performing M(p) * G(p)/

Systematic: Coded data ( C2C1C0 ) is obtained by performing P q * M(p)/G(p) and

resultant Encoded data will be in form of

Here M (p) is input Message / Data of p

G (p) is constant algebraic expression of p

q is constraint length i.e. Systematic (7, 4) gives q=n-

k n is channel length and

k is data length

Let us consider an example for implementation of the experiment (Q) Design the encoder for the

Systematic (7, 4) cyclic code generated by a polynomial G(p)= p 3 + p + 1 and decode the data
transferred by syndrome decoding procedure for knowing input.

The implementation of cyclic encoding and decoding kit is based on the same example. The

encoded data output will be which is can be obtained from Systematic coding

procedure and the decoding the data will be done by syndrome decoding procedure to regenerate input and
correct the data received from any noisy channel.
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Observation Table

NORMAL SYSTEM WITHOUT CODING

I/P Normal Errors in
Data Transmission Transmission
Set

Cha1 O/P Cha1 O/P

data Data data Data

1010 1010 1010 1000 1000

SYSTEM WITH BLOCK CODING

Cha1 O/P Cha1 O/P
data Data data Data

1010 1010xyz 1010 1000xyz 1010

xyz (as per our discussion C2C1C0 ) in the channel data above indicates the hamming encoded bits
of corresponding data.

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Procedure:

1. Observe the signal chain, i.e. the input stage, coding stage, transmission stage and the decode
stage
2. Put the mode selection switch in NORMAL mode and see the process and observe output
3. Select input message that is to be coded, by shifting the bits 0/1 by means of pressing the keys 0,
1, CLEAR.
4. codes this input message by pushing the key „CODE A BIT‟ or by pushing „ CODEALL‟
5. Now the message is coded and displayed in the transmission path. Student can now introduce an
error in the transmission channel by means of pressing the keys BITSEL and ERRSET. On
every push of the BITSEL one bit is selected in the channel code, the selected bit will be
completely in OFF mode at this stage, if the student presses ERRSET key, the OFF mode bit
will be inverted to make it as an error.
6. Now the student pushes the DECODE key, the channel code is decoded and displayed as the
Output message. If an error is detected in the channel code ERRDETECTED LED glows, if an
error is corrected from channel code then the ERRCORRECTED LED glows in the decoder
Output stage.
7. Now put mode selection in CODE mode and repeat the process and observe the output changes.
8. Observe how the error detection and correction in code mode and hence the implementation of
Binary Cyclic encoder and decoder.
9. Pushing Demo mode switch will give a brief description of implementation of KIT

Result:

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x
m m m
j j 1
j
2 j

j m
j
2 mj

(n, k, L)=(2, 1, 2) encoder

Implemented Encoder in this Kit

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EXP No: Date:

CONVOLUTION CODES ENCODER AND DECODER

Aim

Employ one of the convolution codes and observe its error correcting performance and decode-
ability.

Theory
Encoder
Convolutional encoder is a finite state machine (FSM), processing information bits in a serial
manner. Thus the generated code is a function of input and the states of the FSM. In this (n, k, L)=(2, 1, 2)
encoder each message bits influences a span of n(L+1)=6 successive output bits

(a) Rate: Ratio of the number of input bits to the number of output bits. In this example, rate is ½ which
means there are two output bits for each input bit.
(b) Constraint length: The number of delay elements in the convolutional coding. In this example, with K
= 3 there are two delay elements.
(c) Generator Polynomial: Wiring of the input sequence with the delay elements to form the output. In

this example, generator polynomial is [7, 5] 8 =[111,101] 2 . The output from the 7 8 =111 2 arm uses
the XOR of the current input, previous input and the previous to previous input. The output from the

5 8 =101 2 uses the XOR of the current input and the previous to previous input.

Decoder Using Viterbi Algorithm

Viterbi algorithm reconstructs the maximum-likelihood path given the input

sequence. Let's define some terms:
A soft decision decoder – a decoder receiving bits from the channel with some kind of reliability estimate.
Three bits are usually sufficient for this task. Further increasing soft decision width will increase
performance only slightly while considerably increasing computational difficulty . For example, if we use
a 3-bit soft decision, then “000” is the strongest zero, “011” is a weakest zero, “100” is a weakest one and
“111” is a strongest one.
A hard decision decoder – a decoder which receives only bits from the channel (without any reliability
estimate).

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Viterbi decoder data flow.

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A branch metric – a distance between the received pair of bits and one of the “ideal” pairs (“00”, “01”,
“10”, “11”).
A path metric – a sum of metrics of all branches in the path.
A meaning of distance in this context depends on the type of the decoder:

for a hard decision decoder it is a Hamming distance, i.e. a number of differing bits;
for a soft decision decoder it is an Euclidean distance.

In these terms, the maximum-likelihood path is a path with the minimal path metric. Thus the problem of
decoding is equivalent to the problem of finding such a path.

Let's suppose that for every possible encoder state we know a path with minimum metric ending in this
state. For any given encoder state there is two (and only two) states from which the encoder can move to
that state, and for both of these transitions we know branch metrics. So, there are only two paths ending in
any given state on the next step. One of them has lesser metric, it is a survivor path. The other path is
dropped as less likely. Thus we know a path with minimum metric on the next step, and the above
procedure can be repeated.

Implementation
A Viterbi algorithm consists of the following three major parts:

1. Branch metric calculation – calculation of a distance between the input pair of bits and the four possible
“ideal” pairs (“00”, “01”, “10”, “11”).

2. Path metric calculation – for every encoder state, calculate a metric for the survivor path ending in this
state (a survivor path is a path with the minimum metric).

3. Traceback – this step is necessary for hardware implementations that don't store full information about
the survivor paths, but store only one bit decision every time when one survivor path is selected from the
two.

Branch Metric Calculation

Methods of branch metric calculation are different for hard decision and soft decision decoders.

For a hard decision decoder, a branch metric is a Hamming distance between the received pair of bits and the
“ideal” pair. Therefore, a branch metric can take values of 0, 1 and 2. Thus for every input pair we have
4 branch metrics (one for each pair of “ideal” values).
For a soft decision decoder, a branch metric is measured using the Euclidean distance. Let x be the first
received bit in the pair, y – the second, x0 and y0 – the “ideal” values. Then branch metric is

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A modulo-normalization approach for path metrics

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Mb=(x-x0)2 + (y-y0)2.

Furthermore, when we calculate 4 branch metric for a soft decision decoder, we don't actually need to
know absolute metric values – only the difference between them makes sense. So, nothing will change if
we subtract one value from the all four branch metrics:

Mb=(x2-2xx0+x02)+(y2-2yy0+y02);

Mb* = Mb - x2 - y2=(x2-2xx0)+(y2-2yy0).

Note that the second formula, M b*, can be calculated without hardware multiplication: x 02 and y02 can be
pre-calculated, and multiplication of x by x 0 and y by y0 can be done very easily in hardware given that x 0
and y0 are constants.

It should be also noted that Mb* is a signed variable and should be calculated in 2's complement format.

Path Metric Calculation

Path metrics are calculated using a procedure called ACS (Add-Compare-Select). This procedure is
repeated for every encoder state.

1. Add – for a given state, we know two states on the previous step which can move to this state, and the
output bit pairs that correspond to these transitions. To calculate new path metrics, we add the previous
path metrics with the corresponding branch metrics.

2. Compare, select – we now have two paths, ending in a given state. One of them (with the greater metric)
is dropped.

As there are 2K-1 encoder states, we have 2K-1 survivor paths at any given time.

It is important that the difference between two survivor path metrics cannot exceed δlog(K-1), where δ is a
difference between maximum and minimum possible branch metrics.

The problem with path metrics is that they tend to grow constantly and will eventually overflow. But, since
the absolute values of path metric don't actually matter, and the difference between them is limited, a data
type with a certain number of bits will be sufficient.

There are two ways of dealing with this problem:

1. Since the absolute values of path metric don't actually matter, we can at any time subtract an identical
value from the metric of every path. It is usually done when all path metrics exceed a chosen threshold
(in this case the threshold value is subtracted from every path metric). This method is simple, but not very
efficient when implemented in hardware.

2. The second approach allows overflow, but uses a sufficient number of bits to be able to detect whether
the overflow took place or not. The compare procedure must be modified in this case.
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Survivor paths graph example. Blue circles denote encoder states. It can be seen that all survivor
paths have a common beginning (red) and differ only in their endings.

Observation Table

NORMAL SYSTEM WITHOUT CODING

I/P Normal Errors in
Data Transmission Transmission
Set
Chal O/P Chal O/P
data Data data Data

1010 1010 1010 1000 1000

SYSTEM WITH CONVOLUTION CODING

Changed Chal Chal O/P
i/p data Data Data

1010 101000* 111101111000** 111100110000 101000

*Channel input increases such that the memory states should become Zero‟s** Channel data as per the
 Convolution encodi

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The whole range of the data type's capacity is divided into 4 equal parts. If one path metric is in the 3-rd
quarter, and the other – in the 0-th, then the overflow took place and the path in the 3-rd quarter should be
selected. In other cases an ordinary compare procedure is applied. This

works, because a difference between path metrics can't exceed a threshold value, and the range of path
variable is selected such that it is at least two times greater than the threshold.

Traceback

It has been proven that all survivor paths merge after decoding a sufficiently large block of data (D on
Figure 5), i.e. they differ only in their endings and have the common beginning.

If we decode a continuous stream of data, we want our decoder to have finite latency. It is obvious that
when some part of path at the beginning of the graph belongs to every survivor path, the decoded bits
corresponding to this part can be sent to the output. Given the above statement, we can perform the
decoding as follows:

1. Find the survivor paths for N+D input pairs of bits.

2. Trace back from the end of any survivor paths to the beginning.
3. Send N bits to the output.
4. Find the survivor paths for another N pairs of input bits.

5. Go to step 2.

In these procedure D is an important parameter called decoding depth. A decoding depth should be
considerably large for quality decoding, no less then 5K. Increasing D decreases the probability of a
decoding error, but also increases latency.
As for N, it specifies how many bits we are sending to the output after each traceback. For example, if
N=1, the latency is minimal, but the decoder needs to trace the whole tree every step. It is computationally
ineffective. In hardware implementations N usually equals D.

Procedure:

1. Observe the signal chain, i.e. the input stage, coding stage, transmission stage and the decode
stage
2. Put the mode selection switch in NORMAL mode and see the process and observe output
3. Student selects input message that is to be coded, by shifting the bits 0/1 by means of pressing
the keys 0, 1, CLEAR
4. Student codes this input message by pushing the key „CODE A BIT‟ or by pushing
„CODEALL‟

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5. Now the message is coded and displayed in the transmission path. Student can now introduce
an error in the transmission channel by means of pressing the keys BITSEL and ERRSET. On
every push of the BITSEL one bit is selected in the channel code, the selected bit will be
completely in OFF mode at this stage, if the student presses ERRSET key, the OFF mode bit
will be inverted to make it as an error.
6. Now the student pushes the DECODE key, the channel code is decoded and displayed as the
Output message. If an error is detected in the channel code ERRDETECTED LED glows,

7. if an error is corrected from channel code then the ERRCORRECTED LED glows in the
decoder Output stage.
8. Now put mode selection in CODE mode and repeat the process and observe the output
changes.
9. Observe how the error detection and correction in code mode and hence the implementation of
convolution encoder and decoder.
10. Pushing Demo mode switch will give a brief description of implementation of KIT
Result

Dept of ECE, Aditya College of Engineering 71