1) Which of the following microprocessor is an 8 bit Microprocessor

a) 4004 b) 8088 c) 8085 d) 8086

2) Which of the following microprocessor has 16 bit address bus
a) 4004 b) 8088 c) 8085 d) 8086
3) Which of the following microprocessor has an 8-bit data bus
a) 4004 b) 8088 c) 8085 d) 8086
4) An 8-bit microprocessor has an
a) 8-bit data bus b) 8-bit address bus c) 8-bit control bus d) 8 interrupt lines

5) If a microprocessor is capable of addressing 64K bytes of memory, its address-bus width

is
a) 16 bits b) 20 bits c) 8 bits d) None of these

6) Flip-flops are used in a microprocessor to indicate

a) Shift register b) latches c) counters d) flags
7) A microprocessor performs as a
a) CPU b) Memory c) output device d) input device
8) A microprocessor system consists of
a) ALU b) address bus c) data bus d) ALU, address bus and data bus
9) For using a microprocessor-based system
a) A program is required
b) The program must be stored in memory before the system can be used
c) The program need not be stored in memory
d) The program is stored in the internal resistors of the microprocessor
10) The number of flag bits in flag register (F) of the 8085 microprocessor is
a) 5 b) 6 c) 4 d) 3
11) The word size of the 8085 microprocessor is
a) 8 bits b) 16 bits c) 20 bits d) 4 bits
12) The 8085 microprocessor is a
a) 40-PIN IC b) 32-PIN IC c) 28-PIN IC d) 24-PIN IC
13) The address bus of a microprocessor is
a) Unidirectional b) Bi-directional c) Unidirectional as well as bi-directional d) none of
these
14) The data bus of a microprocessor is
a) Unidirectional b) Bi-directional c) Unidirectional as well as bi-directional d) none of
these
15) The program counter (PC) in a microprocessor

a) Keeps the address of the next instruction to be fetched

b) Counts the number of instructions being executed on the microprocessor
c) Counts the number of programs being executed on the microprocessor
d) Counts the number of interrupts handled by the microprocessor
16) Which of the following units are used in 8085
a) Register b) ALU c) Control unit (CU) d) All of these

17) What is the clock frequency for 8085

 a) 3 MHZ b) 2 MHZ c) 4 MHZ d) 5 MHZ
18) 8085 requires
a) +5 volt power supply b) +10 volt power supply c) +7 volt power supply d) -5 volt power
supply
19) Which of the following is not a part of the processor?
a) Register b) ALU c) CU b) System bus
20) Which of the following is a general purpose register in 8085
a) Register B b) Flag register (F) c) Instruction decoder d) Program Counter
21) Which of the following is a special purpose register in 8085
a) Register A b) Register B c) Register C d) Register D
22) Accumulator (Acc) in a 8085 microprocessor is denoted by
a) Register A b) Register B c) Register C d) Register D
23) Which of the following is a valid register pair
a) B-C b) B-D c) H-E d) B-L
24) What is the name of 16 bit register in 8085
a) SP b) PC c) Both SP and PC d) None of these
25) Which of the following is a memory pointer register
a) Register A b) Register B c) Register C d) Program Counter (PC)
26) MOV A,B is

a) One Byte Instruction b) Two Byte Instruction c) Three Byte Instruction d) Four Byte
Instruction

27) LXI H, 2050H is

a) One Byte Instruction b) Two Byte Instruction c) Three Byte Instruction d) Four
Byte Instruction

28) ADD B is

a) One Byte Instruction b) Two Byte Instruction c) Three Byte Instruction d) Four Byte
Instruction

29) LDA 2050H is

a) One Byte Instruction b) Two Byte Instruction c) Three Byte Instruction d) Four Byte
Instruction

30) MVI A, 32H is

a) One Byte Instruction b) Two Byte Instruction c) Three Byte Instruction d) Four
Byte Instruction

31) MVI M, 32H is

a) One Byte Instruction b) Two Byte Instruction c) Three Byte Instruction d)

Four Byte Instruction
32) ADI 32H is

a) One Byte Instruction b) Two Byte Instruction c) Three Byte Instruction d) Four
Byte Instruction

33) ANA B (Logical AND) is

a) One Byte Instruction b) Two Byte Instruction c) Three Byte Instruction d) Four
Byte Instruction
34) ORA B (Logical OR) is
a) One Byte Instruction b) Two Byte Instruction c) Three Byte Instruction d) Four
Byte Instruction

35) Opcode of instruction MOV A,B is

a) 01111000 b) 01111111 c) 00000000 d) 11111111

36) Opcode of instruction ADD B is

a) 10000000 b) 100011100 c) 11111111 d) 11100000

37) Opcode of instruction LXI H, 2050H is

a) 00100001 b) 100011100 c) 11111111 d) 11100000

38) Opcode of instruction MVI A, 32H is
a) 00111110 b) 01111000 c) 01111111 d) 00000000
39) Opcode of instruction ADI 32H is
a) 00100001 b) 100011100 c) 11111111 d) 11000110
40) Opcode of instruction ANA B is
a) 10100000 b) 10111000 c) 11111111 d) 10101111
41) Let the contents of register A (ACC) and register B are 20H and 30H respectively.
After execution of instruction MOV A,B contents of register A (ACC) and register B
are
a) 20H and 30H b) 20H and 20H c) 30H and 30H d) 30H and 20H
42) Let the contents of register A (ACC) and register B are 20H and 30H respectively.
After execution of instruction ADD B contents of register A (ACC) and register B are
a) 20H and 30H b) 20H and 20H c) 30H and 30H d) 50H and 30H
43) Let the contents of register A (ACC) and register B are 30H and 20H respectively.
After execution of instruction SUB B contents of register A (ACC) and register B are
a) 20H and 30H b) 20H and 20H c) 30H and 30H d) 10H and 20H
44) Let the content of register A (ACC) is 10H. After execution of instruction INR A
content of the register A is
a) 11H b) 0FH c) F0H d) 10H
45) Let the content of register A (ACC) is 10H. After execution of instruction DCR A
content of the register A is
a) 11H b) 0FH c) F0H d) 10H
46) Let the content of register A (ACC) is 00H. After execution of instruction MVI A, 32H
content of the register A is
a) 00H b) 32H c) 33H d) 22H
47) Let the contents of register A (ACC) and register B are 20H and 30H respectively.
After execution of instruction ANA B (Logical AND) contents of register A (ACC)
and register B are
a)20H and 30H b) 20H and 20H c) 30H and 30H d) 30H and 20H
48) Let the contents of register A (ACC) and register B are 20H and 30H respectively.
After execution of instruction ORA B (Logical OR) contents of register A (ACC) and
register B are
a)20H and 30H b) 20H and 20H c) 30H and 30H d) 30H and 20H
49) Let the contents of register A (ACC) and register B are 20H and 30H respectively.
After execution of instruction XRA B (Logical X-OR) contents of register A (ACC)
and register B are
a)10H and 30H b) 20H and 20H c) 30H and 30H d) 30H and 20H
50) Let the contents of register A (ACC) and register B are 20H and 30H respectively.
After execution of instruction CMP B (Logical Compare) contents of register A
(ACC) and register B are
a)20H and 30H b) 20H and 20H c) 30H and 30H d) 30H and 20H
51) Let the contents of register A (ACC) and register B are 20H and 30H respectively.
After execution of instruction ADD B status of Flag register (F) is
a) S=0, Z=0, CY=0, AC=0, P=1 b) S=0, Z=0, CY=1, AC=1, P=1 c) S=0, Z=0, CY=0,
AC=1, P=1 d) S=1, Z=1, CY=0, AC=0, P=1
52) Let the contents of register A (ACC) and register B are 30H and 20H respectively.
After execution of instruction SUB B status of Flag register (F) is
a) S=0, Z=0, CY=0, AC=0, P=0 b) S=0, Z=0, CY=1, AC=1, P=1 c) S=0, Z=0,
CY=0, AC=1, P=1 d) S=1, Z=1, CY=0, AC=0, P=1
53) Let the contents of register A (ACC) is 10H. After execution of instruction INR A
status of Flag register (F) is
a) S=0, Z=0, AC=0, P=1 b) S=0, Z=0, AC=1, P=1 c) S=1, Z=0, AC=1, P=1 d)
S=1, Z=1, AC=0, P=1
54) Let the contents of register A (ACC) is 10H. After execution of instruction DCR A
status of Flag register (F) is
a) S=0, Z=0, AC=0, P=1 b) S=0, Z=0, AC=1, P=1 c) S=1, Z=0, AC=1,
P=1 d) S=1, Z=1,AC=0, P=1
55) Let the contents of register A (ACC) and register B are 15H and 93H respectively.
After execution of instruction ANA B (Logical AND) status of Flag register (F) is
a) S=0, Z=0, CY=0, AC=0, P=1 b) S=0, Z=0, CY=1, AC=1, P=1 c) S=0, Z=0,
CY=0, AC=1, P=1 d) S=1, Z=1, CY=0, AC=0, P=1

56) Let the contents of register A (ACC) and register B are 15H and 93H respectively.
After execution of instruction ORA B (Logical OR) status of Flag register (F) is
a) S=1, Z=0, CY=0, AC=0, P=0 b) S=0, Z=0, CY=1, AC=1, P=1 c) S=0, Z=0, CY=0,
AC=1, P=1 d) S=1, Z=1, CY=0, AC=0, P=1
57) Let the contents of register A (ACC) and register B are 15H and 93H respectively.
After execution of instruction XRA B (Logical X-OR) status of Flag register (F) is
a) S=1, Z=0, CY=0, AC=0, P=0 b) S=0, Z=0, CY=1, AC=1, P=1 c) S=0, Z=0,
CY=0, AC=1, P=1 d) S=1, Z=1, CY=0, AC=0, P=1
58) Let the contents of register A (ACC) and register B are 15H and 93H respectively.
After execution of instruction CMP B (Logical compare) status of Flag register (F)
is
a) S=1, Z=0, CY=1, AC=1, P=1 b) S=0, Z=0, CY=0, AC=1, P=1 c) S=0, Z=0,
CY=0, AC=1, P=0 d) S=1, Z=1, CY=0, AC=0, P=1