Multilevel Waveform Synthesis

Vdc/4

Vdc/2 a
Vdc/4
a a
Vdc
Vdc/4
Vdc/2 Vao
Vao Vao
Vdc/4

2-level 3-level 5-level

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Fig. Pole voltages (Vao) of (a) two-level, (b) three-level and (c) five-level inverters.
Equivalent circuit of multilevel voltage-
source converters

2
 Topologies of Multilevel Inverters
• Neutral Point Clamped Inverter
• Diode Clamped Multilevel Inverter
• Capacitor Clamped Multilevel Inverter
• Cascaded H-Bridge Inverter
• Hybrid Multilevel (Inverters (3kV GTO and 1.5kV IGBT inverter for
motor control)

• Phase shifting of 2-level H-bridge inverters

• Binary MLI
• Asymmetrical MLI to improve the resolution of low and medium
power inverters,
• Open-end winding induction motor control topology
Nabae (1981) developed the basic structure of multilevel 3
inverter, known as Neutral Point Clamped (NPC) inverter
 Multilevel Inverter Topologies

• Diode Clamped Multilevel Inverter (DCMLI),

• Flying Capacitor Multilevel Inverters (FCMLI),

• Cascaded H-Bridge Inverters with Separate DC Sources,

• Generalized Multilevel Inverter,

• Asymmetrical Multilevel Inverter,

• Mixed-Level Hybrid Multilevel Cells,

• Zero Voltage Switching Multilevel Inverters etc.

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Diode Clamped Multilevel Inverter

Pole Voltage

3-level

5
Diode Clamped Multilevel Inverter

Pole Voltage

5-level

6
 Diode Clamped Multilevel Inverter
In general,
If m is the number of levels in output phase voltage of inverter
for DCMLI, then

Number of levels in output line voltage of inverter = (2m-1),

Number of capacitors in dc link = (m-1),
Number of clamping diodes per phase leg = (m-1)(m-2),
Voltage to be withstand by each switching device = Vdc/(m-1)
Voltage across each dc link capacitor = Vdc/(m-1)

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Main Features of Diode Clamped Multilevel Inverter
• A common DC bus for all the phases,
• Reduced harmonic contents in inverter output voltage, dominant
harmonics are present around double the switching frequency,

• If all the devices are switched at fundamental frequency, it results in

reduced switching losses and increased efficiency.

• Voltage stress across each switch is reduced,

• Simple control circuitry,

• All the capacitors can be pre-charged.

• The back-to-back interconnection of two multilevel converters of DCMLI
enables bidirectional power flow for balancing the capacitor voltage
levels.

• A large number of ‘n’ yields a smaller harmonic content

• Controlled reactive power flow. 8

 Design Challenges with DCMLI Topology
• It is difficult to control real power flow though diode clamped
inverter because intermediate dc levels tend to overcharge or
discharge without precise control and monitoring.

• Clamping Diodes (high reverse recovery voltage across it in

series connected diodes with high switching frequency devices
such as IGBT, IGCT etc.),

• Unequal conduction duty ratio for each device in the same

phase leg requires unequal current ratings of devices,

• Neutral Point Potential (NPP) variation and Capacitor Voltage

unbalancing problem.

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Sinusoidal Pulse Width Modulation (SPWM)
• Based on carrier signal:
– Alternate Phase Opposition Disposition (APOD)
– Phase Disposition (PD)
– Phase Opposition Disposition (POD)
– Hybrid (H)
– Phase Shifted (PS)
– Super Imposed Carrier (SIC)

• Based on modulating signal:

– Pure Sinusoidal PWM
– Third Harmonic Injection PWM
– Switching Frequency Optimal (SFO) Sinusoidal PWM

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 SPWM
Based on Carrier Signals
Vr Vy Vb
2
C1
1.5

1
C2
0.5

C3
-0.5

-1

C4
-1.5

-2
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02

Phase Disposition(PD) Phase Opposition Disposition(POD)

SPWM SPWM

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 SPWM
Based on Carrier Signals
Vr Vy Vb Vr Vy Vb
2 C1 C2 C3 C4
1
C1
1.5 0.8

0.6
1
C2 0.4
0.5
0.2

0 0
C3
-0.5 -0.2

-0.4
-1
C4 -0.6
-1.5
-0.8

-2 -1
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02 0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02

Alternate Phase Opposition Phase Shifted (PS) SPWM

Disposition(APOD) SPWM

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 SPWM
Based on Carrier Signals
Vr Vy Vb Vr Vy Vb
2 2
C1 C1
1.5 1.5

1 1
C2 C2
0.5 0.5

0 0
C3 C3
-0.5 -0.5

-1 -1

C4 C4
-1.5 -1.5

-2 -2
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02 0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02

Variable Frequency Carrier SPWM Carrier Overlapping SPWM

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 1.5
1
SPWM
Magnitude (pu)

0.5
0
-0.5
Based on Reference Signals
-1
-1.5
0 0.005 0.01 0.015
Time (s)

Pure SPWM
1.5
1
Magnitude (pu)

0.5 Injecting 17 % of third harmonics into reference

0 modulating wave yield approximately 15 % increase
-0.5 in gain over the pure SPWM technique before going
-1
into over-modulation.
-1.5
0 0.005 0.01 0.015
Time (s)

Third Harmonic Injection SPWM

min(Vr,Vy,Vb)+ max(Vr,Vy,Vb)
1.5
1
Voff = −
0.5
2
0
-0.5
Switching Frequency Optimal PWM (SFO-PWM) Method
-1
-1.5
Used for common mode voltage control and
0 0.005 0.01 0.015 harmonic control
Time (s)

Switching Frequency Optimal SPWM

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(SFO-SPWM)
 Switching Frequency Optimal SPWM
(SFO-SPWM)
V  (r, y,b) = V (r, y,b) +Voff

Voff =−
min(Vr,Vy,Vb)+ max(Vr,Vy,Vb)
Triplen harmonics off-set
2
V *
= V * −V
rSFO r offset
Continuously centers all of the three reference
V *
= V −V *
voltage waveforms in the carrier band
ySFO y offset

V *
= V * −V
bSFO b offset

Similar to using SVPWM with the zero voltage state divided evenly at the
beginning and end of each half carrier interval

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 Carrier Signals and Modulating
Signals for 5-Level DCMLI (mf=21, ma=0.8)
2 2

1.5 1.5

1 1

0.5 0.5

0 0

-0.5 -0.5

-1 -1

-1.5 -1.5

-2 -2
0 500 1000 1500 2000 2500 3000 3500 4000 0 500 1000 1500 2000 2500 3000 3500 4000

Phase Disposition(PD) Switching Frequency Optimal SPWM

SPWM (SFO-SPWM)

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 Carrier Signals and Modulating
Signals for 3-Level DCMLI (mf=21, ma=0.8)
carrier 1 vr vy vb carrier 1 vr vy vb
1
1
0.8
0.8
0.6
0.6

0.4 0.4

0.2 0.2
carrier 2
0 0
carrier 1
-0.2 -0.2

-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1
-1
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02 0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02

Phase Disposition(PD) Switching Frequency Optimal SPWM

SPWM (SFO-SPWM)

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 Signals ‘Vmax’, ‘Vmin’, ‘Vr’ and off-set
voltage ‘Voffset’ in 3-Level PD SFO-SPWM
1

0.8

0.6
Vr Vmax
0.4

0.2

-0.2
Voffset
-0.4
Vmin
-0.6

-0.8

-1
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
time (sec)

Voffset signal has frequency three times that of

fundamental output voltage 18
 Harmonic Profiles with 3-Level PD-SPWM
and SFO-SPWM
1000 1000

Line Voltage (volts)

Line Voltage (volts)

500 500

0 0

-500 -500

-1000 -1000
0.1 0.105 0.11 0.115 0.12 0.125 0.13 0.135 0.1 0.105 0.11 0.115 0.12 0.125 0.13 0.135
Time (s) Time (s)

Fundamental (50Hz) = 590 , THD= 20.42% Fundamental (50Hz) = 589.6 , THD= 7.81%
100 100

Mag (% of Fundamental)
Mag (% of Fundamental)

80 80

60 60

40 40

20 20

0 0
0 10 20 30 40 50 0 10 20 30 40 50
Harmonic order Harmonic order

PD SPWM SFO-SPWM

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