System Design using Verilog

Dr. Shaik Rafi Ahamed

Department of Electronics and Electrical Engineering
Indian Institute of Technology, Guwahati

Introduction to Verilog
Lecture - 01
Verilog Operators and Modules

Ok. The title of the course is a System Design Using Verilog. So, in this lecture first, I will
discuss about the need of Verilog for the system design, and what is the design flow to design
any system using Verilog, and then some basics of Verilog ok.

(Refer Slide Time: 00:57)

So, if you this any digital system design normally, so we will use the manual procedure to
design any circuit let us say for example half adder. If you want to design a half adder, so we
will take the number of inputs are two. Because the half adder is capable of adding two bits
of the information and the output will be sum and carry.

So, we will form the truth table. So, we will simplify the Boolean expressions for the outputs.
We will draw the logic diagram. Then we will connect this logic diagram on a breadboard.
We will give the inputs logic 0 and logic 1 through a power supply.

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So, 0 volts corresponds to 0 logic 0, and 5 volts corresponds to logic 1. And to verify the
outputs, we will connect the LEDs at the sum and carry. If sum bit is 1, the LED will glow; if
sum bit is 0, the LED will be off. This is the normal classical method ok.

But the drawback of this normal classical designs is if a circuit consisting of the millions of
gates. So nowadays we are using VLSI and ULSI, Very Large-Scale Integration, and Ultra
Large-Scale Integration. So, in this, the ICs will be containing several millions of the gates.
So, in order to design those ICs containing several millions of the gates, the manual methods
fails because it is very difficult to I mean connect these many number of gates on the
breadboard and check the functionality of the system ok.

So, one of the solutions to design such complex ICs containing several millions of the gates is
a hardware description language HDL. So, using HDL, so this HDL is actually it describes
the hardware of the digital system in textual form. So, instead of using the actual hardware
components, so we will use some sort of the textural form like C program and all ok.

So, because of that the designer can manage the design of the complex circuits containing the
millions of gates. This is the one of the important advantage of this HDL. And another
advantage of this HDL is a working circuit can be easily synthesized. So, we are going to
discuss what is meant by synthesize.

So, synthesize means if you write a program using HDL , so we will get a net list means
which will give the physical connections between the different electronic components. So,
that synthesize circuits can be done by using this HDL. So, synthesis of the given HDL can
be automatically done using Verilog ok. So, that is why this HDL based synthesize is now
dominant design in many of the industries ok.

So, one of the important or famous synthesis tool is synopsys, synopsys is one of the
important synthesize tool. And coming for the general operation that can be performed by
using the HDL. So, HDL can perform the design entry. Once if you design a circuit say full
adder ok, so the entry can be done by using if I take say for example, if you have a exclusive
OR gate for sum if I give the inputs as x, y sum is exclusive OR operation, and carry is AND
operation.

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So, this design can be entered. This can be entered by using a keyword called XOR this can
be entered by using AND ok. So, whatever the design that you are going to get for a system
can be easily entered using HDL. So, the second function of this HDL is design verification.
We can verify whether this particular gate is performing exclusive OR operation or not, this
particular AND gate is performing AND operation or not.

Basically, we are going to check the truth tables. And we can generate the tests means here
this x can be 0 or 1. This can be generated using HDL, x can be 0 or 1 – we can generate the
wave form type of thing, we can generate some sort of this one this is logic 1, this is logic 0
ok. And also we can do the synthesis as I have told. So, synthesis is given an HDL, we can
obtain the actual the circuit diagram.

Then we can do the timing and fault analysis, there are some uses of this HDL. So, there are
two HDLs which are more popular. So, one is Verilog, another is VHDL. The full form of the
VHDL is Very High Speed Integrated Circuit Hardware Description Language. This V stands
for this entire thing Very High Speed Integrated Circuit, and HDL is Hardware Description
Language. But this Verilog is more popular.

So, in this course, we will discuss only about Verilog ok. Once if you understand this Verilog
language, we can easily learn this VHDL also. Again between these two, Verilog is one of the
popular language. So, this Verilog was introduced by a Gateway Design System Corporation
in 1985.

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(Refer Slide Time: 07:21)

Now, coming for the basic design flow. So, in order to design any system, what is the flow
that we have to follow so that finally, we can fabricate a IC. So which can operate at high
speeds, which occupies the less area, which consumes less power ok. So, given a
specification, from the specifications first we have to I mean obtain the behavioral features of
that particular specification, we have to draw the behavioral architecture ok. This is basically
architectural feature ok.

So, here at architectural level, we will stimulate and we will check the functionality, this is
higher level of the design module. So, we will simulate that particular system ok. So, if the
design is ok, then we will proceed for the next step. This simulation can be done using HDL.

Then we will verify the functionality. If functionality is ok, we will go for the next stage;
otherwise we will edit, again we will go for the simulation. So, this process is repeated until
you will get a correct design ok.

So, this behavioral I mean modeling is basically it consisting of the architecture without
giving the actual details of the circuitry. Suppose, if we have the multiplier, so we will
represent by a block diagram. This is a multiplier. But here at this behavioral level, we will
not discuss about the internal details of the multiplier. So, what is the internal circuitry and all
this details will be not covered at behavioral level ok.

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And once this behavioral level is passed using this process, then we will go to the next level
which is called as Register Transfer Logic RTL which is called RTL level. So, this RTL level
basically consisting of different state machines and sequential circuits ok. So, again here also
we will do the same procedure. So, we will simulate using HDL, we will verify the
functionality. If ok, we will go to the next stage; otherwise you will edit and we will repeat
this process until the functionality is correct ok.

Once if this RTL is available, so in a fully automated design this RTL description will be sent
to the synthesis tool ok. This synthesis tool basically produces the netlist of hardware
components. So, what is netlist is? Netlist will give this description of the connections. This
will give connectivity description, how the different electronic components will be connected
ok.

So, once if you know this connectivity of this one, connectivity of the circuit, then we will do
the synthesis ok. So, there are two important synthesis tools are there one is FPGA and ASIC
that we are going to discuss in the coming slides. So, after that, we will get the logic design
this is what is called the gate level ok.

And each gate consisting of the transistors ok, then we will discuss about the circuit design.
So, here at each and every level we will simulate and verify. This also we can simulate and
verify by using HDL such as Verilog. Once all the stages have been passed, so finally, we will
go for the physical design and that physical design will be sent to the tape out for the
fabrication of the IC.

So, in order to I mean obtain an IC which can operate at high speed, low power consumption,
low area, we have to optimize the problem at each and every level. So, we can optimize the
problem at behavioral level, we can optimize the problem at RTL level, synthesis level, logic
design, circuit design. Even in the layout also we can optimize the problem.

Once if you optimize this, we will get an optimal IC which can operate at high speeds, low
power and low area. So, this is about the basic VLSI design flow.

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(Refer Slide Time: 12:49)

So, as I have told there are two I mean synthesis tools one is we can use the field
programmable gate array, FPGA, or we can use application specific integrated circuit ok. So,
each one is having relative advantages and disadvantages. If we go for the FPGAs, FPGA are
cost effective and design flow is simple ok.

So, in FPGA we will be having some standard libraries ok. So, once if you dump this
synthesize circuit into the FPGA, it will use the internal blocks, and it will simulate ok, but
they are not optimized for the various requirements ok. So, if you want to design a particular
IC say for example, FFT – Fast Fourier Transform ok. We cannot optimize this FFT design
using FPGA. For that, we have to go for the ASIC ok.

So, they are less energy efficient and have lower performance than the ASICs ok. So, ASICs
are designed for the application specific for a particular specific application. Even though this
ASIC design flow is more complex, so this will give the optimal design and also it is more
highly energy efficient.

So, in conclusion, normally if we want to have the mass production we will go for the ASICs,
ASIC for mass production. Whereas, for designing a fewer systems, then we will go for the
FPGA ok. So, you see about this synthesis tools ok. This is basic introduction to the HDL.
So, with this we will go for some basics of Verilog how to write the codes using Verilog.

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(Refer Slide Time: 14:53)

So, first I will discuss about the logic values. So, logic 0 can be zero, logic low, false, ground,
so all these are the names for the logic 0. Similarly, logic 1, it can be one, logic high or
power. This is ground and this is power ok. Like this is GND, this is VDD in case of CMOS
circuits. X is a do not care which is unknown; it can be 0 or 1 ok.

So, there is one more state which is called as Z which is high impedance state which is
unconnected or tri-state. So, basically this is something like floating ok. Suppose, if I connect
the output of this gate to the input of some other gate, so if state of this output is Z that is
something like this high impedance state.

So, in between these connections, we have very high impedance which is almost high
impedance means if I take the infinite impedance, it will be open circuit which is almost
equivalent to open circuit between these two means virtually it draws almost 0 current.

Means, if this connection if we do not want to use this connection; this gate will not draw any
current from this output, so that the driving capability of this gate will increase, so it is a high
impedance state.

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(Refer Slide Time: 16:45)

Now, how to represent the numbers in the Verilog ok? So, the basic format of this number
representation is we have to first specify the size followed by radix, then you have to specify
the value. So, we have a different number of systems like binary. We have only 0 or 1; octal –
we can have 0 to 7; decimal – 0 to 9; hexadecimal – 0 to 9, then we have A for 10, B for 11,
C for 12, D – 13, E – 14, and F for 15.

So, totally we have 0 to 15 in hexadecimal ok. So, normally, this binary it can be represented
with either lower case letter, upper case letter B, this with 0 either lower or upper, this is also
D, this is also H.

Then the value consisting of any of these values like 0 to F in case of hexadecimal; x it can be
a do not care, it can be high impedance. Also as I have told in the earlier slide, so the logical
values can be 0, 1, x, z. So, here also this value will be value can be either any one of this 0 to
F, or it can be do not care, or it can be high impedance state.

Here I have given some examples. So, what does it mean? This 4 there will be a dash here.
So, this 4 represents 4 bits. And this b represents binary. And what is the value of that binary
number 1010. This 8 represents 8 bits; h represents hexadecimal; A x, A is nothing but as I
have told this can be either lowercase or uppercase letters A is 10, 10 means 1 0 1 0. This is 1
0 10.

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And this is x is do not care. So, we have 4 bit equivalent of the x is xxxx. So, total 8 bits. So,
this is 12 bits – octal. This is octal can have digit from 0 to 7, so 3zx7. So, because this octal
we have eight different characters, we use 3 bits to represent each octal digit. 3, 3 will be
represented by a 3-bit number. In hexadecimal, 4 bits are required because total 16 different
combinations, whereas in octal we have 8 combinations.

So, this 8 is 2 cube; so, each digit can be represented by 3 bits. In hexadecimal, 16 is 2 raise
to the power of 4. So, each bit will be represented by 4 bits ok. So, this 3 is, this is 3, and z is
3z high impedance, x is do not care, and 7 is 3 ones ok. This is about the number
representation in Verilog.

(Refer Slide Time: 20:06)

So, coming for the arithmetic operations similar to the conventional arithmetic. So, this star
will be used to represent the multiplier, this symbol is used for divide, plus is for add, minus
is for subtract, percentage is for modulus. So, modulus is nothing but the remainder of the
operation.

For example, if I take 10 percentage of 3, so if I divide 10 with 3, 3 3’s are 9, 1 is the

reminder. So, this reminder is represented here ok that is what is called the modulus. So, these
are some examples. This is plus operation 15. This is minus, minus 5; this is plus 5. This is

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multiplication; this is division. This is multiplication, and you have minus value also this. So,
these are the arithmetic operators.

(Refer Slide Time: 21:18)

Similarly, we have logical operators. So, in order to do logical AND, we will use this symbol
ok; and logical OR – this symbol; logical NOT – this symbol. So, in all these cases, each bit
can be either 0 or 1 or x ok. And we are going to perform this operation bitwise if I take say
for example, if A is 1, B is 0, C is do not care. So, this is A and B. So, A is 1, B is 0. So, 1
AND with 0 is 0. If I give for AND gate, one, one input is 0, another input is 1; output will be
0.

So, this will be equivalent to this logical OR operation we have A, and this is NOT, B bar,
this is something like A,Bbar we are going to give. So, A is 1, B is 0, but B bar is equal to 1
ok, output is 1. This will give output is equal to 1. This is OR operation. And the third
example is C OR with B.

So, C is do not care, B is 0. If you perform the OR operation with do not care, we will get do
not care only because do not care can be 0 or 1 ok. If x is equal to 0, 0 OR with 0, so if you
have 0 OR with 0 is 0; if do not care is 1, this is one the second bit is 0 only. So, output is 1.
So, this one means 1; do not care is 0 means 0. So, basically this is do not care ok. So, these
are three logical operations.

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(Refer Slide Time: 23:38)

There are some relation operations. So, this, these are I mean similar to the conventional a
less than b, a greater than b, and less than or equal to in conventional normally we will write
this one, but in Verilog we will write less than and then is equal to side by side. Similarly, this
is greater than or equal to ok.

So, since I have given some examples like a 5 less than or equal to 10, 5 less than or equal to
10 is this operation true or false because 5 is less than 10 ok, this is true. So, the value is 1. As
I have told a logic one can be used for the true also ok. The second statement is false, this is
false. So, the logic value is 0. As I have told 0 can be used for representing the false operation
ok.

Then this is one bit as I have discussed in the number representation this is 1 bit binary do not
care is less than or equal to 10. So, this is two-bit number. This is one-bit number you say do
not care ok. So, this is again do not care because this operation we cannot discuss because
this is do not care unless otherwise we know the value we cannot compare that value with the
other value that is why the outcome of this one is do not care ok.

Similarly, if I use z also, we will get a do not care. So, here about some relation operations.

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(Refer Slide Time: 25:27)

Then equality operation. So, a is equivalent to b will be represented by this. If a is not equal
to b is represented like this. So, here this is case inequality here the, this include x and z also
ok, whereas, here this x and z are not included. And this is x and z are not included ok.

So, two with x and z are included two with x and z are not included. Here also we are going
to perform the comparison operation bit by bit, with zero filling if two operands do not have
the same length. Suppose, if I want to I mean compare 110 with 11 so, we will add 0 here.

Here if I take these 4 bits, binary and this is do not care 0 0 1. This is 4 bits binary do not care
0 0 1; because we are used these three equalities this notation this will include x and z also
because these two are same. This is also do not care, this is also do not care. So, this is giving
true that is why logic 1 ok.

And the second one is this is x, two do not cares are there, whereas here we have only one do
not care, so that is false. This is logic 0. Whereas, here this is 4 bit binary, z is there, z 0 x 1.
This is also z 0 x 1, true. This is z 0 x 1, but this is z 0 0 0, so false. This is false, this is true.
This is true, this is false.

And this is for not equality. So, this is x 0 x 1, this is x 0 0 1. So, these two are not equal
including x and z. So, this is true. This is z 0 x 1, this is z 0 0 0 0 1. So, this is again not

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equal, this is true. So, this is without z and x, 5 is equal to 10 – false; 5 is equal to 5 – true.
So, these are some equality operators.

(Refer Slide Time: 28:09)

Then we have some shift and conditional operations. So, the shift right will be represented by
two greater than symbols; shift left by two less than symbols ok. If I take a is equal to 4-bit
binary 1010 which is 10. If I write d is equal to a right shift by 2 bits, you have to specify the
number of bits ok.

So, what we will get? This is 1010 if we shift by 1 bit, this will become this 1 will go here, 0
will go here, this 1 will go here, and this 0 will be comes to the initial. So, this will come to
this is 0101. And if I shift one more bit here, so 0’s will be inserted here actually basically not
this 0.

So, this will be lost and so many 0s will be inserted here. So, after the shift, so this bit will
move here, this bit will move here, this bit will move here, this will be lost, and a 0 will be
inserted here So, what will be the result? So, 0 0 1 0. So, this is how we can perform the shift
right operation.

Similarly, shift left operation if I write c a less than 2 less than equal this is I mean shift left
by one-bit position. So, shift left means 1010. Shift left means this will be lost, this will come

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here, this will come here, this will go here this will be lost, and a 0s will be inserted here. So,
what will be this one? 0 1 0 0, this is 0 1 0 0 ok. So, this is about shift operator.

Then we have some conditional operator also. So, we have to give some condition with
question mark, we have to give here the expression for the true. After that we have to give the
false expression ok. Like if I take the 2 by 1 multiplexer, so what is the operation here? If
selection is 0, output Y will be the input that is connected to 0 will be B. If selection is 1,
output will be the input that is connected to 1 signal which is A ok.

So, this can be represented using single statement this. Y, selection is the condition this is the
condition if this is true, true means 1, false means 0. So, this true condition is A. If this is true
means if this is equal to 1, output Y becomes A. If this is false means 0, output Y becomes B
ok. This thing can be represented using single statement like this. This is what is called the
conditional operator.

(Refer Slide Time: 31:43)

Then the basic building block of Verilog, if you want to write the code ok, the basic building
block is module ok. So, a module can be an element or collection of the lower level design
blocks ok. For example, if I want to write a simple program for a OR gate simple two input
OR gate, you have to first define the module.

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You have to give some name say OR this is optional, and you have to specify the inputs and
outputs. Output is Y inputs are, a and b. So, this is the first statement that you have to write
for the Verilog code. This is the Verilog code correspond to simple OR gate. After that you
have to write inside this body you have to write the different statements. And the last one is
end module here.

You have to describe your circuit ok. The starting of any Verilog code is module, and the
ending of that one is end module. So, in the module, you have to specify all the inputs and
outputs ok. So, typically the elements are grouped into the module to provide the common
functionality.

So, this functionality will be explained here. So, the module provides the necessary
functionality to the higher-level blocks through its port interfaces. So, these are the ports we
have one output port, two input ports ok. So, this is the general structure of the module ok.
This will be clear while writing the Verilog codes.

(Refer Slide Time: 33:25)

So, continuation of these modules. Everything you write in Verilog must be inside the module
as I have already described. So, in Verilog, a module is declared by the keyword module, and
then you have end module ok. So, each module must have the module name which is of

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course an optional one, and then we have to give terminal list as I have explained in the
previous example.

So, here we have to write module some module name, and then the inputs and outputs. This is
terminal list. So, but the modules cannot be nested this is one of the important property ok.

(Refer Slide Time: 34:17)

So, there are several keywords in the Verilog using which we will write the Verilog code ok.
So, you note that all the keywords are defined in lowercase only this is one of the important
points to be noted. So, there are some examples of the keywords like module is one keyword,
end module, input, output, inout.

If I want to use a dual port which is which will access input as well as output port we will
write inout, and register this reg stands for the register if we want to store some data,
parameter, begin, end, these are some few keywords. So, the keywords, all the keywords will
be understood while writing the modules or the Verilog codes ok.

So, here I have given a simple program like module for the memory we have to specify the
ports. So, this memory will have some clock. So, we are inputting the clock; we are inputting
the address also. So, in order to access this memory, we require the address. Each memory
location will be having some addresses.

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Here we have to specify the address this is some 0 0 0 0, 0 0 0 1 these are the addresses. Then
we can have read enable if we want to read the data from this location, we should have read
enable for this signal through read bar. And if you want to write, so you have to mention
some data in any location I can write this data. Suppose, if I want to write the data into this
one F2H hexadecimal ok.

So, what is the width of the data? This is 8 bits, I have given here 1 1 1 1 0 0 1 0, this is F 2
ok. So, this data width is 8. And what is the width of the address? Of course, in this example I
have given as a 16 ok, depth will be one-bit shifted version by address width ok. This is some
example of a module.

(Refer Slide Time: 36:40)

There are some other examples ok. So, this is the general structure of the module as I have
told. So, module, module name, module terminal list, then the internals, then endmodule. If I
take a simple 2 by 1 multiplexer which I have discussed earlier ok, so I am giving the name
module name as mux, output is y, this is not there, output is y, then the inputs are one
selection line, a, b.

So, first we have to mention this output. These are the input. Later we can explain in detail
inputs are selection a b, and then output is y. And as I have told the operation can be
explained using a single conditional operator which is y is equal to select a, b.

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As I have told if this is true, this value will be the output, output y is equal to the first value.
If it is false means 0, true means 1, output y will be the second value b ok. This is the main
example of a Verilog code for 2 by 1 multiplexer.

Thank you.

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 System Design using Verilog
Dr. Shaik Rafi Ahamed
Department of Electronics and Electrical Engineering
Indian Institute of Technology, Guwahati

Introduction to Verilog
Lecture - 02
Verilog Ports, Data types and Assignments

In the last class, we are discussing about the basics of Verilog. So, we have discussed about
this number representation, logical operators, mathematic operators, conditional operators,
etc. ok.

(Refer Slide Time: 00:52)

So, next one is the data types. So, basically, we have two data types; one is called a net,
another is register. So, in the net data type as I have discussed in the earlier lecture also so,
this net represents the physical connection between the structural elements. Suppose if you
want to connect the output of one gate to the input of other gate so, this is we will call this as
a net.

So, net basically represent the physical connection between the structural elements, and it
carries the value of the signal, the output of this AND gate, if this is 0 or 1 so, this net will
carry this information 0 or 1 and it will transmit to the input of OR gate. Suppose if the

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driving end of the net is floating for example, if I have something like this, I have to connect
to this one, but this is floating.

Then this net value we will assumes a high impedance state z. So, the example of this one is
wire. So, basically, we can define this net as a wire. The second type is a register type. As the
name implies register, which can be used to store the information ok, a register is capable of
storing the information. So, this register represents an abstract storage element.

So, this is again it can be net or wire connected to the register takes the values stored in the
register and can be used as na input for the other circuit element ok. Suppose, if I store this
register, again we are going to define later register can be a scalar or vector ok. Suppose if I
have some block say memory block and if I define this as a register and if I define this wire is
equal to register, whatever the information on the register will be taken care by this wire.

If I connect this wire to some of the other circuit element, then the whatever the information
on register will be carried to this particular circuit element ok. So, the example of this register
type is reg, reg is the keyword used for the register and wire, wire is the keyword used for the
net. So, the default values for the net it is high impedance state, register it is don’t care.

(Refer Slide Time: 03:48)

Next, we can have the scalars as well as vectors ok, the data type can be either scalar or
vector ok. As the name implies scalar so, all the entities representing a single bit is called as a

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scalar whether that bit can be stored or changed or transferred. So, whatever the operation is a
single bit is normally called as a scalar ok example is here wire w1.

If I take this particular circuit ok here, we have three inputs a, b and selection are the inputs
and output is output y whereas this w1 is not accessible to the programmer ok. So, all the I
mean connections which are not accessible neither input nor output, we have to define by the
wire.

So, here only single output, the output of this OR gate is single bit so, we need a scalar. So,
this wire w1 if I define so, this will act as a 1-bit wire. And the other hand vector as a name
implies it is a multiple line that carries signals in cluster. So, basically like if want to I mean
transfer the data from the microprocessor to memory, this is a microprocessor and here we
have some memory suppose if it is having 8-bit data bus, this is D 7 to D 0, 8-bit data bus.

So, this is nothing but actually this is bi-directional. So, instead of writing this D 7 line is this,
D 6 is this so on up to D 0 instead of writing 8 lines separately, we will write using bus ok.
So, such type of the clustering of the single lines is called as a vector ok. So, the example is
we can have the wire with multiple lines msb and lsb ok.

Similarly, register can have some msb, lsb instead of representing all, if you want to represent
this data, you can represent with 7 and 0. So, this is example if I take wire 6 comma 0, this is
a 7-bit wire. So, what are these 7 wires? One is wire 6, wire 5, wire 4, wire 3, wire 2, wire 1,
wire 0. Instead of writing these many wires, we can represent with a vector wire 6 is to 0,
then some Clear so, Clear is the name of that particular wire say.

Similarly, you can represent for the memory also if you have register 0 to 3 or memory 0 to
64 ok so, this represents an array of 64 4-bit registers ok, this is 4-bit register, this represent
this 4-bit register and this is 64 arrays, an array of 64 4-bit registers can be represented in this
way register followed by memory.

And if I write just only simple register m means this is 5 1-bit registers if nothing is written
here only register is there means 1-bit, if 0 to 3 is mentioned this is 4-bit registers ok. So, this
is how we can mention, or you can represent the scalars and vectors in Verilog.

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(Refer Slide Time: 07:50)

Next coming for the ports. So, we have three types of the ports. So, it can be either input port,
output port or bidirectional port inout ok, these are the keywords used for this input port, this
is keyword for output port, this is keyword for bidirectional port ok. So, we can have either
the ports can be either scalar or vector ok.

For example, if I write in input A, B, Cin so, these are all scalars. So, this A, B, Cin are the
inputs ok. We can represent single keyword, we can represent as many numbers of signals as
possible ok. So, we have three signals, input signals where we can represent with input.

Suppose if we want to represent a vector, we have to represent a range. So, this A is 16-bit
width which is, vector B is also another vector, data is another vector. So, this is nothing but
A 15 to A 0 so, this 15 is to 0, A represents A 15 to A 0. Similarly, B 15 to B 0 and data also
data 15 to data 0, but all these three are defined as input ports ok.

So, there are some examples of the output ports also. Output port is defined as Cout it is a
single bit, this is a scalar ok and 0 volts which is ground, MINUS is a minus symbol. A
vector is again if you have 8 outputs, you can represent output 7, output 6 so on up to output
0, we can represent as simply 7 : 0 output.

Similarly, this output we are calling as accumulator, accumulator giving 8-bit. Similar register
in is 8-bit, data out is 8-bit ok. Similarly, you can have inout also you can use here instead of

24
output if a particular port is bidirectional port ok. So, basically, we have three types of the
ports: input port, output port and then, bidirectional port ok.

(Refer Slide Time: 10:25)

Then, there are some event control elements ok. So, we know that in sequential circuits ok so,
we will apply the clock signal so, the sequential circuits can be either edge triggered, or level
triggered. If I take for example, a clock signal; ideal clock signal, this is ideal clock why
ideal? To change from 0 to 1, this is logic 0 logic 1, this is taking 0 amount of the time, to
change from 1 to 0 also, the time is 0 ok.

But practically, it will take some time. If I take the practical clock, there will be a rise time
and fall time type of thing. So, 0 to 1 it will take some time, this is the transistor time required
for changing 0 to 1. Similarly, 1 to 0 also it will take some time. From here to here, we will
be calling one period.

Over a period, a clock whether it can be ideal or practical normally, we will use practical
clock is having four portions; this is one portion, this is another portion, this is third portion,
this is fourth portion. So, the transition from 0 to 1 is called as positive edge or leading edge
and the duration over which the clock is equal to 1 is called as positive level.

And the transition from logic 1 to logic 0 is called as negative edge or falling edge and if
clock is equal to 0, it remains at 0, then this is called as negative level. So, we can define the

25
flip-flops or we can design the flipflops which can be either edge triggered, or level triggered
ok, but normally, this level triggered flip-flops will be having problem with race around
condition.

So, in most of the applications especially in counters and all, we will use edge triggered. See
in order to represent this edge triggered and level triggered so, we have to represent like at
whether a positive edge of the clock clk, this is positive edge is this, this positive edge in
Verilog will be represented by posedge means whenever the positive edge occurs, then only
the particular operation will take place ok. So, Current State is equal to Next state.

If I take the flipflop say D flip-flop with a clock this is input D, this is output Q, this is clock,
this is positive edge triggered. Negative edge triggered normally we will follow the notation
like a bubble here. If I take this clock, simply if we write clk, D, output Q, this is negative
edge. So, distinguish between positive edge and negative edge, we will place a bubble and
without bubble ok.

So, the meaning of this one is in case of D flip-flop, the output is equal to input, but when
does this output becomes input? Q is equal to D only, but at a very positive edge ok that is
what we are going to explain here. So, at a very positive edge, Current State is equal to Next
state ok. So, whatever the current state, it will be equal to next state means simply the output
will be transferred to the input.

And if I take another example where this is a level triggered ok, at A or B, output is equal to
A AND B, this is AND operation between A and B. So, in the previous lecture, we have
discussed this AND operation as A, B say output Y is equal to this, this is also AND
operation.

We just I mean understand the difference between these double AND and single AND. So,
this particular AND operation is called this is binary operation whereas, this particular AND
operation is called unary operation. So, this will take this A and B as a whole, this can have
any number of the bits and it will perform the AND operation whereas, this operation is
bitwise ok.

26
If of course, they are single bit, both will be same. If A and B are having multiple number of
the bits, then unary operation and binary operations are different so, binary you cannot
present for more than 1-bits ok, you have to represent you have to AND with each and every
bit whereas, here, as a whole you can perform this operation ok.

So, normally, this type of operation will be used in the data flow modelling that we are going
to discuss in the coming slides ok. So, this is Out is equal to A AND B means so, this output
of this AND gate will become A AND B, this will be executed see whenever a positive edge
occurs when A is equal to 1 or B is equal to 1.

If I apply here so, at this point when A is equal to 1 or when B is equal to 1, then only this
particular operation will be executed here, here and all ok otherwise, this output will remain
in the previous state ok. So, this is about the event control. So, we can control the events
based on whether this is a positive level or positive edge, negative level or negative edge ok.

(Refer Slide Time: 18:04)

So, the next I mean operation is assignments. So, we can assign some variable to the some
other variable ok. So, there are basically two types of these assignments one is called
continuous assignment, another is procedural assignment ok. Again, in the procedural, we
have two types again this is blocking and non-blocking. Again, this will be used with data
flow modelling ok.

27
So, in continuous assignment so, as the name implies, we will assign values to the nets, net
can be either vector or scalar, this we have already discussed in the earlier slides ok. Here,
basically we are going to assign some values to the nets, it can be vector or scalar. So, when
does this particular value will be assigned is so, whenever the right-hand side value will
change.

So, for example, if I take this assign, assign is the keyword used for the either continuous
assignment or procedural assignment, whether it can be blocking or non-blocking so, for all
the assignments, the keyword is assigned. Here in this example, I have given assign out is
equal to in1 AND with in2, this is actually as I have told this is behavioural, this is unary
AND operation.

So, they will be triggered whenever in1 or in2 will change, this is AND gate output is out,
in1, in2 ok. So, whenever the value of the right-hand side, right-hand side is this, in1 and in2.
So, whenever in1 changes or in2 changes, then only this particular instruction will be
executed ok otherwise not. This is called continuous assignment.

Whereas the second type of assignment is procedural assignment. So, this drive are the
registers, this is normally used with the nets. As I have told there are two types of the data
types, one is net, and another is register. So, to deal with nets, we will use the continuous
assignments and to deal with the registers, we will use procedural assignments ok.

So, normally, this procedural assignment whether this is blocking or non-blocking always
uses with always and initial, there are two more keywords so, these keywords will be used in
this procedural assignment and also in addition to there are two more which is called as initial
begin and end.

So, these are other two keywords we are going to use ok. So, always this procedural
assignment in addition to this assign, we have to use always or initial and begin and end ok.
So, this will be clear if I give some examples in the next slide. Now, they are triggered when
the flow of execution reaches them, this is sequential.

So, for here, we have some assign statement so, this will be executed so, first this will be
executed, this will be executed, this will be after that this will be executed in sequence like C

28
whereas, here, this will be triggered whenever the one of the inputs that is right-hand side will
change ok that is the main difference between the continuous assignment and procedural.

Procedural is in a sequence that will be executed whereas, in continuous, whenever the

right-hand side expression changes, then only that particular assign will be executed. So, all
these statements inside this initial statement constitutes initial block. Similarly, all the
statements in always constitutes always block.

So, initial block starts from the time t 0 and execute exactly once during the simulation. If
there are multiple initial blocks, then all will be executed simultaneously at t is equal to 0 ok
and the execution completion that depends upon the instruction that are present in the initial
block ok. This will be clear if I give the examples now.

(Refer Slide Time: 22:55)

So, again two examples, one with initial, another with always ok. So, this is initial or always,
always you have to use begin and end. Say whatever these statements that are present
between this begin and end are called as this is called initial block and this is called always
block.

So, when does this initial block will be executed? When does this always block is executed?
As I have told this will start at time t is equal to 0 and this will execute only exactly once, this

29
is some sort of initialization as the name implies. So, initial Sum I have defined for 0, initial
Carry also I have defined to 0 whereas, in always so, there is a condition A or B.

So, Sum is equal to this is exclusive OR operation in procedure or this data flow modelling,
this is XOR operation, unary exclusive OR operation and this is unary AND operation. So,
we know that for half adder Sum is equal to A exclusive OR B and Carry is equal to A AND
with B ok.

So, when does these two will be executed? Whenever A changes or B changes because if A
or B changes correspondingly, sum and carry also will changes ok that is always at A or B,
these two will be executed whereas, here this will execute only once at time t is equal to 0 ok.
So, that is the main difference between this initial and always blocks ok.

(Refer Slide Time: 24:54)

So, as I have told in procedural, you have two types of assignments again so, one is blocking
assignment, another is non-blocking assignment ok. As the name implies blocking this will
block, non-blocking means it will not block the other operations ok. So, in blocking
assignment, they are executed in the order they are listed ok.

And the main difference is we are going to use is equal to operator in blocking assignment
whereas, in case of non-blocking assignment, we are going to discuss in the next slide, we are

30
going to use less than equal to ok, this is the one of the main differences between blocking
and non-blocking assignments.

So, I have given the example of the blocking assignment. So, I have defined the registers as a,
b, c, register 1, register 2 and I have given the initial, begin and end ok. So, I have given this
a register I have defined with 1, b with 0, c with 1, this is this will happen at t is equal to 0 ok.
So, there are I mean different ways to represent these delays. So, this symbol hash symbol
represents delay ok.

If these delays are not there, all these statements will be executed at t is equal to 0 because
these delays are present here ok. So, if I take this timescale at t is equal to 0 this is time, at t is
equal to 0 at this point so, a will become 1, b will become 0, c will become 1 and this
represent that after 10 seconds, if I give this in seconds, after 10 seconds somewhere here at
10 seconds.

The register 1 is assigned with here this register 1 will be assigned with this is the I mean
number representation that I have discussed in the earlier lecture so, 1 stands for 1-bit, b
stands for binary, the bit value is 0 so, this is equal to 0. Then, the second statement
represents there is some other delay 5 so, after 5 more delays means total becomes 15 so, this
will add together ok.

So, at this point, c will be assigned to register 1 so, c was initially at t is equal to 0, 1 now, c
will become register 1 value which is 0. After 5 more seconds at 20 seconds, register 2 is
assigned to b value, b value was 0. This is how this all these statements will be executed in
sequence ok. If these delays are not there, all will be executed at t is equal to 0 only ok. So,
this is the example of blocking assignment and here, we are going to assign with is equal to
symbol ok.

31
(Refer Slide Time: 28:28)

So, on the other hand, the other type of procedural assignment is non-blocking assignment.
As I have told so, here we will use less than or equal to, but do not confuse with this one, this
is not equal, less than or equal to ok, this is only assignment this is not less than or equal to,
this is only the notation, but exactly not this is a less than or equal to ok.

So, this will be assigned by this operator and a non-blocking statements does not block the
execution of the other statements in the list. So, unlike this previous one, here unless
otherwise I will execute this one, I cannot execute this so, this particular statement is
blocking this statement and also this statement.

So, this particular statement is blocking this statement ok that is why the name blocking. So,
this particular statement is blocking these two statements whereas, in case of non-blocking as
the name implies so, the execution of the current statement does not block the execution of
the other statements ok.

So, this will be a clear with this example. So, always at positive edge of the clock, begin and
end is required whether it is a I mean blocking or non-blocking assignments so, what you
have defined is B is equal to A, C is equal to B, D is equal to C so, these three statements will
be executed simultaneously.

32
So, this statement will not block this, this, this statement will not block this ok, like in case of
the previous blocking assignment ok. So, at every positive clock edge so, B is defined with A
so, B will become A and C will becomes B, but the new value of B is A initially, some value
will be there ok.

So, whatever this C will be assigned is this is old B because this statement and these
statements will be executed simultaneously unless otherwise this is executed, we cannot
assign this value here so, the value that is assigned to C will be the old B. Similarly, D is
assigned to C means this is not this particular new C, this is old C. So, see how we can
execute this non-blocking statement without blocking the other statements ok.

(Refer Slide Time: 31:23)

Then coming for this different type of Verilog modelling or coding or modelling. Basically,
we have broadly we can classify into three modelling so, one is called behavioural, another is
called data flow, another is structural. Of course, in structural, I will define this as a two, one
is gate level as well as switch level or transistor level.

This is low level of abstraction so, we will have all details of the circuitry, and this is high
level, and this is medium level, moderate one ok. So, this behavioural is exactly same as the
C type of the programming. So, it becomes easier to write the behavioural code, but it will
not be optimized ok.

33
So, we are going to represent with some blocks only ok, the system some sort of the
architectural type of thing ok, this is architectural behaviour we are going to multiplication
say y is equal to a into b, this is multiplication, we will not mention what is the operation
inside this, this is only simple multiplication. What is the architecture inside this multiplier?
We will not mention, this is MUL will take a block with a and b so, output y is equal to is a
into b.

So, what is this circuitry that performs the multiplication of a and b will not be considered at
behaviour level ok because of that so, this will design its own multiplier and it will perform
this y is equal to ab so, in that way this is not optimized whereas, in data flow, normally we
will use a RTL type of modelling.

So, we have some details of this, but not gate level ok whereas, here, we will be having the
complete circuitry of the multiplier either in terms of logic gates if it is gate level, if it is
switch level even we have transistor ok so, this will be the more detailed one so, we can
easily optimize this because we know the entire internal circuit of this one, we can provide
some pipelining, parallel processing, some sort of the optimization techniques and we will get
mostly optimized design here.

So, if want more optimized design, we have to go for the structural ok, but the problem is for
the complex systems so, structural design becomes somewhat difficult ok, it will be
consisting of thousands of millions of the gates so, it becomes difficult to I mean write the
structural modelling. So, for normally the complex systems will go for the behavioural. They
are simple systems; it is better to always use structural and this data flow is in between ok.

So, I will explain this with an example so that we will get the clear difference between these
three types. So, of course, I am not going to discuss now here the switch level ok, I will take
one example. So, I will discuss how this behavioural code will be appears data flow and
structural ok.

34
(Refer Slide Time: 35:14)

We have taken a simple example of Half Adder. So, behavioural so, half adder will be taken
as a simple block, I do not know what is the circuit inside this, I will take as a block which is
plus block with in1, in2 inputs, output is sum, carry. So, you have to define this, this is
module name you have to write, this is module is the keyword and this adder underscore b, b
stands for behavioural is the name of this module.

This is optional one, this is name of the module and we have to mention all the inputs and
outputs here and we have to clearly define using input, output ports as we have discussed in
the earlier slides, in1 or in2 are the input ports, carry and sum are output.

Then, here we will write a single statement like assign carry, sum is equal to in1 plus in2 ok.
So, this addition is high level construct, the Verilog compiler will generate the code for the
addition ok simply it will add and whatever the sum is assigned, sum is a resulted that will be
assigned to sum, carry resulted will be assigned to carry. I do not know what is the circuitry
inside this, just this is abstract level modelling.

35
(Refer Slide Time: 36:48)

On the other hand, if I use this data flow design, these things are same, I have given just name
as d for data flow, this is optional one so, the remaining all are these are same except for the
name I have changed. Then here, we will use assign statement as I have told assign statement
ok. In this we are going to use blocking statement so that we can define this sum and then,
carry ok.

So, assign sum is equal to this I have told, this is unary exclusive OR operation. So, sum is
nothing but exclusive OR between both the inputs, carry nothing but this is unary AND
operation, then end module. So, this is somewhat I mean better than the previous model. Of
course, this is also not giving the complete details ok, but we are going to perform this
exclusive OR and AND operations.

36
(Refer Slide Time: 37:53)

And the low-level modelling is a structural design ok. Here also this I have given as s name
as for structural otherwise, these three statements are same, here we need the circuitry so,
what is the circuitry of this one ok? Carry should be AND operation, sum should be exclusive
OR operation. So, we are defining this as gate 0, gate 1 ok.

So, we have to write directly AND gate, OR gate, we are going to use primitives, and is the
primitive used for the AND gate or XOR is the primitive used for the XOR gate ok. So, AND
g0 is the gate name, this is optional, you can give any name here.

Then, you have to mention the output followed by the inputs so, one output carry, two inputs
because we already define this input in1 and in2 as input through the input port declaration,
sum and carry we have defined as output port using this declaration. So, the similarly
exclusive OR the sum is output, in1, in2 are the inputs this is endmodule.

So, here we should know this gate level circuitry of whatever the circuit that we are going to
model ok. Unless otherwise you do not know this gate level circuit, we cannot write the code
for structural design ok that is why this is more optimized ok. So, there are about three
different things and in structural also we have instead of gate level, you can have switch level
also.

37
Here, I have given just a simple example of this half adder to understand the difference
between these three types of the modelling. So, in the coming lectures, we will discuss in
detail about each type of the modelling. So, of course, first I will start with the structural
modelling which is gate level, then I will discuss about the switch level, then I will discuss
about the data flow, these two comes under structural, then I will discuss about the higher
level, which is called behavioural in detail with some examples ok.

Thank you.

38
 System Design Through VERILOG
Prof. Shaik Rafi Ahmed
Department of Electrical and Electronics Engineering
Indian Institute of Technology, Guwahati

Introduction to Verilog
Lecture - 03
Basics of gate level modeling

(Refer Slide Time: 00:34)

Ok. Today, we will discuss about the gate level modeling. As we know that there are four
levels of design description, we take the design description. This can be done by using four
ways. So, one is gate level – this also is called as a structured level. Then we have the circuit
level – this also is called as switch level. And we have the data flow level, and behavioral
level.

So, out of these four, so this gate level description is gradually easier to describe the design,
basically all will be used to describe the digital designs. So, first we will start with this gate
level modeling. So, in gate level modeling, so this basically uses the primitives of all the
logic gates, primitives of all the combination logic gates are used to describe the design.

39
So, what are the basic combinational logic gates? Such as NOT gate we have primitive NOT.
We have AND gate and, we have OR gate or, NAND gate nand, NOR gate nor. So, there are
already available in the VLSI, Verilog library.

So, there are nearly 26 different primitives are available in Verilog library. So, this not only
uses this logic gates, but also in addition to these this also describes the interconnections of
the wires. So, if the different, I mean primitives of Verilog OR, NOT, AND, OR, NAND,
these are all n input primitives.

So, here n varies from 1 to any value. If I take NOT gate, n is equal to 1, for AND gate, you
can have any value of n ok for OR gate also, NAND gate, NOR gate, so n is n can be greater
than or equal to 2. So, minimum two inputs are required, this is greater than or equal to 2.

(Refer Slide Time: 04:52)

So, there are some primitives which will be having multiple outputs, n output primitives such
as you have buffer buf. And you have bufferif0, bufferif1. So, this can have the multiple
outputs.

If you take a simple buffer, the symbol of buffer is same as the NOT gate or inverter except
for the bubble at the output side. So, this will have some input, some output. In terms of the

40
voltages output is equal to input. If you give the logic 0, 0 volts, output is also 0 volts. If you
give 5 volts as the input, output is also 5 volts.

Then what is the need of the buffer? So, buffer is basically this will act as a current amplifier.
So, if you want to drive the large current capacity loads, so normally we will use buffers. So,
this is just two state buffers, you can call this one as a two-state buffer it can take only two
states. So, states are 0 or 1.

So, there are some buffers which are called as tri-state. This is tribufferif 0, tribufferif 1. So,
the difference between the tri state buffer and a two-state buffer is as the name implies in tri
state buffer, we have three states. So, this is a buffer. In addition to this, we have one control
signal. This is control signal; this is input, and output.

So, the operation is if c is equal to 1 implies output is input. If c is equal to 0, output will
become state called high impedance state Z. Z is high impedance state that means if I want to
connect this to some device, this will offer a high impedance path; the resistance of this wire
will become high impedance.

As a result of that, this will act something like an open circuit, almost like open circuit, so
that this does not draw any current. As a result of that, we can increase the current capability
of the output of this particular gate. So, this is if c is equal to 1, output is input; c is equal to 0
output is Z.

This type of buffer is called tri buffer, triif1. If I place a bubble here means the operation is
reverse to this one. If c is equal to 1, high impedance state; c is equal to 0, output is equal to
input. This type of buffer is called triif0 buffer ok. So, whether you take a two-state buffer or
tri state buffer, they can have multiple outputs, an output primitive.

How they can control this multiple output is? So, we can connect output of this particular
gate. Suppose, if I take this output, this can be connected to many devices. This is device 1,
this is device 2, v is going to control these number of devices that can be connected to a
single output.

Suppose, if you have this is 10th device, this is what is called fan-out you might have studied
in your digital logic course. So, if the current required to drive this one is say 1 milliamp, this

41
is also 1 milliamp. If I assume that all belong to same family, this is 1 milliamp. If this output
is capable of giving 10 milliamps of the current, then I can connect 10 of these devices which
draws 1 milliamp of the current, then fan-out is called as 10.

So, depends upon the current capacity of these devices and the current that is supplied by the
output of a gate, we can connect multiple outputs ok. So, this is what is called n output
primitive. This n is nothing but the fan-out. So, like that we have 26 different primitives in
Verilog library.

(Refer Slide Time: 10:18)

So, coming for our basic circuits if I take a simple AND primitive AND gate because any
digital circuit can be implemented by using these basic gates such as NOT, AND, OR. Using
these three gates, we can construct the remaining gates such as NAND, NOR, exclusive OR,
exclusive NOR and so on ok. So, the basic the primitive of this one is you have to use
lowercase letter, Verilog is a case sensitive language.

So, you have to write only lowercase letters, and so within the bracket you have to represent
first the output. So, output will be normally only one for the AND gate we can have any
number of the inputs. Suppose, if you have 8 inputs I 1, I 2, say I 0, I 1 so on up to I 7. So,
this will represent an AND gate whose output is 0 whose inputs are I 0, I 1 so on up to I 7.

42
So, instead of writing this, you can simply write using this primitive, and with this output
followed by input ok.

So, now, if you take the two input AND gate say A and B are the inputs, Y is the output, Y is
given by AB. So, here each value A can take four different values here. This is A, this is B.
So, A can take either 0 or 1 or it can be X which is a do not care it can be Z which is high
impedance state.

This is do not care; this is high impedance state. As I have already discussed what is meant
by high impedance state means it basically draws almost 0 current. Similarly, B can take 0, 1,
X and Z ok. So, what is the output value Y for different combinations? So, we know the
ordinary combinations like 0 0, output is 0. If any, one input is 0, output will be 0.

So, if B is 0 regardless of A whether this is 0 or 1 or X or w, output is 0 ok. Similarly, when A

is equal to 0 regardless of B, B is 0, 1, X or Z, output will be 0. So, this row and this column
both are 0s. Now, for 1 1 output is 1; 1 X output is X. 1 Z, here there is a logic, 1 Z is also X.
The reason for this one is supposing if I have an input which is floating I can connect this
input to either ground, I can connect this input to VCC which is plus 5 volts ok.

So, in this case, this is logic 0, this is logic 1. Suppose, if an input of the gate is floating, so I
have connected here logic 1, 5 volts, this I have not neither I have connected this to be 5 volts
nor I have connected this to ground this is floating. So, this is what the meaning of Z. Z is
high impedance state; this is almost open circuit type of thing. So, it is coming from some
other gate, but this is almost open circuit.

So, when a gate is floating, so normally NAND logic if input is floating, floating input will be
taken as logic 1 in case of TTL gates – Transistor Transistor Logic. Whereas, the floating gate
in CMOS logic is a do not care ok because this is going to I mean on both the NMOS and
PMOS transistors thereby the circuit oscillates.

So, a floating input is there in CMOS, the CMOS causes CMOS circuit oscillates ok. In TTL
it is really taken as 1, whereas in CMOS this will oscillate means do not care basically. So, if
one input is 1, Z in case of this I mean TTL gate is 1, but normally it is CMOS gate because

43
the circuit oscillates. So, it is fully taken as a do not care so that is why this will be do not
care. If one input is 1, other input is Z, this will be taken as a do not care.

So, similarly, X 1 is X, X X is also X, X Z is also X. So, 0 Z 0 is 0, Z 1 is X as we have

discussed earlier like here we have Z 1 is X. And then we have Z X is also X, Z Z is also X.
So, this is I mean the logic operations of AND gate for all combinations of the inputs.
Similarly, can you have for OR gate the other gates also NAND, NOR and remaining gates
ok. So, now, using these basic gates, how to I mean write a Verilog code.

(Refer Slide Time: 16:08)

So, I will discuss a Verilog code for a simple circuit. For and or inverter 4 input circuit. This
is and or inverter 4 input circuit. As we have discussed this Verilog has twofold operation,
Verilog can be used for describing the hardware given a circuit you can describe by using the
key words.

We can describe the circuit or we can test the designed circuit ok. First, I am going to explain
with an example how this Verilog code can be used for describing a circuit ok. The circuit
that I have taken is AOI4 means this is something like we have 4 inputs, 2 inputs for this
AND gate, 2 input for this AND gate a b, c d, then we have OR gate and inverter. I am going
to club these two together, so that this becomes an OR.

44
Basically, we have AND gate, OR gate, NOT gate inverter AOI. These 4 represents four
inputs. Output let us call as Y. So, I want to describe this instead of drawing this diagram, I
want to describe by using Verilog code ok. So, how to write the Verilog code? So, whatever
the code that we have to write, we have to write between the module and end module.

So, the starting this one is module, we have to give some name. So, I am giving the name of
the module as AOI4 itself. After reading the program, the last keyword is end module. So, in
between this, so whatever the description that you have to write. So, AOI followed by here
you have to specify the inputs and outputs of the circuit ok. So, we have one output and four
inputs. First you have to specify output y, then the inputs a, b, c, d.

So, after that, we require a semicolon here. Then you describe what are these values output y
semi colon input you have a, b, c, d semicolon. So, this instead of writing these three I mean
key words, this can be described in a single keyword also like module is same, the name is
also you can write the same name AOI4.

So, within this bracket, here itself you can write output y comma input. You have to give
some tab. Here you have to give the gap after this output or after this input a comma b
comma c comma d. So, this single keyword is equivalent to these three. So, you can write
anyway ok. So, I am using this notation only. So, this definition of the input and output ports
also you can give here itself ok.

Now, coming for this one. So, we have four input ports, these will be connected to the input
port. And this will be connected to the output port. In between, if you want to interconnect
this gate ok, we require some wires. This is similar to the physical connection that you are
going to give in a digital laboratory.

So, I want to connect the output of this AND gate to the input of this NOR gate. So, I require
a wire, I will call this one as w 1, similarly here also we require another wire w 2. So, we
have to define this wire. Wires are basically used to connect the gates in the design ok, wire
w 1 comma w 2 semicolon.

Now, I can give some name for this AND gates and OR gates ok. So, this I will call as A 1,
this I will call as A 2, this I will call as N 2. We can directly give this as a NOR, or we can

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give OR and NOT also, this is up to you ok. So, I am writing this primitive of the AND gate
is as we have discussed in the earlier slide is and – lowercase and. And in the parentheses, we
have to first write the output which is w 1. And you have to give the name because there are
two AND gates. To distinguish between these two, you can write a name.

So, I am defining this AND gate as A 1. For A 1, what is the output? w 1 comma the inputs
are a comma b. Similarly, there is second AND gate A 2, output is w 2 the inputs are c and d.
Now, the final output y will be the output of the NOR gate. So, you can write directly NOR
whose output is y, the inputs are w 1 and w 2. These w 1 and w 2, we can write in any order
ok, so that is all.

This is the description of this given circuit which is called as AND, OR and inverter circuit.
So, we can also write this NOR as otherwise this you can write using two I mean keywords
one is you can use OR. So, you have to define one more wire here ok. If want to right this
NOR as the inputs are w 1, w 2, and this is y. This is equivalent to OR followed by you can
define another w 3.

In that case, you have to define here another w 3, then NOT gate this is finally, is y. So, OR
you have to write here w 3 in that case output is w 3 comma w 1, w 2 semicolon NOT y
comma w 3. So, this is how if you write this program, this will give the description of the
given circuit ok.

So, this is I mean Verilog is having two folded uses, one is it will describe the circuit. So, we
can test the designed circuit. So, you have some design. So, normally, how to test the design?
Normally, we will connect using the ICs and I will test the functionality.

So, whereas, using Verilog code, you can test the functionality of the design by writing the
Verilog code ok. So, I will consider another example of how to I mean test the design. So, for
that, I have to first discuss how to design the digital circuit.

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(Refer Slide Time: 23:44)

We know that digital circuits can be broadly classified as combinational circuits and
sequential circuits. So, combinational circuit is a logic circuit, where the output at any time
depends upon only the present input without regard to the previous outputs ok. Whereas, in
case of sequential logic circuits, the output not only depends upon the present input, but also
on the previous outputs.

So, you need some memory in case of sequential to remember the previous output. So, this
requires some memory. And there will be some feedback connection from output to input ok.
So, first I will discuss the design of combinational circuits and the corresponding Verilog
codes. CKT is the symbol for the abbreviation of circuit ok. So, there are certain rules for
design of combinational circuits ok.

So, step 1 for the design of the combinational circuit is, so we have to define the problem.
From the specifications determine, so you will be given the specifications, determine the
number of inputs available and the number of outputs required. Then step 2 is assign letter
symbols, to all the inputs and outputs.

3rd step is drawing the truth table which describes the relation between the input and output.
Then next step is writing the Boolean expressions for all the outputs and simplify by using

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K-map. And next step is this is the last step, draw the logic diagram. Once the logic diagram
is obtained, to check the functionality, normally we will connect using the ICs ok.

For simple circuits, which contains a smaller number of gates, we can test manually, but in
case of VLSI circuits where millions of the gates are there. Then we have to go for the
computer aided designs. So, here in order to test this logic diagram that we have obtained
from the design, so you can write a Verilog code and you can run the simulation. You can
give the different combinations of the inputs, and you can check the outputs ok.

So, in order to I mean explain this design rules or design steps, I will take an example of
design a 3-bit squarer. So, the problem statement is given how to obtain the logic diagram
which I mean squares the 3-bit input value ok. So, the first step is we have to determine the
number of inputs available; it is already given that 3-bit. So, number of inputs are 3.

Then how to find out the number of outputs required. So, basically this circuit has to square
the input number, we have 3-bits say you have a 2, a 1; a 0 is the 3-bit number. This is 3-bit
squarer. So, how many outputs are required? How to find out this? So, what is the maximum
3-bit number ok? So, the maximum 3-bit number is all the a 2, a 1, a 0 should be 111. This is
in binary.

This is 7 in decimal. If I square 7 in decimal, what is the value 49 is the decimal value, sorry,
this is decimal 10 stands for the decimal base. So, what is the binary equivalent of 49? So
many bits are required at the output because you have to accommodate the maximum
possible value also.

So, 49 if you convert into binary 24 are 1, 2 12 are 0, 2 6s are 0, 2 3s are 0, 2 1s are 0 1, 2 0s
1. Until the quotient is 0, you have to stop here and you have to read this value from bottom
to top. So, what is that value is 11001. If you want to verify, you can verify also. The weight
of this one is 1, in decimal this is 2, this is 4 powers of 2, this is 8, this is 16, this is 32.

So, basically you are adding 32 because 1, 32 plus 16 which is equal to 48 plus 1 is 49. So,
this in binary form is 110001 in binary. So, we require 6 outputs. So, 6 outputs are required.
So, starting with y 5, y 4, y 3, y 2, y 1, y 0 ok. I am assembling letter symbols, and finding
this one. The second one is I am assigning the letter symbols I am assuming that a 2, a 1, a 0

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is the, this is second step also I have combined this. Step 1 and step 2, I have combined
together.

So, I have assigned the letter symbols for the inputs as a 2, a 1, a 0, and outputs as y 5 to y 0,
y 5 is the MSB; y 0 is the LSB, y 5 I have called as MSB. You have to clearly define this y 0
is LSB. MSB stands for most significant bit; LSB stands for least significant bit.

(Refer Slide Time: 31:56)

In the third step, you have to draw the truth table. For all the combinations, how many
combinations are there? Because inputs are 3 a 2, a 1, a 0, so we have 8 combinations;
outputs are 6 right, so y 5, y 4, y 3, y 2, y 1, y 0. So, we take all the eight combinations 0 0 0.
So, if you want you can write decimal value also here, decimal input value decimal output
value, so that we can easily understand this problem decimal output decimal input.

So, 0 means 0, 0 square what is the decimal equivalent value 0 only. So, what is 6 bit
equivalent of 0? All 0s. Decimal 1, if the input is decimal 1, the representation in input binary
is 001. 1 square is decimal is also 1. How to represent 1 using six bits 000001. If the input is
2, the binary representation of 2 is 010.

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So, the decimal square of this one is 4. So, how to represent 4? 000100. If the decimal value
is 3, the binary representation is 011. 3 squares are 9. How to represent 9? 001001. These are
basically the weights you can add. This weight is 1, 2, 4, 8, 16, 32.

So, to get 9, you have to add 8 plus 1 ok, 4 100. So, this is basically 16, 16 is directly there,
so 010000. 5, 101; 5 square is 25. To get the 25, it is 16 plus 8 is 24 plus 1. So, 011001. 6 is
110; 6 squares are 36 – 32 plus 4, so 100100. 7, 111; 7 is 49. We have obtained this 32 plus
16 plus 1. So, you see the truth table so which will describe the given problem for all the
combinations of the inputs it will give the output square value.

So, what is next step? Step 4 is you have to obtain the Boolean expressions for the all the
outputs and we have to simplify by using K-map ok. We can see that one even if you simplify
also you will get same thing y 0 is nothing but this is 01010101 a 0 also 01010101. So,
simply y 0 is equal to see by observation you can do it by using k map also you will get same
thing. This is by observation.

And y 1 is always 0. And y 2 is what are the min terms? y 2 is sigma m. So, wherever
Boolean expression you have 1, this 1 is correspond to this min term 2, 2 this min term is 6.
You can use the k map basically the inputs are a 2, a 1, this is up to you can write in any way
I am writing a 2, a 1, a 2 is MSB, a 0 is LSB, or you can write a 2, a 1 here, and a 0 here.

So, in any case, you will get the same final expression. So, we know that we are going to use
gray code to remember the rows and columns 0001. If it is binary, 1011; if it is a gray, 1110.
So, this box number is 2, 2 means 0 10, 010 is this is 2. And 6 is 110; 110 is this ok. This is
two box combination.

So, therefore, y 2 is equal to. So, here the variable that is changing will get cancelled a 2 is 0
here, a 2 is 11 here. So, a 2 will get cancelled, a 1 is constant at 1. So, you have to take
without complement, whereas here a 0 is 0. So, this is a 0 bar a 1 ok.

Similarly, you can get y 3 as sigma m y 3 is the min term is 3, 5. So, this is a 2, a 1, a 0, 00,
01, 11, 10, 01, 3, 5. 011 is 3; 5 is 101. So, this is nothing but just there is no I mean
combination at all. This is single box combination, this is single box combination. So, you
will have y 3 is equal to this expression is a 2 bar a 1 a 0 plus this one is a 2 a 1 bar a 0.

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So, a 0 is common. You can write this one as this is y 3. This is equal to a, a 0 is common,
then it is exclusive OR between a 2 and a 1. So, a0 times a 2 exclusive OR with a 1; y 4
sigma m min terms are 4, 5, 7. So, 00, 01, 11, 10, 01, a 2, a 1, a 0. So, 4, 5, 7, 100, 5 is 11
101; 7 is 111. So, this is two box combination; this is another two-box combination.

So, therefore, y 4 is this expression is a 0 will changes. So, this is a 2 a 1 bar, and this one is a
0 and here a 2, say it is common. And similarly, y 5 is equal to sigma m 6, 7. So, if you
simplify this, you will get 00 01 11 10 a 2, a 1, a 0, 6, 7, 110, 111. This is two box
combination. This is simply y 5 is a 2 a 1. So, we have the final expression. Then we have to
draw the Boolean the logic diagram ok.

(Refer Slide Time: 40:07)

So, I will draw here the expressions for y 0, y 1. y 0 is a 0, y 1 is 0, y 2 is y 2 we have got this
y 2 as a 0 bar a 1; y 3 is a 0 a 2 exclusive OR a 1; y 4 is a 2 into a 1 bar plus a 0 a 2 into a 1
bar a 0; and y 5 is a 2 a 1 right, a 2 a 1. So, last step is we have to draw the logic diagram. So,
you can draw this logic diagram using gates.

Now, see not I mean write the Verilog code correspond to this one module using these
Boolean expressions I have directly I am writing the Verilog code ok, or otherwise you can
draw the logic diagram, so that it will be easier. So, this will be y 0 is a 0, you have three

51
inputs a 0, a 1, a 2, and the corresponding complements. This is how you can draw the logic
diagram easily. You have a 0. And if I connect through the NOT gate a 0bar.

This is a 1. If you connect the NOT gate between this, you will get a 1 bar, this is a 2, this is a
2 bar. So, we have a NOT gate. So, to get this is a 0 directly you have to connect this from the
a 0, this your y 0. So, y 1 is basically ground; y 2 is a 0 bar a 1 a 0 bar line is this, a 1 is this,
this is y 2. y 3 is a 0 into a 2 exclusive OR a 1. a 2 line is this, a 1 line is this.

This is exclusive OR, and this you have end with a 0, this is your y 3. And y 4 is a 2 into a 1
bar plus a 0; a 1 bar is this plus a 0 is this, OR operation, and you have to end with a 2. This is
a 2, and y 5 a 2 to a 1. This is the complete design of this one. If you want to verify this,
normally we will in manual mode, we will connect the ICs correspond to all the logic gates
and we will verify.

Whereas, in Verilog code, we want to write Verilog code, module I will give the name as
squarer output is y 0 so on up to y 1, y 2, y 3, y 4, y 5 comma a 2, a 1, a 0 semicolon output y
0 comma y 1 comma y 2 comma y 3 comma y 4 comma y 5 semi colon input a 2 comma a 1
comma a 0 semi colon.

Then how to get output y? y 0 is same as a1. For that, we can write buffer. Buffer because
buffer will give the same output is equal to input. Buffer with output as y 0 input as a 0. And
y 1 is 0, you can directly give assign y 1 is equal to 0, or we can give if want to use a gate,
then you can use something like AND y 1 inputs. If you give any input like a 2 comma a 2
bar if I use 0 say other input.

This you have to you can design in many ways, you can assign directly in case of behavioral
modeling ok. I will discuss that in the coming classes. This is 0, a 2 comma 0. Then y 2 is
nothing but so y 2 if want a 0, first you obtain this a 0 bar, a 1 bar, a 2 bar using three not
gates not. So, we call this one output as a 0 bar, a 0, not a 0 bar sorry a 1 bar, a 1, not a 2 bar a
2.

Then y 2 is AND, and y 2 comma inputs are a 0 bar a 1, a 0 bar we have already obtained ok.
And y 3 is we have to first we have to define the wire here, we have to define wire y 1 w 1.

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So, XOR output is w 1 comma the inputs are a 2 and a 1. Then we have to use AND
operation, AND output is y 3 the inputs are w 1 and then a 0.

Then y 4 first you have to write OR between a 1 bar and a 0 this output you call as y w 2. So,
w 2 comma the inputs are a 1 bar comma a 0, then AND between output is y 4 input is w 2
comma the other input is a 2. AND y 5 is and between a 2 and a 1, output is y 5 a 2 comma a
1 end module. So, this is the complete design using Verilog ok.

So, if you run this program and if you simulate this a 0, a 1, a 2, a 0, this you can give 0 or 1,
this will give 0 or 1 using the simulation tools. And you can observe these outputs y 5 to y 0,
y 5 to y 0, it has to satisfy the truth table that I have written in the previous slide ok. This is
how we can check using this Verilog code ok. This is all about this first design. So, in the
coming classes, we will discuss some more examples of the combinational circuits.

Thank you.

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