UNIT I

80386DX- Basic Programming

Model and Applications
Instruction Set
 What is Microprocessor?
● A microprocessor is an integrated circuit (IC) which incorporates core functions of a
computer’s central processing unit (CPU). It is a programmable multipurpose silicon
chip, clock driven, register based, accepts binary data as input and provides output
after processing it as per the instructions stored in the memory.
 How does a Microprocessor work?
● A processor is the brain of a computer which basically consists of Arithmetical and
Logical Unit (ALU), Control Unit and Register Array. As the name indicates ALU
performs all arithmetic and logical operations on the data received from input devices
or memory. Register array consists of a series of registers like accumulator (A), B, C,
D etc. which acts as temporary fast access memory locations for processing data. As
the name indicates, control unit controls the flow of instructions and data throughout
the system.
● So basically a microprocessor takes input from input devices, process it as per
instructions given in the memory and produces output.
 Common Terms used in a
Microprocessor
● Instruction Set - The group of commands that the microprocessor can understand is
called Instruction set. It is an interface between hardware and software.
● Bus - Set of conductors intended to transmit data, address or control information to
different elements in a microprocessor. A microprocessor will have three types of buses,
i.e., data bus, address bus, and control bus.
● IPC (Instructions Per Cycle) - It is a measure of how many instructions a CPU is
capable of executing in a single clock.
● Clock Speed - It is the number of operations per second the processor can perform. It
can be expressed in megahertz (MHz) or gigahertz (GHz). It is also called the Clock
Rate.
● Bandwidth - The number of bits processed in a single instruction is called Bandwidth.
● Word Length - The number of bits the processor can process at a time is called the
word length of the processor. 8-bit Microprocessor may process 8 -bit data at a time.
The range of word length is from 4 bits to 64 bits depending upon the type of the
microcomputer.
● Data Types - The microprocessor supports multiple data type formats like binary, ASCII,
signed and unsigned numbers.
 Features of Microprocessor
● Low Cost - Due to integrated circuit technology microprocessors are available at very
low cost. It will reduce the cost of a computer system.
● High Speed - Due to the technology involved in it, the microprocessor can work at very
high speed. It can execute millions of instructions per second.
● Small Size - A microprocessor is fabricated in a very less footprint due to very large
scale and ultra large scale integration technology. Because of this, the size of the
computer system is reduced.
● Versatile - The same chip can be used for several applications, therefore,
microprocessors are versatile.
● Low Power Consumption - Microprocessors are using metal oxide semiconductor
technology, which consumes less power.
● Less Heat Generation - Microprocessors uses semiconductor technology which will
not emit much heat as compared to vacuum tube devices.
● Reliable - Since microprocessors use semiconductor technology, therefore, the failure
rate is very less. Hence it is very reliable.
● Portable - Due to the small size and low power consumption microprocessors are
portable.
Microprocessor vs Microcontroller
 Evolution of Microprocessors
4004
● The first microprocessor was introduced in the year 1971. It was introduced by Intel
and was named Intel 4004.
● Intel 4004 is a 4 bit microprocessor and it was not a powerful microprocessor. It can
perform addition and subtraction operation on 4 bits at a time.
 Evolution of Microprocessors...
8008
● The first 8-bit microprocessor, Intel 8008 (i8008) was released 5 months after Intel
4004.
● Intel 8008 was designed using PMOS technology and had a 18 pin design.
● It had a 14 bit external address bus and can support 16 KB of memory.
● The Intel 8008 has 3500 transistors that enabled it to process 30,000 to 160,000
instructions per second.
● The Inte 8008 has also the ability to handle interrupts and it was built using 7 levels of
CPU stack design.
 Evolution of Microprocessors...
8080
● Succeeding the Intel 8008 microprocessor, the Intel 8080 was designed by Masatoshi
Shima and Federico Faggin.
● The Intel 8080 was the second 8-bit microprocessor manufactured by Intel and was
released in 1974.
● The microprocessor was considered an enhanced as well as extended version of the
preceding 8008 microprocessor.
● The Intel 8080 microprocessor was one of the most popular microprocessors ever
produced.
 Evolution of Microprocessors...
8085
● It is an 8-bit microprocessor designed by Intel in 1977 using NMOS technology.
● 8-bit data bus
● 16-bit address bus, which can address upto 64KB
● A 16-bit program counter
● A 16-bit stack pointer
● Six 8-bit registers arranged in pairs: BC, DE, HL
● Requires +5V supply to operate at 3.2 MHZ single phase clock
● It is used in washing machines, microwave ovens, mobile phones, etc
 Evolution of Microprocessors...
8086
● Intel 8086 microprocessor is the enhanced version of Intel 8085 microprocessor. It was
designed by Intel in 1976.
● The 8086 microprocessor is a16-bit, N-channel, HMOS microprocessor. Where the
HMOS is used for "High-speed Metal Oxide Semiconductor".
● Intel 8086 is built on a single semiconductor chip and packaged in a 40-pin IC package.
The type of package is DIP (Dual Inline Package).
● Intel 8086 uses 20 address lines and 16 data- lines. It can directly address up to 220 = 1
Mbyte of memory.
● It consists of a powerful instruction set, which provides operation like division and
multiplication very quickly.
● 8086 is designed to operate in two modes,
i.e., Minimum and Maximum mode.
 Evolution of Microprocessors...
80186
● The Intel 80186 is an improved version of the 8086 microprocessors. 80186 is a 16-
bit microprocessor with 16- bit data bus and 20-bit address bus.
● It has a programmable peripheral devices integrated in the same package. The
instruction set of the 80186 is a superset of the instruction set of the 8086. The term
superset means that all of the 8086 instructions will execute properly on an 80186,
but the 80186 having the few additional instructions. We will see on Instruction set of
80186 under this heading.
 Evolution of Microprocessors...
80286
● 80286 Microprocessor is a 16-bit microprocessor that has the ability to execute 16-bit
instruction at a time. It has non-multiplexed data and address bus.
● The size of data bus is 16-bit whereas the size of address bus is 24-bit.
● It was invented in February 1982 by Intel. 80286 microprocessor was basically an
advancement of 8086 microprocessor. Further in 1985, Intel produced upgraded
version of 80286 which was a 32-bit microprocessor.
 Evolution of Microprocessors...
80386
● 80386 Microprocessor is a 32-bit processor that holds the ability to carry out 32-bit
operation in one cycle. It has data and address bus of 32-bit each. Thus has the
ability to address 4 GB (or 232) of physical memory.
● Multitasking and protection capability are the two key characteristics of 80386
microprocessor. 80386 has an internal dedicated hardware that permits multitasking.
● The 80386 was also released in subsequent
versions including the 386SX, a lower cost
version lacking a math coprocessor. 386SL is
the low-power version intended for mobile
computers.
 Evolution of Microprocessors...
80486
● Intel 80486, also known as i486 or just 486, is the fourth-generation generation Intel
x86 microprocessor.
● The 80486 was capable of over 40 million instructions per second (MIPS) and offered
roughly twice the performance of the 386. It featured an 8K cache for storing recent
instructions. Tighter pipelining allowed for a complete simple instruction per clock
cycle as compared to the two clock cycles required for a 386. An integrated floating
point unit (FPU) gave faster floating point operations than 386 with a 387 math
coprocessor.
 Evolution of Microprocessors...
Pentium
● Pentium, Family of microprocessors developed by Intel Corp. Introduced in 1993 as
the successor to Intel’s 80486 microprocessor, the Pentium contained two processors
on a single chip and about 3.3 million transistors.
● Using a CISC (complex instruction set computer) architecture, its main features were
a 32-bit address bus, a 64-bit data bus, built-in floating-point and memory-
management units, and two 8KB caches. It was available with processor speeds
ranging from 60 megahertz (MHz) to 200 MHz.
● The Pentium quickly became the processor of choice
for personal computers. It was superseded by
ever faster and more powerful processors, the
Pentium Pro (1995), the Pentium II (1997), the
Pentium III (1999), and the Pentium 4 (2000).
Evolution of Microprocessors...
Evolution of Microprocessors...
Evolution of Microprocessors...
 Evolution of Microprocessors...
● A dual-core processor is a CPU with two processors or "execution cores" in the same
integrated circuit. Each processor has its own cache and controller, which enables it
to function as efficiently as a single processor.
Evolution of Microprocessors...
Evolution of Microprocessors...
Evolution of Microprocessors...
Evolution of Microprocessors...
The Processor War
 80386 Microprocessor
Features of 80386
●
As it is a 32-bit microprocessor. Thus has 32-bit ALU.
●
80386 has data bus of 32-bit.
●
It holds address bus of 32 bit.
●
It supports physical memory addressability of 4 GB and virtual memory
addressability of 64 TB.
●
80386 supports variety of operating clock frequency, which are 16 MHz, 20 MHz, 25
MHz and 33 MHz.
●
It offers 3 stage pipeline: fetch, decode and execute. As it supports simultaneous
fetching, decoding and execution inside the system.
● Multitasking and protection capability are the two key characteristics of 80386
microprocessor.
 80386 Microprocessor Versions
● There are two version of 80386 microprocessor, 80386SX and 80386DX. The SX
stands for single execution while the DX stands for double execution.
● 80386SX holds a data bus of 16-bit. While 80386DX has a data bus of 32-bit.
● Whenever we talk about 80386 then it nothing but 80386DX having 32-bit data bus.
But sometimes a system having 8086 microprocessor needs to improve the its
performance as well as protection. And we know that 8086 is a 16-bit microprocessor,
that operates on 2 banks.
● But 80386 in general has a 32-bit data bus that needs 4 banks. So, to access some
of the features of 80386 in a system having 8086 processor, we use 80386SX as
processor having data bus of 16-bit.
● Thus in this case, a system can be upgraded to facilities of 80386 by simply changing
the processor despite changing the overall system. This is reason why we have
80386SX version of the 80386 microprocessor.
● Generally, we consider 80386 as 80386DX, a processor with 32-bit of data bus.
 Operating modes of 80386
The 80386 has three processing modes:
1. Protected Mode.
2. Real-Address Mode.
3. Virtual 8086 Mode.

● Protected mode is the natural 32-bit environment of the 80386

processor. In this mode all instructions and features are available.
● Real-address mode (often called just "real mode") is the mode of the
processor immediately after RESET. In real mode the 80386 appears to
programmers as a fast 8086 with some new instructions. Most
applications of the 80386 will use real mode for initialization only.
● Virtual 8086 mode (also called V86 mode) is a dynamic mode in the
sense that the processor can switch repeatedly and rapidly between V86
mode and protected mode. The CPU enters V86 mode from protected
mode to execute an 8086 program, then leaves V86 mode and enters
protected mode to continue executing a native 80386 program.
Architecture of 80386
Microprocessor
Architecture of 80386
Microprocessor
Architecture of 80386
Microprocessor
 Architecture of 80386
Microprocessor
Basically it has 6 functional units which are as follows:
● Bus Interface Unit
● Code Fetch Unit
● Instruction Decode Unit
● Execution Unit
● Memory Management Unit
As we have already discussed that the 80386 possess the ability of 3 stage
pipelining thus performs fetching, decoding and execution simultaneously
along with memory management and bus accessing. Thus all these units
operate parallely.
 Architecture of 80386
Microprocessor
1. Bus Interface Unit
● The bus interface unit or BIU holds a 32-bit bidirectional data bus as well as
32-bit address bus. Whenever a need for an instruction or a data fetch is
generated by the system then the BIU generates signals (according to the
priority) for activating the data and address bus in order to fetch the data
from the desired address.
● The BIU connects the peripheral devices through the memory unit and also
controls the interfacing of external buses with the coprocessors.
 Architecture of 80386
Microprocessor
2. Code Prefetch Unit
● This unit fetches the instructions stored in the memory by making use of system buses.
Whenever the system generates a need for an instruction then the code prefetch unit
fetches that instruction from the memory and stores it in 16-byte prefetch queue.
● So to speed up the operation this unit fetches the instructions in advance and the queue
stores these instructions.
● The sequence in which the instructions are fetched and gets stored in the queue depends
on the order they exist in the memory.
● As this unit fetches one double word in single access. So, in such a case, it is not
necessary that each time only a single instruction will be fetched, as the fetched instruction
can be parts of two different instructions.
● It is to be noted here that, code prefetching holds lower priority than data transferring. As
whenever, a need for data transfer is generated by the system then immediately the code
prefetcher leaves the control over the buses. So that the BIU can transfer the required data.
● But prefetching of instruction and storing it in the queue reduces the wait for the upcoming
instruction to almost zero.
 Architecture of 80386
Microprocessor
3. Instruction Decode Unit
● We know that instructions in the memory are stored in the form of bits.
So, this unit decodes the instructions stored in the prefetch queue.
Basically the decoder changes the machine language code into assembly
language and transfers it to the processor for further execution.

4. Execution Unit
● The decoded instructions are stored in the decoded instruction queue.
So, these instructions are provided to the execution unit in order to
execute the instructions.
● The execution unit controls the execution of the decoded instructions.
This unit has a 32-bit ALU, that performs the operation over 32-bit data in
one cycle. Also, it consists of 8 general purpose as well as 8 special
purpose registers. These are used for data handling and calculation of
offset address.
 Architecture of 80386
Microprocessor
5. Memory Management Unit
● This unit has two separate units within it. These are
Segmentation Unit
Paging Unit
● Segmentation unit: The segmentation unit plays a vital role in the 80836
microprocessor. It offers protection mechanism in order to protect the code or data
present in the memory from application programs.
● It gives 4 level protection to the data or code present in the memory. Every information
in the memory is assigned a privilege level from PL0 to PL3. Here, PL0 holds the
highest priority and PL3 holds the lowest priority.Suppose a file (either data or code) is
needed to be accessed is stored in the memory at PL0. Then only those programs
which are working at PL0 would be able to access that file. While other programs will
not be able to access the same.
● Also, if a file is present at PL1, then programs of PL0 and PL1 both can access it. As
PL0 has higher priority than PL1. So, for protection purpose the main part of OS is
stored in PL0 while PL3 holds the user programs.
 Architecture of 80386
Microprocessor

● Providing protection to the data or code inside the system is the most advantageous
factor that was first given by 80386 microprocessor.
 Architecture of 80386
Microprocessor
● Paging Unit: The paging unit operates only in protected mode and it changes
the linear address into physical address. As the programmer only provides the
virtual address and not the physical address.
● The segmentation unit controls the action of paging unit, as the segmentation
unit has the ability to convert logical address into linear address at the time of
executing an instruction.
● Basically it changes the overall task map into pages and each page has a size
of 4K. This allows the handling of task in the form of pages rather than
segments.
● Paging unit supports multitasking. This is so because the physical memory is
not required to hold the whole segment of any task. Despite, only that part of
the segment which is needed to be currently executed must be stored in that
memory whose physical address is calculated by the paging unit.
● This resultantly reduces the memory requirement and hence this frees the
memory for other tasks. Thus by this we get an effective way for managing the
memory to support multitasking.
Basic Programming Model x386
The basic programming model consists of these aspects:
● Memory organization and segmentation
● Data types
● Registers
● Instruction format
● Operand selection
● Interrupts and exceptions
Memory organization and segmentation
● Physical memory organized as sequence of 8-bit bytes
● Each byte is assigned unique address (range 0 to 232 – 1)
● Physical address space : 4 GB (physical memory)
● Logical address space : 64 TB (Virtual memory)
Memory organization and segmentation
● x386 programs independent of physical address space
● Programmer not known the physical memory addresses
● Also, no clue exact location of data n code in memory
● The architecture of the 80386 gives designers the freedom to choose a
model for each task.
● The model of memory organization can range between the following :
- A "flat" address space consisting of a single array of up to 4
gigabytes.
- A segmented address space consisting of a collection of up to 16,383
linear address spaces of up to 4 gigabytes each.
 The "Flat" Model
● The applications programmer sees a single array of up to 2 32
bytes (4 gigabytes)
● The processor maps the 4 gigabyte flat space onto the physical
address space by the address translation mechanisms
 The "Flat" Model
● Applications programmers do not need to know the details of the
mapping.
● A pointer into this flat address space is a 32-bit ordinal number
that may range from 0 to 232-1.
● Relocation of separately-compiled modules in this space must be
performed by systems software (e.g., linkers, locators, binders,
loaders).
 The Segmented Model
● The address space as viewed by an applications program (called the logical
address space) is a much larger space of up to 246 bytes (64 terabytes).
 The Segmented Model...
● The processor maps the 64 terabyte logical address space onto the
physical address space (up to 4 gigabytes) by the address translation
mechanisms.
● Applications programmers do not need to know the details of this
mapping.
● Applications programmers view the logical address space of the 80386
as a collection of up to 16,383 one-dimensional subspaces, each with a
specified length.
● Each of these linear subspaces is called a segment.
● A segment is a unit of contiguous address space.
● Segment sizes may range from one byte up to a maximum of 2 32 bytes (4
gigabytes).
 The Segmented Model...
● A complete pointer in logical address space consists of two parts
● A segment selector, which is a 16-bit field that identifies a segment.
● An offset, which is a 32-bit ordinal that addresses to the byte level
within a segment.
● During execution of a program, the processor associates with a
segment selector the physical address of the beginning of the segment.
● Separately compiled modules can be relocated at run time by
changing the base address of their segments.
● The size of a segment is variable; therefore, a segment can be exactly
the size of the module it contains.
Two Component Pointer
 Data Types of 80386
Microprocessor
● The 80386 supports the following data types they are,
1. Bit
2. Bit Field: A group of at the most 32 bits (4bytes)
3. Bit String: A string of contiguous bits of maximum 4Gbytes in
length.
 Data Types of 80386
Microprocessor...
4. Signed Byte: Signed byte data
5. Unsigned Byte: Unsigned byte data.
6. Integer word: Signed 16-bit data.
7. Long Integer: 32-bit signed data represented in 2’s complement form.
8. Unsigned Integer Word: Unsigned 16-bit data
9. Unsigned Long Integer: Unsigned 32-bit data
10. Signed Quad Word: A signed 64-bit data or four word data.
11. Unsigned Quad Word: An unsigned 64-bit data.
 Data Types of 80386
Microprocessor...
12. Offset: 16/32-bit displacement that points a memory location using any of the
addressing modes.
13. Pointer: This consists of a pair of 16-bit selector and 16/32-bit offset.
14. Character: An ASCII equivalent to any of the alphanumeric or control
characters.
15. Strings: These are the sequences of bytes, words or double words. A string may
contain minimum one byte and maximum 4 Gigabytes.
16. BCD: Decimal digits from 0-9 represented by unpacked bytes.
17. Packed BCD: This represents two packed BCD digits using a byte, i.e. from 00
to 99.
Data Types of 80386
Microprocessor
Data Types of 80386
Microprocessor
 Data Types of 80386
Microprocessor
Packed BCD:
A byte (packed) representation of two decimal digits, each in the range 0 through
9. One digit is stored in each half-byte. The digit in the high-order half-byte is
the most significant. Values 0-9 are valid in each half-byte. The range of a
packed decimal byte is 0-99.
Bytes, Words, and Doublewords in
Memory
 Registers
● The 80386 contains a total of sixteen registers that are of interest to
the applications programmer.
1. General registers. These eight 32-bit general-purpose registers are
used primarily to contain operands for arithmetic and logical
operations.
2. Segment registers. These special-purpose registers permit systems
software designers to choose either a flat or segmented model of
memory organization. These six registers determine, at any given
time, which segments of memory are currently addressable.
3. Status and instruction registers. These special-purpose registers
are used to record and alter certain aspects of the 80386 processor
state.
Registers
 1. General Registers
● The general registers of the 80386 are the 32-bit registers EAX, EBX, ECX, EDX,
EBP, ESP, ESI, and EDI. These registers are used interchangeably to contain the
operands of logical and arithmetic operations. They may also be used
interchangeably for operands of address computations (except that ESP cannot be
used as an index operand).
● The low-order word of each of these eight registers has a separate name and can
be treated as a unit. This feature is useful for handling 16-bit data items and for
compatibility with the 8086 and 80286 processors. The word registers are named
AX, BX, CX, DX, BP, SP, SI, and DI.
● Byte of the 16-bit registers AX, BX, CX, and DX has a separate name and can be
treated as a unit. This feature is useful for handling characters and other 8-bit data
items. The byte registers are named AH, BH, CH, and DH (high bytes); and AL, BL,
CL, and DL (low bytes).
● All of the general-purpose registers are available for addressing calculations and for
the results of most arithmetic and logical calculations; however, a few functions are
dedicated to certain registers. By implicitly choosing registers for these functions,
the 80386 architecture can encode instructions more compactly. The instructions
that use specific registers include: double-precision multiply and divide, I/O, string
instructions, translate, loop, variable shift and rotate, and stack operations.
 2. Segment Registers
● The segment registers of the 80386 give systems software designers the flexibility to
choose among various models of memory organization. Designers may choose a
model in which applications programs do not need to modify segment registers, in
which case applications programmers may skip this section.
● Complete programs generally consist of many different modules, each consisting of
instructions and data. However, at any given time during program execution, only a
small subset of a program's modules are actually in use. The 80386 architecture
takes advantage of this by providing mechanisms to support direct access to the
instructions and data of the current module's environment, with access to additional
segments on demand.
● At any given instant, six segments of memory may be immediately accessible to an
executing 80386 program. The segment registers CS, DS, SS, ES, FS, and GS are
used to identify these six current segments. Each of these registers specifies a
particular kind of segment, as characterized by the associated mnemonics ("code,"
"data," or "stack") shown in Figure 2-6 . Each register uniquely determines one
particular segment, from among the segments that make up the program, that is to
be immediately accessible at highest speed.
● The segment containing the currently executing sequence of instructions is known as
the current code segment; it is specified by means of the CS register. The 80386
fetches all instructions from this code segment, using as an offset the contents of the
instruction pointer. CS is changed implicitly as the result of intersegment control-
transfer instructions (for example, CALL and JMP), interrupts, and exceptions.
 2. Segment Registers...
● Subroutine calls, parameters, and procedure activation records usually require that a region
of memory be allocated for a stack. All stack operations use the SS register to locate the
stack. Unlike CS, the SS register can be loaded explicitly, thereby permitting programmers
to define stacks dynamically.
● The DS, ES, FS, and GS registers allow the specification of four data segments, each
addressable by the currently executing program. Accessibility to four separate data areas
helps programs efficiently access different types of data structures; for example, one data
segment register can point to the data structures of the current module, another to the
exported data of a higher-level module, another to a dynamically created data structure,
and another to data shared with another task. An operand within a data segment is
addressed by specifying its offset either directly in an instruction or indirectly via general
registers.
● Depending on the structure of data (e.g., the way data is parceled into one or more
segments), a program may require access to more than four data segments. To access
additional segments, the DS, ES, FS, and GS registers can be changed under program
control during the course of a program's execution. This simply requires that the program
execute an instruction to load the appropriate segment register prior to executing
instructions that access the data.
● The processor associates a base address with each segment selected by a segment
register. To address an element within a segment, a 32-bit offset is added to the segment's
base address. Once a segment is selected (by loading the segment selector into a segment
register), a data manipulation instruction only needs to specify the offset. Simple rules
define which segment register is used to form an address when only an offset is specified.
Use of Memory Segmentation
 Stack Implementation
● Stack operations are facilitated by three registers:
The stack segment (SS) register. Stacks are implemented in memory. A
system may have a number of stacks that is limited only by the maximum
number of segments. A stack may be up to 4 gigabytes long, the maximum
length of a segment. One stack is directly addressable at one located by SS.
This is the current stack, often referred to simply as "the" stack. SS is used
automatically by the processor for all stack operations.
 Stack Implementation...
● The stack pointer (ESP) register. ESP points to the top of the push-down
stack (TOS). It is referenced implicitly by PUSH and POP operations,
subroutine calls and returns, and interrupt operations. When an item is
pushed onto the stack, the processor decrements ESP, then writes the item
at the new TOS. When an item is popped off the stack, the processor copies
it from TOS, then increments ESP. In other words, the stack grows down in
memory toward lesser addresses.
● The stack-frame base pointer (EBP) register. The EBP is the best choice of
register for accessing data structures, variables and dynamically allocated
work space within the stack. EBP is often used to access elements on the
stack relative to a fixed point on the stack rather than relative to the current
TOS. It typically identifies the base address of the current stack frame
established for the current procedure. When EBP is used as the base
register in an offset calculation, the offset is calculated automatically in the
current stack segment (i.e., the segment currently selected by SS). Because
SS does not have to be explicitly specified, instruction encoding in such
cases is more efficient. EBP can also be used to index into segments
addressable via other segment registers.
 Flags Register
● The flags register is a 32-bit register named EFLAGS. Figure 2-8 defines the bits
within this register. The flags control certain operations and indicate the status of the
80386.
● The low-order 16 bits of EFLAGS is named FLAGS and can be treated as a unit. This
feature is useful when executing 8086 and 80286 code, because this part of EFLAGS
is identical to the FLAGS register of the 8086 and the 80286.
● The flags may be considered in three groups: the status flags, the control flags, and
the systems flags.
 Flags Register...
1. Status Flags
There are 6 flag registers in 8086 microprocessor which become set(1) or reset(0) depending
upon condition after either 8-bit or 16-bit operation. These flags are conditional/status flags. 5
of these flags are same as in case of 8085 microprocessor and their working is also same as
in 8085 microprocessor. The sixth one is the overflow flag.
The 6 status flags are:
1. Sign Flag (S)
2. Zero Flag (Z)
3. Auxiliary Cary Flag (AC)
4. Parity Flag (P)
5. Carry Flag (CY)
These first five flags are defined here
6. Overflow Flag (O) – This flag will be set (1) if the result of a signed operation is too large
to fit in the number of bits available to represent it, otherwise reset (0). After any operation, if
D[6] generates any carry and passes to D[7] OR if D[6] does not generates carry but D[7]
generates, overflow flag becomes set, i.e., 1. If D[6] and D[7] both generate carry or both do
not generate any carry, then overflow flag becomes reset, i.e., 0.
Example: On adding bytes 100 + 50 (result is not in range -128…127), so overflow flag will
set.
 Flags Register...
2. Control Flag
Control Flags – The control flags enable or disable certain operations of the microprocessor.
There are 3 control flags in 8086 microprocessor and these are:
i. Directional Flag (D) – This flag is specifically used in string instructions.
If directional flag is set (1), then access the string data from higher memory location towards lower
memory location.
If directional flag is reset (0), then access the string data from lower memory location towards
higher memory location.
ii. Interrupt Flag (I) – This flag is for interrupts.
If interrupt flag is set (1), the microprocessor will recognize interrupt requests from the peripherals.
If interrupt flag is reset (0), the microprocessor will not recognize any interrupt requests and will
ignore them.
Iii. Trap Flag (T) – This flag is used for on-chip debugging. Setting trap flag puts the
microprocessor into single step mode for debugging. In single stepping, the microprocessor
executes a instruction and enters into single step ISR.
If trap flag is set (1), the CPU automatically generates an internal interrupt after each instruction,
allowing a program to be inspected as it executes instruction by instruction.
If trap flag is reset (0), no function is performed.

.
 Instruction Pointer
● The instruction pointer register (EIP) contains the offset address, relative to
the start of the current code segment, of the next sequential instruction to be
executed. The instruction pointer is not directly visible to the programmer; it
is controlled implicitly by control-transfer instructions, interrupts, and
exceptions.
● The low-order 16 bits of EIP is named IP and can be used by the processor
as a unit. This feature is useful when executing instructions designed for the
8086 and 80286 processors.
 Instruction Format
● 80386 instruction contains :
a specification of the operation to be performed,
the type of the operands to be manipulated, and
the location of these operands in encoded format
● If an operand is located in memory, the instruction must also select, explicitly
or implicitly, which of the currently addressable segments contains the
operand.
● 80386 instructions are composed of various elements and have various formats.
● Of instruction elements, only one, the opcode, is always present.
● The other elements may or may not be present, depending on the particular
operation involved and on the location and type of the operands.
 Instruction Format...
● 80386 instructions are composed of various elements and have various formats.
The elements of an instruction, in order of occurrence are as follows:
1. Prefixes -- one or more bytes preceding an instruction that modify the operation
of the instruction.
The following types of prefixes can be used by applications programs:
-> Segment override -- explicitly specifies which segment register an instruction should use,thereby

overriding the default segment-register selection used by the 80386 for that instruction.

-> Address size -- switches between 32-bit and 16-bit address generation.

-> Operand size -- switches between 32-bit and 16-bit operands.

-> Repeat -- used with a string instruction to cause the instruction to act on each element of the string.

2. Opcode -- specifies the operation performed by the instruction. Some operations

have several different opcodes, each specifying a different variant of the operation.
3. Register specifier -- an instruction may specify one or two register operands.
Register specifiers may occur either in the same byte as the opcode or in the same
byte as the addressing mode specifier.
 Instruction Format...
5. Addressing-mode specifier -- when present, specifies whether an operand is a
register or memory location; if in memory, specifies whether a displacement, a base
register, an index register, and scaling are to be used.
5. SIB (scale, index, base) byte -- when the addressing-mode specifier indicates that
an index register will be used to compute the address of an operand, an SIB byte is
included in the instruction to encode the base register, the index register, and a scaling
factor.
6. Displacement -- when the addressing-mode specifier indicates that a displacement
will be used to compute the address of an operand, the displacement is encoded in the
instruction. A displacement is a signed integer of 32, 16, or eight bits. The eight-bit form
is used in the common case when the displacement is sufficiently small. The processor
extends an eight-bit displacement to 16 or 32 bits, taking into account the sign.
7. Immediate operand -- when present, directly provides the value of an operand of
the instruction. Immediate operands may be 8, 16, or 32 bits wide. In cases where an
eight-bit immediate operand is combined in some way with a 16- or 32-bit operand, the
processor automatically extends the size of the eight-bit operand, taking into account
the sign.
 Operand Selection
An instruction can act on zero or more operands, which are the data
manipulated by the instruction. An operand can be in any of these locations:
● In the instruction itself (an immediate operand)
● In a register (EAX, EBX, ECX, EDX, ESI, EDI, ESP, or EBP in the case of 32-bit
operands; AX, BX, CX, DX, SI, DI, SP, or BP in the case of 16-bit operands; AH,
AL, BH, BL, CH, CL, DH, or DL in the case of 8-bit operands; the segment
registers; or the EFLAGS register for flag operations)
● In memory
● At an I/O port
Immediate operands and operands in registers can be accessed more rapidly
than operands in memory since memory operands must be fetched from
memory. Register operands are available in the CPU. Immediate operands are
also available in the CPU, because they are prefetched as part of the instruction.
 Operand Selection...
Most of the instructions that have operands, some specify operands implicitly;
others specify operands explicitly; still others use a combination of implicit and
explicit specification; for example:
● Implicit operand: AAM
By definition, AAM (ASCII adjust for multiplication) operates on the contents of
the AX register.
● Explicit operand: XCHG EAX, EBX
The operands to be exchanged are encoded in the instruction after the opcode.
● Implicit and explicit operands: PUSH COUNTER
The memory variable COUNTER (the explicit operand) is copied to the top of
the stack (the implicit operand).
Note that most instructions have implicit operands. All arithmetic instructions,
for example, update the EFLAGS register.
 Operand Selection...
An 80386 instruction can explicitly reference one or two operands. Two-operand
instructions, such as MOV ADD, XOR, etc., generally overwrite one of the two
participating operands with the result. A distinction can thus be made between the
source operand (the one unaffected by the operation) and the destination operand (the
one overwritten by the result).
For most instructions, one of the two explicitly specified -- the source or the -- be either
in a register or in memory. The other operand must be in a register or be an immediate
source operand. Thus, the explicit two-operand instructions of the 80386 permit
operations of the following kinds:
● Register-to-register
● Register-to-memory
● Memory-to-register
● Immediate-to-register
● Immediate-to-memory
Certain string instructions and stack manipulation instructions, however, transfer data
from memory to memory. Both operands of some string instructions are in memory and
are implicitly specified. Push and pop stack operations allow transfer between memory
operands and the memory-based stack.
Default Segment Register Selection Rules

Memory Segment Implicit Segment Selection Rule

Reference Register
Needed Used
Instructions Code (CS) Automatic with instruction prefetch

Stack Stack (SS) All stack pushes and pops. Any memory
reference that uses ESP or EBP as a base
register.
Local Data Data (DS) All data references except when relative to
stack or string destination.
Destination Extra (ES) Destination of string instructions.
Strings
 Effective-Address Computation
● The modR/M byte provides the most flexible of the addressing methods
● instructions that require a modR/M byte as the second byte of the instruction are the
most common in the 80386 instruction set.
● For memory operands defined by modR/M, the offset within the desired segment is
calculated by taking the sum of up to three components:
✔ A displacement element in the instruction.
✔ A base register.
✔ An index register.
✔ The index register may be automatically multiplied by a scaling factor of 2, 4, or
8.
● The offset that results from adding these components is called an effective address.
● Each of these components of an effective address may have either a positive or
negative value.
● If the sum of all the components exceeds 2 32, the effective address is truncated to 32
bits.
Effective-Address Computation...
 Addressing Modes
● Register Addressing Mode
● Immediate Addressing Mode
● Memory Addressing Mode
1. Direct Addressing Mode
2. Register Indirect Addressing Mode
3. Based Mode
4. Index Mode
5. Scaled Index Mode
6. Based Index Mode
7. Based Scaled Index Mode
8. Based Index Mode with Displacement
9. Based Scaled Index Mode with Displacement
● String Addressing Mode
● Implied Addressing Mode
 Addressing Modes...
● Register Addressing Mode
✔ Data is in the registers and the instruction specifies the particular registers.
✔ It is normally preferred because the instruction are compact and fastest
executing of all instruction forms.
✔ Registers may be used as source operands, destination operands or both.
e.g. MOV EAX, EDX
 Addressing Modes...
● Immediate Addressing Mode
✔ Immediate operand is nothing but constant data contained in an instruction.
✔ Sourse operand is a part of the instruction instead of register or memory.
✔ Data may be 8, 16 or 32 bits in length.
✔ Immediate operands only serve as source operands.
E.g. MOV ECX, 70304060H
 Addressing Modes...
● Memory Addressing Mode
1. Direct Addressing Mode
Here EA is taken from the displacement field of the instruction.
EA is used as 8,16 or 32 bit displacement from the current value of the data
segment register

E.g. MOV AX, [1875 H]

 Addressing Modes...
● Memory Addressing Mode
2. Register Indirect Addressing Mode
Here, base or index register contains the operands effective
address.
E.g. MOV EBX, [ECX]
3. Based Mode
In this mode the contents of a base register are added to
displacement, in order to obtain the operand's EA.
E.g. MOV ESI, [EAX+25H]
 Addressing Modes...
● Memory Addressing Mode
4. Index Mode
Here, index register contains are added to a displacement to obtain
the operand's effective address.
ESP cannot act as index pointer

E.g. MOV EAX, [ESI +05]

5. Scaled Index Mode
In this mode the contents of an index register are multiplied by
a scling factor of (1,2,4 or 8) which is then added to the
displacement, in order to obtain the operand's EA.
E.g. MOV [ESI*2], ECX
 Addressing Modes...
● Memory Addressing Mode
6. Based Indexed Mode
Here, base register are added to the contents of an index
register to compute operand's effective address.
E.g. MOV ESI, [ECX] [EBX]
7. Based Scaled Index Mode
In this mode the contents of an index register are
multiplied by a scling factor and the result is added to base
register to compute the operand's EA.
E.g. MOV ECX, [EDI*4] [ESP]
 Addressing Modes...
● Memory Addressing Mode
8. Based Indexed Mode with Displacement
Here, operands effective address is computed by adding the
contents of base register and index register with a displacement.
E.g. MOV [EBX] [EBP + 12345678H], EDI
9. Based Scaled Index Mode with Displacement
In this mode, the operands effective address is computed by
multiplying the index register with a scaling factor and result
is added to base register and also a displacement is added.
E.g. MOV [EBX*8] [ECX + 5794 H] , ECX
 Addressing Modes...
● String Addressing Mode
For accessing the operands the String instructions do not use
the commonly used memory addressing modes.
For string instruction, SI will point to the first byte or word of the
source string with DS as the segment register and DI ponits to
the first byte or word of the destination string with ES as the
segment register.
The automatic adjustment is done with the help of DF in flag
register, and achieved by MOD and R/M bits in instruction
format.
 Addressing Modes...
● Implied Addressing Mode
The instructions which do not have operands come under
implied addressing mode.

E.g. XLAT
 Interrupts and Exceptions
● The 80386 has two mechanisms for iterrupting program execution
1. Exceptions are synchronous events that are the responses of the CPU to
certain conditions detected during the execution of an instruction.
2. Interrupts are asynchronous events typically triggered by external
devices needing attention.
● Interrupts and exceptions are alike in that both cause the processor to
temporarily suspend its present program execution in order to execute a
program of higher priority.
● An exception is always reproducible by re-executing with the program and
data that caused the exception, whereas an interrupt is generally
independent of the currently executing program.
 Interrupts and Exceptions
● A divide error exception results when the instruction DIV or IDIV is executed with a
zero denominator or when the quotient is too large for the destination operand.
(Refer to Chapter 3 for a discussion of DIV and IDIV.)
● The debug exception may be reflected back to an applications program if it results
from the trap flag (TF).
● A breakpoint exception results when the instruction INT 3 is executed. This
instruction is used by some debuggers to stop program execution at specific points.
● An overflow exception results when the INTO instruction is executed and the OF
(overflow) flag is set (after an arithmetic operation that set the OF flag). (Refer to
Chapter 3 for a discussion of INTO).
● A bounds check exception results when the BOUND instruction is executed and the
array index it checks falls outside the bounds of the array. (Refer to Chapter 3 for a
discussion of the BOUND instruction.)
● Invalid opcodes may be used by some applications to extend the instruction set. In
such a case, the invalid opcode exception presents an opportunity to emulate the
opcode.
● The "coprocessor not available" exception occurs if the program contains instructions
for a coprocessor, but no coprocessor is present in the system.
● A coprocessor error is generated when a coprocessor detects an illegal operation.
Interrupts and Exceptions...
 Applications
Instruction Set
 Instruction set of 80386
● Data Movement Instructions
● Binary Arithmetic Instructions
● Decimal Arithmetic Instructions
● Logical Instructions
● Control Transfer Instructions
● String and Character Translation Instructions
● Instructions for Block-Structured Languages
● Flag Control Instructions
● Coprocessor Interface Instructions
● Segment Register Instructions
● Miscellaneous Instructions
 Data Movement Instructions
● These instructions provide convenient methods for moving bytes, words, or
doublewords of data between memory and the registers of the base
architecture. They fall into the following classes:
- General-purpose data movement instructions.
- Stack manipulation instructions.
- Type-conversion instructions.
 MOV
MOV (Move) transfers a byte, word, or doubleword from the source operand
to the destination operand. The MOV instruction is useful for transferring
data along any of these paths There are also variants of MOV that operate
on segment registers. These are covered in a later section of this chapter:
● To a register from memory
● To memory from a register
● Between general registers
● Immediate data to a register
● Immediate data to a memory
The MOV instruction cannot move from memory to memory or from segment
register to segment register are not allowed. Memory-to-memory moves can
be performed, however, by the string move instruction MOVS.
 XCHG
● XCHG (Exchange) swaps the contents of two operands. This
instruction takes the place of three MOV instructions.
● It does not require a temporary location to save the contents of one
operand while load the other is being loaded.
● XCHG is especially useful for implementing semaphores or similar
data structures for process synchronization.
● The XCHG instruction can swap two byte operands, two word
operands, or two doubleword operands.
● The operands for the XCHG instruction may be two register
operands, or a register operand with a memory operand.
● When used with a memory operand, XCHG automatically activates
the LOCK signal.
 Stack Manipulation Instructions
● PUSH (Push) decrements the stack pointer (ESP), then transfers the source
operand to the top of stack indicated by ESP (see Figure 3-1). PUSH is often
used to place parameters on the stack before calling a procedure; it is also
the basic means of storing temporary variables on the stack. The PUSH
instruction operates on memory operands, immediate operands, and register
operands (including segment registers).
 PUSHA
● PUSHA (Push All Registers) saves the contents of the eight general registers on the
stack (see Figure 3-2). This instruction simplifies procedure calls by reducing the
number of instructions required to retain the contents of the general registers for use
in a procedure. The processor pushes the general registers on the stack in the
following order: EAX, ECX, EDX, EBX, the initial value of ESP before EAX was
pushed, EBP, ESI, and EDI. PUSHA is complemented by the POPA instruction.
 POP
● POP (Pop) transfers the word or doubleword at the current top of stack
(indicated by ESP) to the destination operand, and then increments ESP to
point to the new top of stack. See Figure 3-3. POP moves information from
the stack to a general register, or to memory There are also a variant of POP
that operates on segment registers. This is covered in a later section of this
chapter.
 POPA
● POPA (Pop All Registers) restores the registers saved on the stack by
PUSHA, except that it ignores the saved value of ESP.
 Type Conversion Instructions
● The type conversion instructions convert bytes into words, words into doublewords,
and doublewords into 64-bit items (quad-words). These instructions are especially
useful for converting signed integers, because they automatically fill the extra bits of
the larger item with the value of the sign bit of the smaller item. This kind of
conversion, illustrated by Figure 3-5, is called sign extension.

● There are two classes of type conversion instructions:

● The forms CWD, CDQ, CBW, and CWDE which operate only on data in the EAX
register.
● The forms MOVSX and MOVZX, which permit one operand to be in any general
register while permitting the other operand to be in memory or in a register.
 Type Conversion Instructions...
● CWD (Convert Word to Doubleword) and CDQ (Convert Doubleword to
Quad-Word) double the size of the source operand. CWD extends the sign
of the word in register AX throughout register DX. CDQ extends the sign of
the doubleword in EAX throughout EDX. CWD can be used to produce a
doubleword dividend from a word before a word division, and CDQ can be
used to produce a quad-word dividend from a doubleword before
doubleword division.
● CBW (Convert Byte to Word) extends the sign of the byte in register AL
throughout AX.
● CWDE (Convert Word to Doubleword Extended) extends the sign of the
word in register AX throughout EAX.
● MOVSX (Move with Sign Extension) sign-extends an 8-bit value to a 16-bit
value and a 8- or 16-bit value to 32-bit value.
● MOVZX (Move with Zero Extension) extends an 8-bit value to a 16-bit value
and an 8- or 16-bit value to 32-bit value by inserting high-order zeros.
 Binary Arithmetic Instructions
● The arithmetic instructions of the 80386 processor simplify the
manipulation of numeric data that is encoded in binary.
● Operations include the standard add, subtract, multiply, and divide as
well as increment, decrement, compare, and change sign.
● Both signed and unsigned binary integers are supported. The binary
arithmetic instructions may also be used as one step in the process of
performing arithmetic on decimal integers.
● Many of the arithmetic instructions operate on both signed and
unsigned integers. These instructions update the flags ZF, CF, SF, and
OF in such a manner that subsequent instructions can interpret the
results of the arithmetic as either signed or unsigned.
● CF contains information relevant to unsigned integers; SF and OF
contain information relevant to signed integers.
● ZF is relevant to both signed and unsigned integers; ZF is set when all
bits of the result are zero.
 Binary Arithmetic Instructions...
● If the integer is unsigned, CF may be tested after one of these arithmetic
operations to determine whether the operation required a carry or borrow of
a one-bit in the high-order position of the destination operand. CF is set if a
one-bit was carried out of the high-order position (addition instructions ADD,
ADC, AAA, and DAA) or if a one-bit was carried (i.e. borrowed) into the high-
order bit (subtraction instructions SUB, SBB, AAS, DAS, CMP, and NEG).
● If the integer is signed, both SF and OF should be tested. SF always has
the same value as the sign bit of the result. The most significant bit (MSB) of
a signed integer is the bit next to the bit 6 of a byte, bit 14 of a word, or bit 30
of a doubleword.
● OF is set in either of these cases:
1. A one-bit was carried out of the MSB into the sign bit but no one bit was
carried out of the sign bit (addition instructions ADD, ADC, INC, AAA, and
DAA). In other words, the result was greater than the greatest positive
number that could be contained in the destination operand.
 Binary Arithmetic Instructions...
2. A one-bit was carried from the sign bit into the MSB but no one bit was
carried into the sign bit (subtraction instructions SUB, SBB, DEC, AAS, DAS,
CMP, and NEG). In other words, the result was smaller that the smallest
negative number that could be contained in the destination operand.
● These status flags are tested by executing one of the two families of
conditional instructions: Jcc (jump on condition cc) or SETcc (byte set on
condition).
 Addition and Subtraction Instructions
● ADD (Add Integers) replaces the destination operand with the sum of the source and
destination operands. Sets CF if overflow.
● ADC (Add Integers with Carry) sums the operands, adds one if CF is set, and
replaces the destination operand with the result. If CF is cleared, ADC performs the
same operation as the ADD instruction. An ADD followed by multiple ADC
instructions can be used to add numbers longer than 32 bits.
● INC (Increment) adds one to the destination operand. INC does not affect CF. Use
ADD with an immediate value of 1 if an increment that updates carry (CF) is needed.
● SUB (Subtract Integers) subtracts the source operand from the destination operand
and replaces the destination operand with the result. If a borrow is required, the CF is
set. The operands may be signed or unsigned bytes, words, or doublewords.
● SBB (Subtract Integers with Borrow) subtracts the source operand from the
destination operand, subtracts 1 if CF is set, and returns the result to the destination
operand. If CF is cleared, SBB performs the same operation as SUB. SUB followed
by multiple SBB instructions may be used to subtract numbers longer than 32 bits. If
CF is cleared, SBB performs the same operation as SUB.
● DEC (Decrement) subtracts 1 from the destination operand. DEC does not update
CF. Use SUB with an immediate value of 1 to perform a decrement that affects carry.
 Comparison and Sign Change
Instruction
● CMP (Compare) subtracts the source operand from the destination
operand. It updates OF, SF, ZF, AF, PF, and CF but does not alter the
source and destination operands. A subsequent Jcc or SETcc
instruction can test the appropriate flags.
● NEG (Negate) subtracts a signed integer operand from zero. The
effect of NEG is to reverse the sign of the operand from positive to
negative or from negative to positive.
 Multiplication Instructions
● The 80386 has separate multiply instructions for unsigned and signed
operands. MUL operates on unsigned numbers, while IMUL operates
on signed integers as well as unsigned.
● MUL (Unsigned Integer Multiply) performs an unsigned multiplication
of the source operand and the accumulator. If the source is a byte,
the processor multiplies it by the contents of AL and returns the
double-length result to AH and AL. If the source operand is a word,
the processor multiplies it by the contents of AX and returns the
double-length result to DX and AX. If the source operand is a
doubleword, the processor multiplies it by the contents of EAX and
returns the 64-bit result in EDX and EAX. MUL sets CF and OF when
the upper half of the result is nonzero; otherwise, they are cleared.
 Multiplication Instructions...
● IMUL (Signed Integer Multiply) performs a signed multiplication operation.
IMUL has three variations:
1. A one-operand form. The operand may be a byte, word, or doubleword
located in memory or in a general register. This instruction uses EAX and
EDX as implicit operands in the same way as the MUL instruction.
2. A two-operand form. One of the source operands may be in any general
register while the other may be either in memory or in a general register. The
product replaces the general-register operand.
3. A three-operand form. two are source and one is the destination operand.
One of the source operands is an immediate value stored in the instruction;
the second may be in memory or in any general register. The product may
be stored in any general register. The immediate operand is treated as
signed. If the immediate operand is a byte, the processor automatically sign-
extends it to the size of the second operand before performing the
multiplication.
 Multiplication Instructions...
● The three forms are similar in most respects:
● The length of the product is calculated to twice the length of the operands.
● The CF and OF flags are set when significant bits are carried into the high-
order half of the result. CF and OF are cleared when the high-order half of
the result is the sign-extension of the low-order half.
● However, forms 2 and 3 differ in that the product is truncated to the length of
the operands before it is stored in the destination register. Because of this
truncation, OF should be tested to ensure that no significant bits are lost.
(For ways to test OF, refer to the INTO and PUSHF instructions.)
● Forms 2 and 3 of IMUL may also be used with unsigned operands because,
whether the operands are signed or unsigned, the low-order half of the
product is the same.
 Division Instructions
● The 80386 has separate division instructions for unsigned and signed
operands. DIV operates on unsigned numbers, while IDIV operates on
signed integers as well as unsigned. In either case, an exception (interrupt
zero) occurs if the divisor is zero or if the quotient is too large for AL, AX, or
EAX.
● DIV (Unsigned Integer Divide) performs an unsigned division of the
accumulator by the source operand. The dividend (the accumulator) is twice
the size of the divisor (the source operand); the quotient and remainder have
the same size as the divisor, as the following table shows.
Size of Source Operand
(divisor) Dividend Quotient Remainder
Byte AX AL AH
Word DX:AX AX DX
Doubleword EDX:EAX EAX EDX
● Non-integral quotients are truncated to integers toward 0. The remainder is
always less than the divisor. For unsigned byte division, the largest quotient
is 255. For unsigned word division, the largest quotient is 65,535. For
unsigned doubleword division the largest quotient is 2^(32) -1.
 Division Instructions...
● IDIV (Signed Integer Divide) performs a signed division of the
accumulator by the source operand. IDIV uses the same registers as
the DIV instruction.
● For signed byte division, the maximum positive quotient is +127, and
the minimum negative quotient is -128. For signed word division, the
maximum positive quotient is +32,767, and the minimum negative
quotient is -32,768. For signed doubleword division the maximum
positive quotient is 2^(31) -1, the minimum negative quotient is
-2^(31). Non-integral results are truncated towards 0. The remainder
always has the same sign as the dividend and is less than the divisor
in magnitude.
 Decimal Arithmetic Instructions
● Decimal arithmetic is performed by combining the binary arithmetic
instructions (already discussed in the prior section) with the decimal
arithmetic instructions. The decimal arithmetic instructions are used in
one of the following ways:
1. To adjust the results of a previous binary arithmetic operation to
produce a valid packed or unpacked decimal result.
2. To adjust the inputs to a subsequent binary arithmetic operation so
that the operation will produce a valid packed or unpacked decimal
result.
● These instructions operate only on the AL or AH registers. Most utilize
the AF flag.
 Packed BCD Adjustment
Instructions
● DAA (Decimal Adjust after Addition) adjusts the result of adding two
valid packed decimal operands in AL. DAA must always follow the
addition of two pairs of packed decimal numbers (one digit in each
half-byte) to obtain a pair of valid packed decimal digits as results.
The carry flag is set if carry was needed.
● DAS (Decimal Adjust after Subtraction) adjusts the result of
subtracting two valid packed decimal operands in AL. DAS must
always follow the subtraction of one pair of packed decimal numbers
(one digit in each half- byte) from another to obtain a pair of valid
packed decimal digits as results. The carry flag is set if a borrow was
needed.
 Unpacked BCD Adjustment
Instructions
● AAA (ASCII Adjust after Addition) changes the contents of register AL to a
valid unpacked decimal number, and zeros the top 4 bits. AAA must always
follow the addition of two unpacked decimal operands in AL. The carry flag is
set and AH is incremented if a carry is necessary.
● AAS (ASCII Adjust after Subtraction) changes the contents of register AL to
a valid unpacked decimal number, and zeros the top 4 bits. AAS must always
follow the subtraction of one unpacked decimal operand from another in AL.
The carry flag is set and AH decremented if a borrow is necessary.
● AAM (ASCII Adjust after Multiplication) corrects the result of a multiplication
of two valid unpacked decimal numbers. AAM must always follow the
multiplication of two decimal numbers to produce a valid decimal result. The
high order digit is left in AH, the low order digit in AL.
● AAD (ASCII Adjust before Division) modifies the numerator in AH and AL to
prepare for the division of two valid unpacked decimal operands so that the
quotient produced by the division will be a valid unpacked decimal number.
AH should contain the high-order digit and AL the low-order digit. This
instruction adjusts the value and places the result in AL. AH will contain zero.
 Logical Instructions
The group of logical instructions includes:
● The Boolean operation instructions
● Bit test and modify instructions
● Bit scan instructions
● Rotate and shift instructions
●
Byte set on condition
 Boolean Operation Instructions
● The logical operations are AND, OR, XOR, and NOT.
● NOT (Not) inverts the bits in the specified operand to form a one's
complement of the operand. The NOT instruction is a unary operation
that uses a single operand in a register or memory. NOT has no effect
on the flags.
● The AND, OR, and XOR instructions perform the standard logical
operations "and", "(inclusive) or", and "exclusive or". These instructions
can use the following combinations of operands:
- Two register operands
- A general register operand with a memory operand
- An immediate operand with either a general register operand or a
memory operand.
● AND, OR, and XOR clear OF and CF, leave AF undefined, and update
SF, ZF, and PF.
 The Boolean operation instructions...
● Bit Test and Modify Instructions
● This group of instructions operates on a single bit which can be in memory or in a general
register. The location of the bit is specified as an offset from the low-order end of the
operand. The value of the offset either may be given by an immediate byte in the instruction
or may be contained in a general register.
● These instructions first assign the value of the selected bit to CF, the carry flag. Then a new
value is assigned to the selected bit, as determined by the operation. OF, SF, ZF, AF, PF are
left in an undefined state.
● Bit Test and Modify Instructions
Instruction Effect on CF Effect on
Selected Bit
BT (Bit Test) CF := BIT (none)
BTS (Bit Test and Set) CF := BIT BIT := 1
BTR (Bit Test and Reset) CF := BIT BIT := 0
BTC (Bit Test and Complement) CF := BIT BIT := NOT(BIT)
 Bit Scan Instructions
● These instructions scan a word or doubleword for a one-bit and store
the index of the first set bit into a register. The bit string being
scanned may be either in a register or in memory. The ZF flag is set if
the entire word is zero (no set bits are found); ZF is cleared if a one-
bit is found. If no set bit is found, the value of the destination register
is undefined.
● BSF (Bit Scan Forward) scans from low-order to high-order (starting
from bit index zero).
● BSR (Bit Scan Reverse) scans from high-order to low-order (starting
from bit index 15 of a word or index 31 of a doubleword).
 Shift and Rotate Instructions
● The shift and rotate instructions reposition the bits within the
specified operand.
● These instructions fall into the following classes:
- Shift instructions
- Double shift instructions
- Rotate instructions
 Shift Instructions
● The bits in bytes, words, and doublewords may be shifted arithmetically or
logically. Depending on the value of a specified count, bits can be shifted up to
31 places.
● A shift instruction can specify the count in one of three ways. 1. One form of shift
instruction implicitly specifies the count as a single shift. 2. The second form
specifies the count as an immediate value. 3. The third form specifies the count
as the value contained in CL. This last form allows the shift count to be a variable
that the program supplies during execution. Only the low order 5 bits of CL are
used.
● CF always contains the value of the last bit shifted out of the destination
operand. In a single-bit shift, OF is set if the value of the high-order (sign) bit was
changed by the operation. Otherwise, OF is cleared. Following a multibit shift,
however, the content of OF is always undefined.
● The shift instructions provide a convenient way to accomplish division or
multiplication by binary power. Note however that division of signed numbers by
shifting right is not the same kind of division performed by the IDIV instruction.
 Shift Instructions...
● SAL (Shift Arithmetic Left) shifts the destination byte, word, or doubleword operand
left by one or by the number of bits specified in the count operand (an immediate
value or the value contained in CL). The processor shifts zeros in from the right (low-
order) side of the operand as bits exit from the left (high-order) side.

● SHL (Shift Logical Left) is a synonym for SAL (refer to SAL).

 Shift Instructions...
● SHR (Shift Logical Right) shifts the destination byte, word, or doubleword
operand right by one or by the number of bits specified in the count operand
(an immediate value or the value contained in CL). The processor shifts
zeros in from the left side of the operand as bits exit from the right side.
 Shift Instructions...
● SAR (Shift Arithmetic Right) shifts the destination byte, word, or doubleword operand to the right
by one or by the number of bits specified in the count operand (an immediate value or the value
contained in CL). The processor preserves the sign of the operand by shifting in zeros on the
left (high-order) side if the value is positive or by shifting by ones if the value is negative.
● Even though this instruction can be used to divide integers by a power of two, the type of
division is not the same as that produced by the IDIV instruction. The quotient of IDIV is
rounded toward zero, whereas the "quotient" of SAR is rounded toward negative infinity. This
difference is apparent only for negative numbers. For example, when IDIV is used to divide -9
by 4, the result is -2 with a remainder of -1. If SAR is used to shift -9 right by two bits, the result
is -3. The "remainder" of this kind of division is +3; however, the SAR instruction stores only the

high-order bit of the remainder (in CF).

 Shift Instructions...
● The code sequence in Figure produces the same result as IDIV for any M =
2^(N), where 0 < N < 32. This sequence takes about 12 to 18 clocks,
depending on whether the jump is taken; if ECX contains M, the
corresponding IDIV ECX instruction will take about 43 clocks.
 Double-Shift Instructions
● These instructions provide the basic operations needed to implement
operations on long unaligned bit strings. The double shifts operate either on
word or doubleword operands, as follows:
Taking two word operands as input and producing a one-word
output.
Taking two doubleword operands as input and producing a
doubleword output.
● Of the two input operands, one may either be in a general register or in
memory, while the other may only be in a general register. The results
replace the memory or register operand. The number of bits to be shifted is
specified either in the CL register or in an immediate byte of the instruction.
● Bits are shifted from the register operand into the memory or register
operand. CF is set to the value of the last bit shifted out of the destination
operand. SF, ZF, and PF are set according to the value of the result. OF and
AF are left undefined.
 Double-Shift Instructions...
● SHLD (Shift Left Double) shifts bits of the R/M field to the left, while shifting
high-order bits from the Reg field into the R/M field on the right. The result is
stored back into the R/M operand. The Reg field is not modified.
 Double-Shift Instructions...
● SHRD (Shift Right Double) shifts bits of the R/M field to the right, while
shifting low-order bits from the Reg field into the R/M field on the left. The
result is stored back into the R/M operand. The Reg field is not modified.
 Rotate Instructions
● Rotate instructions allow bits in bytes, words, and doublewords to be
rotated. Bits rotated out of an operand are not lost as in a shift, but
are "circled" back into the other "end" of the operand.
● Rotates affect only the carry and overflow flags. CF may act as an
extension of the operand in two of the rotate instructions, allowing a
bit to be isolated and then tested by a conditional jump instruction (JC
or JNC). CF always contains the value of the last bit rotated out, even
if the instruction does not use this bit as an extension of the rotated
operand.
● In single-bit rotates, OF is set if the operation changes the high-order
(sign) bit of the destination operand. If the sign bit retains its original
value, OF is cleared. On multibit rotates, the value of OF is always
undefined.
 Rotate Instructions...
● ROL (Rotate Left) rotates the byte, word, or doubleword destination operand left by
one or by the number of bits specified in the count operand (an immediate value or
the value contained in CL). For each rotation specified, the high-order bit that exits
from the left of the operand returns at the right to become the new low-order bit of the
operand.

● ROR (Rotate Right) rotates the byte, word, or doubleword destination operand right
by one or by the number of bits specified in the count operand (an immediate value or
the value contained in CL). For each rotation specified, the low-order bit that exits
from the right of the operand returns at the left to become the new high-order bit of
the operand.
 Rotate Instructions...
● RCL (Rotate Through Carry Left) rotates bits in the byte, word, or
doubleword destination operand left by one or by the number of bits
specified in the count operand (an immediate value or the value contained in
CL).
● This instruction differs from ROL in that it treats CF as a high-order one-bit
extension of the destination operand. Each high-order bit that exits from the
left side of the operand moves to CF before it returns to the operand as the
low-order bit on the next rotation cycle.
 Rotate Instructions...
● RCR (Rotate Through Carry Right) rotates bits in the byte, word, or
doubleword destination operand right by one or by the number of bits
specified in the count operand (an immediate value or the value contained in
CL).
● This instruction differs from ROR in that it treats CF as a low-order one-bit
extension of the destination operand. Each low-order bit that exits from the
right side of the operand moves to CF before it returns to the operand as the
high-order bit on the next rotation cycle.
 Byte-Set-On-Condition Instructions
● This group of instructions sets a byte to zero or one depending on
any of the 16 conditions defined by the status flags. The byte may be
in memory or may be a one-byte general register. These instructions
are especially useful for implementing Boolean expressions in high-
level languages such as Pascal.
● SETcc (Set Byte on Condition cc) set a byte to one if condition cc is
true; sets the byte to zero otherwise.
 Test Instruction
● TEST (Test) performs the logical "and" of the two operands,
clears OF and CF, leaves AF undefined, and updates SF, ZF,
and PF. The flags can be tested by conditional control transfer
instructions or by the byte-set-on-condition instructions. The
operands may be doublewords, words, or bytes.
● The difference between TEST and AND is that TEST does not
alter the destination operand. TEST differs from BT in that TEST
is useful for testing the value of multiple bits in one operations,
whereas BT tests a single bit.
 Control Transfer Instructions
● The 80386 provides both conditional and unconditional control transfer
instructions to direct the flow of execution. Conditional control transfers
depend on the results of operations that affect the flag register.
Unconditional control transfers are always executed.
● Unconditional Transfer Instructions JMP, CALL, RET, INT and IRET
instructions transfer control from one code segment location to another.
These locations can be within the same code segment (near control
transfers) or in different code segments (far control transfers). The variants
of these instructions that transfer control to other segments are discussed in
a later section of this chapter. If the model of memory organization used in a
particular 80386 application does not make segments visible to applications
programmers, intersegment control transfers will not be used.
 Jump Instruction
● JMP (Jump) unconditionally transfers control to the target location. JMP is a one-way transfer of
execution; it does not save a return address on the stack.
● The JMP instruction always performs the same basic function of transferring control from the
current location to a new location. Its implementation varies depending on whether the address
is specified directly within the instruction or indirectly through a register or memory.
● A direct JMP instruction includes the destination address as part of the instruction. An indirect
JMP instruction obtains the destination address indirectly through a register or a pointer
variable.
● Direct near JMP. A direct JMP uses a relative displacement value contained in the instruction.
The displacement is signed and the size of the displacement may be a byte, word, or
doubleword. The processor forms an effective address by adding this relative displacement to
the address contained in EIP. When the additions have been performed, EIP refers to the next
instruction to be executed.
● Indirect near JMP. Indirect JMP instructions specify an absolute address in one of several ways:
The program can JMP to a location specified by a general register (any of EAX, EDX, ECX,
EBX, EBP, ESI, or EDI). The processor moves this 32-bit value into EIP and resumes
execution.
● The processor can obtain the destination address from a memory operand specified in the
instruction.
● A register can modify the address of the memory pointer to select a destination address.
 Call Instruction
● CALL (Call Procedure) activates an out-of-line procedure, saving on the
stack the address of the instruction following the CALL for later use by a RET
(Return) instruction. CALL places the current value of EIP on the stack. The
RET instruction in the called procedure uses this address to transfer control
back to the calling program.
● CALL instructions, like JMP instructions have relative, direct, and indirect
versions.
● Indirect CALL instructions specify an absolute address in one of these ways:
The program can CALL a location specified by a general register (any of
EAX, EDX, ECX, EBX, EBP, ESI, or EDI). The processor moves this 32-bit
value into EIP.
● The processor can obtain the destination address from a memory operand
specified in the instruction.
 Return and Return-From-Interrupt
Instruction
● RET (Return From Procedure) terminates the execution of a procedure and
transfers control through a back-link on the stack to the program that
originally invoked the procedure. RET restores the value of EIP that was
saved on the stack by the previous CALL instruction.
● RET instructions may optionally specify an immediate operand. By adding
this constant to the new top-of-stack pointer, RET effectively removes any
arguments that the calling program pushed on the stack before the
execution of the CALL instruction.
● IRET (Return From Interrupt) returns control to an interrupted procedure.
IRET differs from RET in that it also pops the flags from the stack into the
flags register. The flags are stored on the stack by the interrupt mechanism.
 Conditional Transfer Instructions
● The conditional transfer instructions are jumps that may or may not transfer
control, depending on the state of the CPU flags when the instruction
executes.
● Conditional Jump Instructions
● Table shows the conditional transfer mnemonics and their interpretations.
The conditional jumps that are listed as pairs are actually the same
instruction. The assembler provides the alternate mnemonics for greater
clarity within a program listing.
● Conditional jump instructions contain a displacement which is added to the
EIP register if the condition is true. The displacement may be a byte, a word,
or a doubleword. The displacement is signed; therefore, it can be used to
jump forward or backward.
Conditional Transfer Instructions...
Conditional Transfer Instructions...
 Loop Instructions
● The loop instructions are conditional jumps that use a value placed in ECX to specify the
number of repetitions of a software loop. All loop instructions automatically decrement ECX
and terminate the loop when ECX=0. Four of the five loop instructions specify a condition
involving ZF that terminates the loop before ECX reaches zero.
●
LOOP (Loop While ECX Not Zero) is a conditional transfer that automatically decrements
the ECX register before testing ECX for the branch condition. If ECX is non-zero, the
program branches to the target label specified in the instruction. The LOOP instruction
causes the repetition of a code section until the operation of the LOOP instruction
decrements ECX to a value of zero. If LOOP finds ECX=0, control transfers to the instruction
immediately following the LOOP instruction. If the value of ECX is initially zero, then the
LOOP executes 2^(32) times.
●
LOOPE (Loop While Equal) and LOOPZ (Loop While Zero) are synonyms for the same
instruction. These instructions automatically decrement the ECX register before testing ECX
and ZF for the branch conditions. If ECX is non-zero and ZF=1, the program branches to the
target label specified in the instruction. If LOOPE or LOOPZ finds that ECX=0 or ZF=0,
control transfers to the instruction immediately following the LOOPE or LOOPZ instruction.
●
LOOPNE (Loop While Not Equal) and LOOPNZ (Loop While Not Zero) are synonyms for
the same instruction. These instructions automatically decrement the ECX register before
testing ECX and ZF for the branch conditions. If ECX is non-zero and ZF=0, the program
branches to the target label specified in the instruction. If LOOPNE or LOOPNZ finds that
ECX=0 or ZF=1, control transfers to the instruction immediately following the LOOPNE or
LOOPNZ instruction.
 Executing a Loop or Repeat Zero
Times
● JCXZ (Jump if ECX Zero) branches to the label specified in the instruction if
it finds a value of zero in ECX. JCXZ is useful in combination with the LOOP
instruction and with the string scan and compare instructions, all of which
decrement ECX.
● Sometimes, it is desirable to design a loop that executes zero times if the
count variable in ECX is initialized to zero. Because the LOOP instructions
(and repeat prefixes) decrement ECX before they test it, a loop will execute
2^(32) times if the program enters the loop with a zero value in ECX.
● A programmer may conveniently overcome this problem with JCXZ, which
enables the program to branch around the code within the loop if ECX is
zero when JCXZ executes.
● When used with repeated string scan and compare instructions, JCXZ can
determine whether the repetitions terminated due to zero in ECX or due to
satisfaction of the scan or compare conditions .
 Software-Generated Interrupts
● The INT n, , and BOUND instructions allow the programmer to specify a
transfer to an interrupt service routine from within a program.
● INT n (Software Interrupt) activates the interrupt service routine that
corresponds to the number coded within the instruction. The INT
instruction may specify any interrupt type. Programmers may use this
flexibility to implement multiple types of internal interrupts or to test the
operation of interrupt service routines. (Interrupts 0-31 are reserved by
Intel.) The interrupt service routine terminates with an IRET instruction
that returns control to the instruction that follows INT n.
● INTO (Interrupt on Overflow) invokes interrupt 4 if OF is set. Interrupt 4
is reserved for this purpose. OF is set by several arithmetic, logical, and
string instructions.
● BOUND (Detect Value Out of Range) verifies that the signed value
contained in the specified register lies within specified limits. An interrupt
(INT 5) occurs if the value contained in the register is less than the lower
bound or greater than the upper bound.
 Software-Generated Interrupts...
● The BOUND instruction includes two operands. The first operand specifies
the register being tested. The second operand contains the effective relative
address of the two signed BOUND limit values. The BOUND instruction
assumes that the upper limit and lower limit are in adjacent memory
locations. These limit values cannot be register operands; if they are, an
invalid opcode exception occurs.
● BOUND is useful for checking array bounds before using a new index value
to access an element within the array. BOUND provides a simple way to
check the value of an index register before the program overwrites
information in a location beyond the limit of the array.
● The block of memory that specifies the lower and upper limits of an array
might typically reside just before the array itself. This makes the array bounds
accessible at a constant offset from the beginning of the array. Because the
address of the array will already be present in a register, this practice avoids
extra calculations to obtain the effective address of the array bounds.
●
The upper and lower limit values may each be a word or a doubleword .
 String and Character Translation
Instructions
● The instructions in this category operate on strings rather than on
logical or numeric values. Refer also to the section on I/O for
information about the string I/O instructions (also known as block I/O).
● The power of 80386 string operations derives from the following
features of the architecture:
-> A set of primitive string operations
1. MOVS -- Move String
2. CMPS -- Compare string
3. SCAS -- Scan string
4. LODS -- Load string
5. STOS -- Store string
 String and Character Translation
Instructions...
-> Indirect, indexed addressing, with automatic incrementing or decrementing of
the indexes.
Indexes:
1. ESI -- Source index register
2. EDI -- Destination index register
-> Control flag:
1. DF -- Direction flag
-> Control flag instructions:
1. CLD -- Clear direction flag instruction
2. STD -- Set direction flag instruction
-> Repeat prefixes
1. REP -- Repeat while ECX not xero
2. REPE/REPZ -- Repeat while equal or zero
3. REPNE/REPNZ -- Repeat while not equal or not zero
 String and Character Translation
Instructions...
● The primitive string operations operate on one element of a string. A string
element may be a byte, a word, or a doubleword. The string elements are
addressed by the registers ESI and EDI. After every primitive operation ESI
and/or EDI are automatically updated to point to the next element of the
string. If the direction flag is zero, the index registers are incremented; if one,
they are decremented. The amount of the increment or decrement is 1, 2, or
4 depending on the size of the string element.
 Repeat Prefixes
● The repeat prefixes REP (Repeat While ECX Not Zero), REPE/REPZ
(Repeat While Equal/Zero), and REPNE/REPNZ (Repeat While Not
Equal/Not Zero) specify repeated operation of a string primitive. This
form of iteration allows the CPU to process strings much faster than
would be possible with a regular software loop.
● When a primitive string operation has a repeat prefix, the operation is
executed repeatedly, each time using a different element of the string.
The repetition terminates when one of the conditions specified by the
prefix is satisfied.
● At each repetition of the primitive instruction, the string operation may
be suspended temporarily in order to handle an exception or external
interrupt. After the interruption, the string operation can be restarted
again where it left off. This method of handling strings allows operations
on strings of arbitrary length, without affecting interrupt response.
 Repeat Prefixes...
● All three prefixes causes the hardware to automatically repeat the
associated string primitive until ECX=0. The differences among the repeat
prefixes have to do with the second termination condition. REPE/REPZ
and REPNE/REPNZ are used exclusively with the SCAS (Scan String)
and CMPS (Compare String) primitives. When these prefixes are used,
repetition of the next instruction depends on the zero flag (ZF) as well as
the ECX register. ZF does not require initialization before execution of a
repeated string instruction, because both SCAS and CMPS set ZF
according to the results of the comparisons they make. The differences
are summarized in the accompanying table.
Prefix Termination Termination
Condition 1 Condition 2
REP ECX = 0 (none)
REPE/REPZ ECX = 0 ZF = 0
REPNE/REPNZ ECX = 0 ZF = 1
 Indexing and Direction Flag Control
● The addresses of the operands of string primitives are determined by the ESI
and EDI registers. ESI points to source operands. By default, ESI refers to a
location in the segment indicated by the DS segment register. A segment-
override prefix may be used, however, to cause ESI to refer to CS, SS, ES,
FS, or GS. EDI points to destination operands in the segment indicated by ES;
no segment override is possible. The use of two different segment registers in
one instruction allows movement of strings between different segments.
● This use of ESI and DSI has led to the descriptive names source index and
destination index for the ESI and EDI registers, respectively. In all cases other
than string instructions, however, the ESI and EDI registers may be used as
general-purpose registers.
● When ESI and EDI are used in string primitives, they are automatically
incremented or decremented after to operation. The direction flag determines
whether they are incremented or decremented. The instruction CLD puts zero
in DF, causing the index registers to be incremented; the instruction STD puts
one in DF, causing the index registers to be decremented. Programmers
should always put a known value in DF before using string instructions in a
procedure.
 String Instructions
● MOVS (Move String) moves the string element pointed to by ESI to the location
pointed to by EDI. MOVSB operates on byte elements, MOVSW operates on word
elements, and MOVSD operates on doublewords. The destination segment register
cannot be overridden by a segment override prefix, but the source segment register
can be overridden.
● The MOVS instruction, when accompanied by the REP prefix, operates as a
memory-to-memory block transfer. To set up for this operation, the program must
initialize ECX and the register pairs ESI and EDI. ECX specifies the number of
bytes, words, or doublewords in the block.
● If DF=0, the program must point ESI to the first element of the source string and
point EDI to the destination address for the first element. If DF=1, the program must
point these two registers to the last element of the source string and to the
destination address for the last element, respectively.
● CMPS (Compare Strings) subtracts the destination string element (at ES:EDI) from
the source string element (at ESI) and updates the flags AF, SF, PF, CF and OF. If
the string elements are equal, ZF=1; otherwise, ZF=0. If DF=0, the processor
increments the memory pointers (ESI and EDI) for the two strings. CMPSB
compares bytes, MOVSW compares words, and MOVSD compares doublewords.
The segment register used for the source address can be changed with a segment
override prefix while the destination segment register cannot be overridden.
 String Instructions...
● SCAS (Scan String) subtracts the destination string element at ES:EDI
from EAX, AX, or AL and updates the flags AF, SF, ZF, PF, CF and OF. If
the values are equal, ZF=1; otherwise, ZF=0. If DF=0, the processor
increments the memory pointer (EDI) for the string. SCASB scans bytes;
SCASW scans words; SCASD scans doublewords. The destination
segment register (ES) cannot be overridden.
● When either the REPE or REPNE prefix modifies either the SCAS or
CMPS primitives, the processor compares the value of the current string
element with the value in EAX for doubleword elements, in AX for word
elements, or in AL for byte elements. Termination of the repeated operation
depends on the resulting state of ZF as well as on the value in ECX.
● LODS (Load String) places the source string element at ESI into EAX for
doubleword strings, into AX for word strings, or into AL for byte strings.
LODS increments or decrements ESI according to DF.
● STOS (Store String) places the source string element from EAX, AX, or AL
into the string at ES:DSI. STOS increments or decrements EDI according
to DF.
 Instructions for Block-Structured
Languages
● The instructions in this section provide machine-language support for functions
normally found in high-level languages. These instructions include ENTER and
LEAVE, which simplify the programming of procedures.
● ENTER (Enter Procedure) creates a stack frame that may be used to implement the
scope rules of block-structured high-level languages. A LEAVE instruction at the end
of a procedure complements an ENTER at the beginning of the procedure to simplify
stack management and to control access to variables for nested procedures.
● The ENTER instruction includes two parameters. The first parameter specifies the
number of bytes of dynamic storage to be allocated on the stack for the routine being
entered. The second parameter corresponds to the lexical nesting level (0-31) of the
routine. (Note that the lexical level has no relationship to either the protection
privilege levels or to the I/O privilege level.)
● The specified lexical level determines how many sets of stack frame pointers the
CPU copies into the new stack frame from the preceding frame. This list of stack
frame pointers is sometimes called the display. The first word of the display is a
pointer to the last stack frame. This pointer enables a LEAVE instruction to reverse
the action of the previous ENTER instruction by effectively discarding the last stack
frame. Example:
● ENTER 2048,3
 Instructions for Block-Structured
Languages...
● Allocates 2048 bytes of dynamic storage on the stack and sets up pointers to two
previous stack frames in the stack frame that ENTER creates for this procedure. After
ENTER creates the new display for a procedure, it allocates the dynamic storage space
for that procedure by decrementing ESP by the number of bytes specified in the first
parameter. This new value of ESP serves as a starting point for all PUSH and POP
operations within that procedure.
● To enable a procedure to address its display, ENTER leaves EBP pointing to the
beginning of the new stack frame. Data manipulation instructions that specify EBP as a
base register implicitly address locations within the stack segment instead of the data
segment.
● The ENTER instruction can be used in two ways: nested and non-nested. If the lexical
level is 0, the non-nested form is used. Since the second operand is 0, ENTER pushes
EBP, copies ESP to EBP and then subtracts the first operand from ESP. The nested
form of ENTER occurs when the second parameter (lexical level) is not 0.
● Figure 3-16 gives the formal definition of ENTER.
Instructions for Block-Structured
Languages...
 Instructions for Block-Structured
Languages...
● The main procedure (with other procedures nested within) operates at the
highest lexical level, level 1. The first procedure it calls operates at the next
deeper lexical level, level 2. A level 2 procedure can access the variables of
the main program which are at fixed locations specified by the compiler. In
the case of level 1, ENTER allocates only the requested dynamic storage
on the stack because there is no previous display to copy.
● A program operating at a higher lexical level calling a program at a lower
lexical level requires that the called procedure should have access to the
variables of the calling program. ENTER provides this access through a
display that provides addressability to the calling program's stack frame.
● A procedure calling another procedure at the same lexical level implies that
they are parallel procedures and that the called procedure should not have
access to the variables of the calling procedure. In this case, ENTER copies
only that portion of the display from the calling procedure which refers to
previously nested procedures operating at higher lexical levels. The new
stack frame does not include the pointer for addressing the calling
procedure's stack frame.
 Instructions for Block-Structured
Languages...
● ENTER treats a reentrant procedure as a procedure calling another procedure
at the same lexical level. In this case, each succeeding iteration of the
reentrant procedure can address only its own variables and the variables of
the calling procedures at higher lexical levels. A reentrant procedure can
always address its own variables; it does not require pointers to the stack
frames of previous iterations.
● By copying only the stack frame pointers of procedures at higher lexical levels,
ENTER makes sure that procedures access only those variables of higher
lexical levels, not those at parallel lexical levels (see Figure 3-17 ). Figures 3-
18 through 3-21 demonstrate the actions of the ENTER instruction if the
modules shown in Figure 3-17 were to call one another in alphabetic order.
● Block-structured high-level languages can use the lexical levels defined by
ENTER to control access to the variables of previously nested procedures.
Referring to Figure 3-17 for example, if PROCEDURE A calls PROCEDURE B
which, in turn, calls PROCEDURE C, then PROCEDURE C will have access
to the variables of MAIN and PROCEDURE A, but not PROCEDURE B
because they operate at the same lexical level. Following is the complete
definition of access to variables for Figure 3-17 .
Instructions for Block-Structured
Languages...
 Instructions for Block-Structured
Languages...
1. MAIN PROGRAM has variables at fixed locations.
2. PROCEDURE A can access only the fixed variables of MAIN.
3. PROCEDURE B can access only the variables of PROCEDURE A and MAIN.
-PROCEDURE B cannot access the variables of PROCEDURE C or -
PROCEDURE D.
4. PROCEDURE C can access only the variables of PROCEDURE A and
MAIN.PROCEDURE C cannot access the variables of PROCEDURE B or
PROCEDURE D.
5. PROCEDURE D can access the variables of PROCEDURE C, PROCEDURE
A, and MAIN. PROCEDURE D cannot access the variables of PROCEDURE B.
ENTER at the beginning of the MAIN PROGRAM creates dynamic storage
space for MAIN but copies no pointers. The first and only word in the display
points to itself because there is no previous value for LEAVE to return to EBP.
See Figure 3-18 .
Instructions for Block-Structured
Languages...
● After MAIN calls PROCEDURE A, ENTER creates a new display for PROCEDURE A with
the first word pointing to the previous value of EBP (BPM for LEAVE to return to the MAIN
stack frame) and the second word pointing to the current value of EBP. Procedure A can
access variables in MAIN since MAIN is at level 1. Therefore the base for the dynamic
storage for MAIN is at [EBP-2]. All dynamic variables for MAIN are at a fixed offset from
this value. See Figure 3-19 .
 Instructions for Block-Structured
Languages...
● After PROCEDURE A calls PROCEDURE B, ENTER creates a new display for
PROCEDURE B with the first word pointing to the previous value of EBP, the
second word pointing to the value of EBP for MAIN, and the third word pointing to
the value of EBP for A and the last word pointing to the current EBP. B can access
variables in A and MAIN by fetching from the display the base addresses of the
respective dynamic storage areas. See Figure 3-20 . After PROCEDURE B calls
PROCEDURE C, ENTER creates a new display for PROCEDURE C with the first
word pointing to the previous value of EBP, the second word pointing to the value
of EBP for MAIN, and the third word pointing to the EBP value for A and the third
word pointing to the current value of EBP. Because PROCEDURE B and
PROCEDURE C have the same lexical level, PROCEDURE C is not allowed
access to variables in B and therefore does not receive a pointer to the beginning
of PROCEDURE B's stack frame. See Figure 3-21 .
● LEAVE (Leave Procedure) reverses the action of the previous ENTER instruction.
The LEAVE instruction does not include any operands. LEAVE copies EBP to ESP
to release all stack space allocated to the procedure by the most recent ENTER
instruction. Then LEAVE pops the old value of EBP from the stack. A subsequent
RET instruction can then remove any arguments that were pushed on the stack by
the calling program for use by the called procedure.
 Flag Control Instructions
● The flag control instructions provide a method for directly changing the state of bits in the flag
register.
Carry and Direction Flag Control Instructions
● The carry flag instructions are useful in conjunction with rotate-with-carry instructions RCL
and RCR. They can initialize the carry flag, CF, to a known state before execution of a rotate
that moves the carry bit into one end of the rotated operand.
● The direction flag control instructions are specifically included to set or clear the direction flag,
DF, which controls the left-to-right or right-to-left direction of string processing. If DF=0, the
processor automatically increments the string index registers, ESI and EDI, after each
execution of a string primitive. If DF=1, the processor decrements these index registers.
Programmers should use one of these instructions before any procedure that uses string
instructions to insure that DF is set properly.
Flag Control Instruction Effect
STC (Set Carry Flag) CF := 1
CLC (Clear Carry Flag) CF := 0
CMC (Complement Carry Flag) CF := NOT (CF)
CLD (Clear Direction Flag) DF := 0
STD (Set Direction Flag) DF := 1
 Flag Transfer Instructions
● Though specific instructions exist to alter CF and DF, there is no direct method
of altering the other applications-oriented flags. The flag transfer instructions
allow a program to alter the other flag bits with the bit manipulation instructions
after transferring these flags to the stack or the AH register.
● The instructions LAHF and SAHF deal with five of the status flags, which are
used primarily by the arithmetic and logical instructions.
● LAHF (Load AH from Flags) copies SF, ZF, AF, PF, and CF to AH bits 7, 6, 4, 2,
and 0, respectively. The contents of the remaining bits (5, 3, and 1) are
undefined. The flags remain unaffected.
● SAHF (Store AH into Flags) transfers bits 7, 6, 4, 2, and 0 from AH into SF, ZF,
AF, PF, and CF, respectively.
● The PUSHF and POPF instructions are not only useful for storing the flags in
memory where they can be examined and modified but are also useful for
preserving the state of the flags register while executing a procedure.
 Flag Transfer Instructions
● PUSHF (Push Flags) decrements ESP by two and then transfers the low-order word
of the flags register to the word at the top of stack pointed to by ESP (see Figure 3-
23). The variant PUSHFD decrements ESP by four, then transfers both words of the
extended flags register to the top of the stack pointed to by ESP (the VM and RF
flags are not moved, however).
● POPF (Pop Flags) transfers specific bits from the word at the top of stack into the
low-order byte of the flag register (see Figure 3-23), then increments ESP by two.
The variant POPFD transfers specific bits from the doubleword at the top of the stack
into the extended flags register (the RF and VM flags are not changed, however),
then increments ESP by four.
 Coprocessor Interface Instructions
● A numerics coprocessor (e.g., the 80387 or 80287) provides an extension
to the instruction set of the base architecture. The coprocessor extends
the instruction set of the base architecture to support high-precision
integer and floating-point calculations. This extended instruction set
includes arithmetic, comparison, transcendental, and data transfer
instructions. The coprocessor also contains a set of useful constants to
enhance the speed of numeric calculations.
● A program contains instructions for the coprocessor in line with the
instructions for the CPU. The system executes these instructions in the
same order as they appear in the instruction stream. The coprocessor
operates concurrently with the CPU to provide maximum throughput for
numeric calculations.
● The 80386 also has features to support emulation of the numerics
coprocessor when the coprocessor is absent. The software emulation of
the coprocessor is transparent to application software but requires more
time for execution . Refer to Chapter 11 for more information on
coprocessor emulation.
Coprocessor Interface Instructions...
● ESC (Escape) is a 5-bit sequence that begins the opcodes that identify floating point
numeric instructions. The ESC pattern tells the 80386 to send the opcode and
addresses of operands to the numerics coprocessor. The numerics coprocessor uses
the escape instructions to perform high-performance, high-precision floating point
arithmetic that conforms to the IEEE floating point standard 754.
● WAIT (Wait) is an 80386 instruction that suspends program execution until the 80386
CPU detects that the BUSY pin is inactive. This condition indicates that the
coprocessor has completed its processing task and that the CPU may obtain the
results.
 Segment Register Instructions
● This category actually includes several distinct types of instructions. These various
types are grouped together here because, if systems designers choose an
unsegmented model of memory organization, none of these instructions is used by
applications programmers. The instructions that deal with segment registers are:

Segment-register transfer instructions.

MOV SegReg, ...
MOV ..., SegReg
PUSH SegReg
POP SegReg
Control transfers to another executable segment.
JMP far direct and indirect
CALL far
RET far
Data pointer instructions.
LDS
LES
LFS
LGS
LSS
 Segment Register Instructions
● Note that the following interrupt-related instructions are different; all are capable of
transferring control to another segment, but the use of segmentation is not apparent
to the applications programmer.
INT n
INTO
BOUND
IRET
● Segment-Register Transfer Instructions
The MOV, POP, and PUSH instructions also serve to load and store segment
registers. These variants operate similarly to their general-register counterparts
except that one operand can be a segment register. MOV cannot move segment
register to a segment register. Neither POP nor MOV can place a value in the code-
segment register CS; only the far control-transfer instructions can change CS.
 Far Control Transfer Instructions
● The far control-transfer instructions transfer control to a location in
another segment by changing the content of the CS register.
● Direct far JMP. Direct JMP instructions that specify a target
location outside the current code segment contain a far pointer.
This pointer consists of a selector for the new code segment and
an offset within the new segment.
● Indirect far JMP. Indirect JMP instructions that specify a target
location outside the current code segment use a 48-bit variable to
specify the far pointer.
●
Far CALL. An intersegment CALL places both the value of EIP
and CS on the stack.
● Far RET. An intersegment RET restores the values of both CS
and EIP which were saved on the stack by the previous
intersegment CALL instruction.
 Data Pointer Instructions
● The data pointer instructions load a pointer (consisting of a segment
selector and an offset) to a segment register and a general register.
● LDS (Load Pointer Using DS) transfers a pointer variable from the source
operand to DS and the destination register. The source operand must be
a memory operand, and the destination operand must be a general
register. DS receives the segment-selector of the pointer. The destination
register receives the offset part of the pointer, which points to a specific
location within the segment. Example:
LDS ESI, STRING_X
● Loads DS with the selector identifying the segment pointed to by a
STRING_X, and loads the offset of STRING_X into ESI. Specifying ESI
as the destination operand is a convenient way to prepare for a string
operation on a source string that is not in the current data segment.
● LES (Load Pointer Using ES) operates identically to LDS except that ES
receives the segment selector rather than DS. Example:
LES EDI, DESTINATION_X
 Data Pointer Instructions...
● Loads ES with the selector identifying the segment pointed to by
DESTINATION_X, and loads the offset of DESTINATION_X into EDI. This
instruction provides a convenient way to select a destination for a string
operation if the desired location is not in the current extra segment.
● LFS (Load Pointer Using FS) operates identically to LDS except that FS
receives the segment selector rather than DS.
● LGS (Load Pointer Using GS) operates identically to LDS except that GS
receives the segment selector rather than DS.
● LSS (Load Pointer Using SS) operates identically to LDS except that SS
receives the segment selector rather than DS. This instruction is especially
important, because it allows the two registers that identify the stack
(SS:ESP) to be changed in one uninterruptible operation. Unlike the other
instructions which load SS, interrupts are not inhibited at the end of the LSS
instruction. The other instructions (e.g., POP SS) inhibit interrupts to permit
the following instruction to load ESP, thereby forming an indivisible load of
SS:ESP. Since both SS and ESP can be loaded by LSS, there is no need to
inhibit interrupts.
 Miscellaneous Instructions
● Address Calculation Instruction
LEA (Load Effective Address) transfers the offset of the source operand
(rather than its value) to the destination operand. The source operand must
be a memory operand, and the destination operand must be a general
register. This instruction is especially useful for initializing registers before
the execution of the string primitives (ESI, EDI) or the XLAT instruction
(EBX). The LEA can perform any indexing or scaling that may be needed.
Example:
LEA EBX, EBCDIC_TABLE
Causes the processor to place the address of the starting location of the
table labeled EBCDIC_TABLE into EBX.
● No-Operation Instruction
NOP (No Operation) occupies a byte of storage but affects nothing but the
instruction pointer, EIP.
 Miscellaneous Instructions...
● Translate Instruction
XLAT (Translate) i replaced a byte in the AL register with a byte from a user-
coded translation table. When XLAT is executed, AL should have the
unsigned index to the table addressed by EBX. XLAT changes the contents
of AL from table index to table entry. EBX is unchanged. The XLAT
instruction is useful for translating from one coding system to another such
as from ASCII to EBCDIC. The translate table may be up to 256 bytes long.
The value placed in the AL register serves as an index to the location of the
corresponding translation value.
 Assembler Directives
● Assembly language consists of two types of statements viz.
● Executable statements- These are the statements to be executed by the
processor. It consists of the entire instruction set of 8086.
● Assembler directives- These are the statements that direct the assembler to
do something. As the name says, it directs the assembler to do a task.
● The specialty of these statements is that they are effective only during the
assembly of a program but they do not generate any code that is machine
executable.
● The assembler directives can be divided into two categories namely the
general purpose directives and the special directives.
 Assembler Directives...
They are classified into the following categories based on the function
performed by them-
● Simplified segment directives
● Data allocation directives
● Segment directives
● Macros related directives
● Code label directives
● Scope directives
● Listing control directives
● Miscellaneous directives
 Assembler Directives...
● .CODE- This assembler directive indicates the beginning of the code
segment. Its format is as follows: .CODE [name] The name in this format is
optional.
● .DATA- This directive indicates the beginning of the data segment.
● .MODEL- This directive is used for selecting a standard memory model for
the assembly language program. Each memory model has various
limitations depending on the maximum space available for code and data.
● .STACK- This directive is used for defining the stack. Its format is as follows:
.STACK [size]
● Define Byte [DB]- This directive defines the byte type variable.
● Define Word [DW]- The DW directive defines items that are one word (two
bytes) in length.
● Define Double word [DD]- It defines the data items that are a double word
(four bytes) in length.
 Assembler Directives...
● Define Quad word [DQ]- This directive is used to tell the assembler to declare
variable 4 words in length or to reserve 4 words of storage in memory.
● Define Ten bytes [DT]- It is used to define the data items that are 10 bytes long.
● ASSUME- The directive is used for telling the assembler the name of the logical
segment which should be used.
● END- This is placed at the end of a source and it acts as the last statement of a
program. This is because the END directive terminates the entire program.
● ALIGN- This directive will tell the assembler to align the next instruction on an
address which corresponds to the given value.
● LABEL- This directive assigns name to the current value of the location counter.
● INCLUDE- This directive is used to tell the assembler to insert a block of source
code from the named file into the current source module. This shortens the
source code. Its format is: INCLUDE path: file name
Procedure and Macros