MODULE III

S. No. TOPICS PAGE NO.

2 ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS 1

3 DESIGN OF SYNCHRONOUS SEQUENTIAL CIRCUITS 5

4 SYNCHRONOUS COUNTERS 11

5 SHIFT REGISTERS 17
5.1 Serial-in parallel-out shift register 17
5.2 Serial-in serial-out shift register 18
5.3 Parallel-in parallel-out shift register 18
5.4 Parallel-in serial-out shift register 19
5.5 Universal shift register 20

6 SHIFT COUNTERS 21
6.1 Ring counter 21
6.2 Johnson counter 22

2 ANALYSIS OF SYNCHRONOUS SEQUENTIAL CIRCUITS

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The analysis of synchronous sequential circuits consists of obtaining a state table or

state diagram for the time sequence of inputs, outputs and internal states.

ANALYSIS PROCEDURE
1. Determine the flip-flop input and the circuit output functions from the logic
diagram.
2. Determine the next state equations using characteristic equation of flip flops
3. Derive the state table.
4. Draw the state diagram.
State table
The state table consists of four sections which are present state, input, next state and
output.
l The present state designates the states of flip-flops before the occurrence of a
clock pulse.
l The next state shows the states of flip-flops after the application of a clock
pulse.
l The output section lists the values of the output variables during the present
state.
State diagram
l State diagram is a pictorial representation of information available in state
table.

l In this diagram state is represented by a circle, and the transition between

states is indicated by directed lines connecting the circles. A directed line
connecting a circle with itself indicates that next state is same as present state.
l The binary number inside each circle identifies the state represented by the
circle and 0/1 represents input/output.

Problems
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1) Derive the state table and state diagram of the following sequential circuit

i) Flip flop input functions

The circuit has no outputs and therefore the state table does not need an output
column. The input function is
D = Q⊕T
ii) Next state equations
Q (t+1) = D (from characteristic equation of D flip flop)

Q (t+1) = Q ⊕ T
Substitute input function in above equation

iii) State table

Present State Input Next State

Q T Q(t+1)
0 0 0
0 1 1
1 0 1
1 1 0

iv) State diagram

2) A sequential circuit has two JK flip-flops, one input x, and one output y. The logic
diagram of the circuit is shown below. Derive the state table and state diagram of the
circuit.
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i) Flip flop input and output functions

JA = B KA = B'
JB = (A⊕X)' KB = (A⊕X)'
Y = B⊕A⊕X

ii) Next state equations

A(t+1) = JA A' + KA' A (from characteristic equation of JK flip flop)
A(t+1) = BA' + BA = B(A+A')
A(t+1 )= B
B(t+1) = JB B' + KB' B

B(t+1) = (A⊕X ⊕B)'

B(t+1) = (A⊕X)' B'+ (A⊕X) B (by X-NOR)

iii) State table

Present State Input Next State Output
A B X A(t+1) B(t+1) Y
0 0 0 0 1 0
0 0 1 0 0 1
0 1 0 1 0 1
0 1 1 1 1 0
1 0 0 0 0 1
1 0 1 0 1 0
1 1 0 1 1 0
1 1 1 1 0 1

iv) State diagram

3) A sequential circuit has two JK flip-flops A and B; one inputs x and one output z, the flip-
flop input functions and the circuit output functions are as follows
'
J A =B ; J B=x
' ' '
K A =B x ; K B= A x + x A = A ⨁ x ; Z= A ⨁ B
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i) Next state equations

' '
A ( t+ 1 )=J A A + K A A ( characteristic equation of JK flipflop )
= B A' + (X' B)' . A (by input functions)
= B A' + AB' +AX
' '
B ( t+1 )=J B B + K B B ( characteristicequationofJKflipflop )
= B'X' + ABX + A'BX'

ii) State table

Present State Input Next State Output
A B X A(t+1) B(t+1) Z
0 0 0 0 1 0
0 0 1 0 0 0
0 1 0 1 1 1
0 1 1 1 0 1
1 0 0 1 1 1
1 0 1 1 0 1
1 1 0 0 0 0
1 1 1 1 1 0

iii) State diagram

4. A sequential circuit has one JK flip-flop; one input, x; and no output. The logic diagram of
the circuit is shown below. Derive the state table and draw the state diagram.
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i) Flip flop input function

J = X⊕Q
K = XQ'

ii) Next state equations

Q(t+1) = J Q' + K'Q (from characteristic equation of JK flip flop)
= (X⊕Q) Q' + (XQ')' Q
Q(t+1) = (X⊕Q) Q' + (X' +Q) Q

iii) State table

Present State Input Next State
Q X Q(t+1)
0 0 0
0 1 1
1 0 1
1 1 1

iv) State diagram

3 DESIGN OF SYNCHRONOUS SEQUENTIAL CIRCUITS

Design procedure for sequential circuits

1. Obtain the state table from the given state diagram

2. Determine the number of flip-flops required using the condition given below and
assign a letter to the output of each flipflop.
2n ≥ N N = Number of states
n = Number of flip-flops

3. Derive the flipflop inputs and outputs from the state table

4. Obtain the flip-flop input functions and output functions using K-map method

5. Draw the logic diagram.

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Design Problems:
1. Design a sequential circuit using D flip-fop for the state diagram given below. The
circuit has one input T and no output.

(i) State table

Present State Input Next State

Q T Q(t+1)
0 0 0
0 1 1
1 0 1
1 1 0

(ii) No of flip-flop needed :

2n ≥ N
2n ≥ 2
2n ≥ 21
Number of flip-flops needed is 1

(iii) Flip-flop inputs

Present State Input Next State Flip-flop

Q T Q(t+1) input D
0 0 0 0
0 1 1 1
1 0 1 1
1 1 0 0

(iv) Flip-flop input function using K map

D = Q⊕T
(v) Logic Diagram
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2. Design a sequential circuit with two JK flip-flops (A, B), one input (x) and one
output (y) for the given state diagram

(i) State table

Present State Input Next State Output
A B X A(t+1) B(t+1) Y
0 0 0 0 1 0
0 0 1 0 0 1
0 1 0 1 0 1
0 1 1 1 1 0
1 0 0 0 0 1
1 0 1 0 1 0
1 1 0 1 1 0
1 1 1 1 0 1

(ii) No of flip-flop needed :

2n ≥ N
2n ≥ 4
2n ≥ 22
Number of flip-flops needed is 2

(iii) Flip-flop inputs and circuit outputs

Present Input Next State Flip-flop inputs Output
State
A B X A(t+1) B(t+1) JA KA JB KB Y
0 0 0 0 1 0 X 1 X 0
0 0 1 0 0 0 X 0 X 1
0 1 0 1 0 1 X X 1 1
0 1 1 1 1 1 X X 0 0
1 0 0 0 0 X 1 0 X 1
1 0 1 0 1 X 1 1 X 0
1 1 0 1 1 X 0 X 0 0
1 1 1 1 0 X 0 X 1 1
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(iv) Flip-flop input function using K-map

JA = B KA = B'
JB = (A⊕X)' KB = (A⊕X)'
Y = A⊕B⊕X

(v) Logic Diagram

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3. Design a sequential circuit with two D flip-flops (A, B), one input (X) and one
output (Y) for the given state diagram

(i) State table:

Present State Input Next State Output

A B X A(t+1) B(t+1) Y
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 1
0 1 1 1 1 0
1 0 0 0 0 1
1 0 1 1 0 0
1 1 0 0 0 1
1 1 1 1 0 0

(ii) No of flip-flop needed :

2n ≥ N
2n ≥ 4
2n ≥ 22
Number of flip-flops needed is 2

(iii) Flip-flop inputs and circuit outputs

Present State Input Next State Flip-flop Inputs Output

A B X A(t+1) B(t+1) DA DB Y
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0
0 1 0 0 0 0 0 1
0 1 1 1 1 1 1 0
1 0 0 0 0 0 0 1
1 0 1 1 0 1 0 0
1 1 0 0 0 0 0 1
1 1 1 1 0 1 0 0
(iv) Flip-flop input function using K-map
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DA = AX + BX DB = A'X Y = AX'+ BX' = (A + B).X'

(v) Logic diagram

4 SYNCHRONOUS COUNTERS
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A sequential circuit that goes through a sequence of states, when input pulses (clock
pulses) are applied is called a counter. A counter which changes its states with each clock
pulse is a synchronous counter. The sequence it follows may be the binary number sequence
or any other sequence of states (non-binary).

A counter that follows the binary number sequence is called as a binary counter. An
n-bit binary counter consists of n- flip-flops and can count in binary from 0 to 2 n -1. Counters
are used for counting the number of occurrences of an event and for generating timing
sequence to control operation in digital system.

Modulo-N (mod-N) Counter:

The total number of states in counter is called as modulus. If counter is modulo-N,

then it has N different states. It has N counts in binary. The number of flip-flops used to
design the modulo-N counter is given by 2 n ≥ N, where N is the number of states and n is the
number of flip-flops.

MOD-2 counter counts 2 discrete states (0 and 1) and it consists of a single flip-flop.
MOD-3 counter counts 3 discrete states (00, 01 and 10) and it consists of (2 2 ≥ 3) = 2 flip-
flops. The two flip-flop counter has natural count of 4 discrete states. But mod-3 counter is
designed in such a way that it skips over the fourth state (i.e. 11) and repeats only the three
counts. Similarly, a MOD-10 counter (decade counter) has 10 distinct states, so it has 10
counts and (24 ≥ 10) = 4 flip-flops.

3-BIT BINARY COUNTER:

State diagram of a 3-bit counter is shown in Figure. The flip-flop outputs repeat the
binary sequence after 111 with a return to 000. The state of counter changes with application
of clock pulse, which is the only input to the circuit. The flip-flop remains in the same state if
no clock pulse occurs. The outputs are specified by present state of flip-flops.

State diagram of a 3-bit counter

The 3-bit binary counter is also a MOD-8 counter, which follows a binary sequence with
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8 distinct states.
The binary counters can be constructed with any flip-flops. Generally, T flip-flops
are used because of their complementing property.

The excitation table for the 3-bit binary counter is shown below:

Flipflop inputs
Present State Next State
(from excitation table)
A2 A1 A0 A2(t+1) A1(t+1) A0(t+1) TA2 TA1 TA0
0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 1
0 1 0 0 1 1 0 0 1
0 1 1 1 0 0 1 1 1
1 0 0 1 0 1 0 0 1
1 0 1 1 1 0 0 1 1
1 1 0 1 1 1 0 0 1
1 1 1 0 0 0 1 1 1

The excitation for the T- inputs of the T flip-flop is obtained using excitation table of
T flip-flop by looking at the present state and next state of flip-flops in the state table.
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The logic diagram of the three bit counter is shown below:

BINARY UP COUNTER:

An n-bit synchronous binary up counter goes through the binary states in order
from 0 to 2n-1. For example, a 2-bit binary up counter goes through the binary states in
order from 0 to 3 i.e. it goes like 00,01,10,11 and again goes back to 00 to repeat the count
for each clock pulse.
A 2-bit synchronous binary up counter is designed as follows:
State diagram for 2-bit binary counter:

Number of Flip-flops required:

2n ≥ N, where N is the number of states and n is the number of flip-flops required. So,
n
here 2 ≥ 4, as there are 4 states (00, 01, 10, 11).
n=2 is the minimum number of flip-flop required for designing the 2-bit up-counter circuit.

Excitation table:

Present state Next state Flip-flop Inputs

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A B A(t+1) B(t+1) JA KA JB KB
0 0 0 1 0 x 1 x
0 1 1 0 1 x x 1
1 0 1 1 x 0 1 x
1 1 0 0 x 1 x 1

K-map for finding the expressions for the flip-flop inputs:

JA=B KA=B JB=1 KB=1

Logic circuit for 2-bit synchronous up counter:

BINARY DOWN COUNTER:

An-bit synchronous binary down counter goes through the binary states in reverse
order from 2n– 1 to 0. For example a binary 4-bit down counter (24–1 = 15 to 0) counts
down from 1111 to 0000 and back to 1111 to repeat the count.

A 2-bit binary down counter can be designed as follows:

State diagram of 2-bit binary down counter:

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Number of Flip-flops required:

2n ≥ N, where N is the number of states and n is the number of flip-flops required. So,
here 2n ≥ 4, as there are 4 states (00, 01, 10, and 11).
n=2 is the minimum number of flip-flop required for designing the 2-bit up-counter circuit.

Excitation table:

Present state Next state Flip-flop Inputs

A B A(t+1) B(t+1) JA KA JB KB
1 1 1 0 X 0 x 1
1 0 0 1 X 1 1 x
0 1 0 0 0 x x 1
0 0 1 1 1 x 1 x

K-map for finding the expressions for the flip-flop inputs:

JA=B′ KA=B′ JB=1 KB=1

Logic circuit for 2-bit synchronous down counter:

2-BIT SYNCHRONOUS UP/DOWN COUNTER

A counter capable of counting either up or down can be combined in one circuit with
a selection input.
The circuit of a 2-bit up–down binary counter using T flip‐flops has an up/down
control input X. When the input X is 1, the circuit counts up (00 to 11) and when the input X
is 0, the circuit counts down (11 to 00).

State diagram of 2-bit up–down binary counter:

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Excitation table:

Input Flip-flop
Present state Next state
Up/Down Input
X A B A(t+1) B(t+1) TA TB
1 0 0 0 1 0 1
1 0 1 1 0 1 1
1 1 0 1 1 0 1
1 1 1 0 0 1 1
0 1 1 1 0 0 1
0 1 0 0 1 1 1
0 0 1 0 0 0 1
0 0 0 1 1 1 1

K-map for finding the expressions for the flip-flop inputs:

Logic circuit for 2-bit binary up/down counter:

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5 SHIFT REGISTERS

A register is a group of flipflops. Each flipflop is capable of storing one bit of

information. An n-bit register consists of a group of n flipflops, capable of storing n bits of
binary information. A register capable of shifting the binary information in a certain direction
(serially from either left or right direction) is called shift register. A shift register is used for
storing and shifting data which is in the form of 1’s and 0’s entered from an external source.
The binary information in a register can be shifted within the register or into or out of the
register when driven by a common clock pulse.
The simplest shift register consists of a number of D flipflops connected together in a
chain arrangement. The number of individual data flipflops used to make up shift registers is
determined by the number of bits to be stored.
Generally, Shift registers operate in one of four different modes:
 Serial-in Parallel-out (SIPO)
 Serial-in Serial-out (SISO)
 Parallel-in Parallel-out (PIPO)
 Parallel-in Serial-out (PISO)
5.1 Serial-in parallel-out (SIPO)
Serial-in Parallel-out shift register accepts data serially, one after the other on a single
input line and produces the stored information on its output in parallel form. Once the data are
stored, each bit appears on its respective output lines and all bits are available simultaneously.

4 – bit Serial-in parallel-out (SIPO) Shift Register

If a logic ‘1’ is connected to the DATA input pin of FF A (flipflop – A) then on the first
clock pulse, the output of FFA will be set HIGH ie., QA becomes ‘1’ and the remaining
flipflops may have a logic ‘1’ or logic ‘0’ (specified as don’t cares in the logic table given
below). Assume now that the DATA input pin of FFA is logic ‘0’.
The next clock pulse will change the output of FF A to logic ‘0’ and the output of FF B
and QB HIGH to logic ‘1’. The logic ‘1’ has now moved or been ‘shifted’ one place along the
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register to the right. When the third clock pulse arrives this logic ‘1’ values moves to the
output of FFc (Qc) and so on.
The effect of each clock pulse is to shift the DATA contents of each stage one place to
the right, and this is shown in the following table. After the complete DATA is stored, it can
be read directly from the outputs of QA to QD. The DATA has been converted from a Serial
Data to a Parallel Data.

Initially if all the flip-flops (FFA to FFD) are

RESET (using CLEAR input), then all the
outputs QA to QD will be at logic level ‘0’
(instead of ‘X’ in the above table).

5.2 Serial-in Serial-out (SISO)

Serial-in serial-out shift register accepts data serially, one after the other on a
single input line and produces the stored information on its output in serial form.
This shift register is very similar to SIPO except where as the data was read directly in
a parallel form from the outputs QA to QD, but in SISO the DATA is allowed to be read
serially from the register. There is only one bit output DATA leaving the shift register at a
time in a serial pattern.
4 – bit Serial in serial out Shift register

CLK Data Input Data Output

0 1 X
1 1 X
2 0 X
3 0 X
4 1 1

This type of shift register also acts as a temporary storage device or as a time delay device,
with the amount of time delay being controlled by the number of stages in the register, 4, 8,
16 etc. by varying the application of the clock pulses.
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5.3 Parallel -in Parallel-out (PIPO)

Parallel-in Parallel-out shift register accepts data in parallel and produces the stored
information on its output in parallel form. Each flipflop accepts its input data at the same time
and once the data are stored, each bit appears on its respective output lines which are
available simultaneously.
Parallel-in parallel-out shift register also act as a temporary storage device or as a time
delay device. The DATA is presented in a parallel format to the parallel input pins D A to DD
and then shifts it to the corresponding output pins QA to QD when the registers are clocked.
4 – bit Parallel in Parallel out Shift register

DATA INPUTS DATA OUTPUTS

CLK
DA DB DC DD QA QB QC QD
0 1 1 1 0 X X X X
1 1 0 1 0 1 1 1 0
2 1 1 0 0 1 0 1 0
3 0 1 1 0 1 1 0 0
4 1 1 1 1 0 1 1 0

5.4 Parallel-in Serial-out (PISO)

Parallel-in serial-out shift register accepts data in parallel and produces the stored
information on its output in serial form. Each flipflop accepts its input data at the same time
and the stored data will be available at the output one after the other in the serial form.
The DATA is applied in parallel form to the parallel input pins D A to DD of the register
and is then read out serially from the last flip flop output Q D, one bit at a time on each clock
cycle.
4 – bit Parallel in serial out Shift register
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Shift/Load DATA INPUTS OUTPUT

CLK
DA DB DC DD QA QB QC QD
0 0 1 1 0 0 X X X X
1 1 1 X X X 1 1 0 0
2 1 0 X X X 1 1 1 0
3 1 0 X X X 0 1 1 1
4 1 0 X X X 0 0 1 1

As this type of shift register converts parallel data into serial data, it can be used to multiplex
many different input lines into a single serial DATA stream which can be sent directly to a
computer or transmitted over communication lines.
5.5 Universal Shift Register
A shift register that can shift left and shift right is called a bidirectional shift
register. If a register has both shifts (shift left and shift right) and parallel load capability then
it is a universal shift register.
OPERATION

6 SHIFT COUNTERS
6.1 RING COUNTER
The ring counter is a circular shift register in which the output of the last flip-flop is
connected to the input of the first flip-flop and the output of the first flip flop is connected to
input of second flip flop and so on. Initially, only the last flip-flops (FF D) is preset with logic
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1 and all the other flip-flops (FFA to FFC) are RESET (using CLEAR input) ie., the initial
value of the register is “0001”.
When the clock pulse is applied, the output of a flipflop will be shifted to the next
flipflop and the last flipflop’s output is shifted to the input of the first flip-flop.
Note: An n-stage Ring counter produces n states, so it may be considered to be a
mod-n counter.
Logic diagram of 4 bit Ring counter:

Logic Table:

CLK QA QB QC QD
0 0 0 0 1 Initial condition
1 1 0 0 0
2 0 1 0 0
3 0 0 1 0
4 0 0 0 1
5 1 0 0 0 Sequence repeats

Waveform of Ring counter

6.2 JOHNSON COUNTER

The Johnson counter is a circular shift register with the complemented output (Q') of
the last flip-flop connected to the input of the first flip-flop. It is also known as Switch-tail
ring counter or twisted ring counter. The output of the first flip flop is connected to input of
second flip flop and so on till the last flipflop. When the clock pulse is applied, the register
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content is shifted once to the right and at the same time the complemented output value of the
last flip-flop is transferred into the first flipflop.
Note: An n-stage Johnson counter will go through a sequence of 2n states.

Logic diagram of 4 bit Johnson counter:

Logic Table:
Clock
QA QB QC QD
Pulse
0 0 0 0 0 Initial condition
1 1 0 0 0
2 1 1 0 0
3 1 1 1 0
4 1 1 1 1
5 0 1 1 1
6 0 0 1 1
7 0 0 0 1
8 0 0 0 0 Sequence repeats

Waveform of Johnson counter