8086 Microprocessor - Detailed Notes

1. Programming with 8086

The 8086 CPU is divided into two units:

 Bus Interface Unit (BIU): Handles instruction fetching, address calculation, and
memory/I/O interfacing.

 Execution Unit (EU): Executes instructions, performs arithmetic/logic, and

controls program flow.

The programming model groups registers into categories :

 General Registers: AX (accumulator), BX (base), CX (counter), DX (data). Each can

be split into 8-bit halves (AH/AL, BH/BL, etc.).

 Pointer & Index Registers: SP (stack pointer), BP (base pointer), SI (source index),
DI (destination index). Used for addressing and stack operations.

 Segment Registers: CS (code segment), DS (data segment), SS (stack segment), ES

(extra segment). Each holds a 16-bit base address of a 64KB memory block.

 Instruction Pointer (IP): Holds the offset (logical address) of the next instruction
in the code segment.

 Flags Register: Contains status and control flags (CF, ZF, SF, OF, etc.).

2. Physical Address, Segment Address, Logical Address/Offset

 The 8086 has a 20-bit address bus → 1 MB memory.

 Each segment register holds a 16-bit base, shifted left by 4 bits (multiplied by 16).

 A physical address = Segment × 10H + Offset

 Example: If DS = 3000H and offset = 0020H,

→ Physical Address = 3000 × 10H + 0020H = 30000H + 20H = 30020H.

3. Addressing Modes

8086 supports 9 addressing modes :

 1. Immediate – Operand is part of instruction (e.g., MOV AX, 1234H).

2. Register – Operand is a register (e.g., MOV BX, AX).

3. Direct – Address is given directly (e.g., MOV AX, [1000H]).

4. Register Indirect – Address from BX, BP, SI, or DI (e.g., MOV AX, [BX]).

5. Based – Uses BX/BP + displacement.

6. Indexed – Uses SI/DI + displacement.

7. Based-Indexed – Combines BX/BP + SI/DI.

8. Based-Indexed with Displacement – Adds displacement.

9. String Addressing – Uses DS:SI and ES:DI for string instructions (MOVSB, CMPSB).

4. Instruction Codes & Default Segment Assignment

 Instructions are encoded into binary (opcodes + operands). The 8086 supports
~4000 instruction forms .

 Default segment use depends on operand :

o Instruction fetch → CS:IP

o Stack operations (SP, BP) → SS

o Data (BX, SI, DI) → DS

o String destination → ES

A segment override prefix (CS:, DS:, ES:, SS:) can change the default .

5. Instruction Groups

8086 instructions are grouped :

1. Data Transfer – MOV, PUSH, POP, XCHG, IN, OUT, XLAT.

2. Arithmetic – ADD, SUB, MUL, DIV, INC, DEC, CMP, NEG.

3. Logical – AND, OR, XOR, NOT, TEST.

4. String Instructions – MOVS, CMPS, SCAS, LODS, STOS.

 5. Transfer of Control – JMP, CALL, RET, LOOP, conditional jumps .

6. Processor Control – STC, CLC, CLI, STI, HLT, NOP .

6. Flags

Flags indicate results of operations :

 Status Flags: CF (carry), ZF (zero), SF (sign), OF (overflow), PF (parity), AF

(auxiliary carry).

 Control Flags: DF (direction), IF (interrupt enable), TF (trap).

Example: After ADD AL, BL,

 ZF = 1 if result is zero.

 CF = 1 if carry generated.

7. Prefixes

Prefixes modify instruction behavior :

1. Segment Override Prefixes: CS:, DS:, ES:, SS: (force alternate segment use).

2. Repeat Prefixes: REP, REPE/REPZ, REPNE/REPNZ (used with string instructions).

3. Lock Prefix: Ensures exclusive bus use for atomic operations (e.g., LOCK XCHG).

2. Assembly Language Programming of 8086

1. Introduction

The 8086 microprocessor executes instructions written in machine language (binary

codes). However, programming directly in binary is difficult and error-prone. To simplify
this, Intel introduced assembly language programming, where instructions are written in
mnemonics (easy-to-remember symbols) instead of binary.

Example:

 Machine code: 10111000 00000101

 Assembly: MOV AX, 05H

Assemblers like MASM (Microsoft Macro Assembler) or TASM translate the assembly
program into machine code (object code) that can be executed by the CPU.

2. Structure of an Assembly Language Program

A typical 8086 assembly program has four main parts:

1. Data Segment (DS): Defines variables, constants, and storage locations.

DATA_SEG SEGMENT

NUM1 DB 25H

NUM2 DB 30H

SUM DB ?

DATA_SEG ENDS

2. Code Segment (CS): Contains executable instructions.

CODE_SEG SEGMENT

ASSUME CS:CODE_SEG, DS:DATA_SEG

START: MOV AX, DATA_SEG

MOV DS, AX

; program instructions

MOV AH, 4CH

INT 21H

CODE_SEG ENDS

END START

3. Stack Segment (SS): Defines stack memory for temporary storage.

STACK_SEG SEGMENT

DW 128 DUP(0)

STACK_SEG ENDS

4. Extra Segment (ES): Optional segment for string operations.

3. Steps in Writing an 8086 Program

1. Problem Definition – Define what needs to be solved.

2. Algorithm – Break the problem into logical steps.

3. Flowchart – Diagrammatic representation of program flow (optional).

4. Coding – Write in 8086 mnemonics with proper syntax.

5. Assembling & Linking – Convert to object code (using MASM/TASM).

6. Execution & Debugging – Run the program and correct errors.

4. Instruction Syntax

General format:

LABEL: MNEMONIC OPERAND1, OPERAND2 ; COMMENT

 LABEL – Optional name for a line.

 MNEMONIC – Instruction (e.g., MOV, ADD, JMP).

 OPERANDS – Data items (registers, memory locations, constants).

 COMMENTS – Explanation for readability.

Example:

START: MOV AX, [2000H] ; Load AX with memory content at 2000H

5. Example Programs

(i) Addition of Two 8-bit Numbers

DATA_SEG SEGMENT

NUM1 DB 25H

NUM2 DB 15H

SUM DB ?

DATA_SEG ENDS

CODE_SEG SEGMENT
 ASSUME CS:CODE_SEG, DS:DATA_SEG

START:

MOV AX, DATA_SEG

MOV DS, AX

MOV AL, NUM1

ADD AL, NUM2

MOV SUM, AL

MOV AH, 4CH

INT 21H

CODE_SEG ENDS

END START

👉 This adds 25H + 15H and stores result in SUM.

(ii) Factorial of a Number

DATA_SEG SEGMENT

NUM DB 05H

FACT DW 1

DATA_SEG ENDS

CODE_SEG SEGMENT

ASSUME CS:CODE_SEG, DS:DATA_SEG

START:

MOV AX, DATA_SEG

MOV DS, AX

MOV CX, NUM

MOV AX, 1

FACTORIAL_LOOP:
 MUL CX

LOOP FACTORIAL_LOOP

MOV FACT, AX

MOV AH, 4CH

INT 21H

CODE_SEG ENDS

END START

6. Features of 8086 Assembly Language Programming

 Low-Level Control: Direct access to hardware (ports, memory, registers).

 Efficiency: Programs are compact and fast.

 Segmented Memory: Programs use CS, DS, SS, ES for organized memory
management.

 Direct Hardware Interface: Useful in embedded and system-level applications.

7. Advantages & Disadvantages

Advantages:

 Precise control of hardware.

 Faster execution compared to high-level languages.

 Small memory footprint.

Disadvantages:

 Complex and time-consuming.

 Not portable across different processors.

 Difficult to debug large programs.

3. I/O Interfacing

I/O Interfacing in 8086

1. Introduction to I/O Interfacing

The 8086 microprocessor communicates with the outside world (keyboard, printer,
display, sensors, etc.) through Input/Output (I/O) ports. Since the CPU can only access
memory or I/O, special interfacing techniques are required.

There are two primary methods of I/O addressing in 8086:

1. I/O Mapped I/O (Isolated I/O)

2. Memory Mapped I/O

2. I/O Mapped I/O (Isolated I/O)

 In this method, I/O devices are assigned unique 8-bit or 16-bit port addresses.

 CPU uses special instructions IN and OUT for data transfer.

 Control signals /IOWR (I/O Write) and /IORD (I/O Read) are activated.

 Address range: 00H to FFFFH (64K ports possible), but usually only lower 256
ports (00H–FFH) are used.

Example:

MOV DX, 05H ; Port address

IN AL, DX ; Input from port 05H into AL

OUT DX, AL ; Output AL to port 05H

✅ Used where dedicated I/O instructions and separate address space are preferred.

3. Memory Mapped I/O

 In this method, I/O devices are treated as memory locations.

 No special I/O instructions → CPU uses MOV, AND, OR etc. for data transfer.

 Control signals /MEMR (Memory Read) and /MEMW (Memory Write) are activated.

 Address space is shared with memory (1 MB).

Example:

MOV AX, [2000H] ; Read from I/O device mapped at 2000H

MOV [2000H], AX ; Write to I/O device mapped at 2000H

✅ Useful for systems with few memory chips and direct arithmetic operations on I/O
data.

4. IN and OUT Instructions

 IN instruction: Reads data from an input port into the accumulator.

o IN AL, 08H → Reads from 8-bit port 08H.

o IN AX, DX → Reads from 16-bit port whose address is in DX.

 OUT instruction: Sends data from accumulator to an output port.

o OUT 0AH, AL → Sends AL to port 0AH.

o OUT DX, AX → Sends AX to port at address in DX.

⚡ Note: IN/OUT only work in I/O mapped I/O mode.

5. Interfacing an 8-bit Input Port (I/O Mapped I/O Mode)

To connect an 8-bit input device (e.g., DIP switch or keyboard row):

1. Connect the device to data bus (D0–D7) via a buffer (like 74LS244).

2. Use an I/O address decoder to generate a unique address for the device.

3. Connect /IORD control signal to enable input transfer.

4. CPU executes IN AL, port to read the device data.

Operation:

 CPU places port address on address bus.

 Decoder selects input port.

 /IORD goes low → data is transferred to CPU via data bus.

6. Interfacing an 8-bit Output Port (I/O Mapped I/O Mode)

To connect an 8-bit output device (e.g., LEDs, display):

1. Connect device to data bus via latch (like 74LS373).

2. Decoder provides chip select for port address.

3. Connect /IOWR control signal.

4. CPU executes OUT port, AL to write data to device.

Operation:

 CPU puts port address on address bus.

 Decoder selects output port.

 /IOWR goes low → data from accumulator is latched and sent to device.

7. Disadvantages of Memory Mapped I/O in Multitasking Microcomputer

While memory mapped I/O seems flexible, it has serious drawbacks in multitasking
systems:

1. Reduced Memory Space – Since I/O shares memory address space, part of RAM is
lost for I/O devices. In 8086 (1 MB memory), memory mapped I/O reduces available
user/program memory.

2. Complexity in OS Design – Multitasking operating systems (like those running

multiple processes) require strict separation of memory and I/O. Memory mapped
I/O makes memory protection and allocation more complex.

3. Extra Address Decoding – Full memory decoding (20-bit) is required, which

increases hardware complexity.

4. Performance Overhead – Because normal memory instructions (MOV, ADD, etc.)

are used, bus contention between memory and I/O devices increases.

5. Security Issues – In multitasking, one process may accidentally overwrite I/O

device registers if memory protection is weak.

✅ That’s why most multitasking systems (like PCs with 8086/8088) preferred I/O mapped
I/O.

📌 Summary
  I/O Mapped I/O: Separate I/O space, uses IN/OUT, easy decoding, safe for
multitasking.

 Memory Mapped I/O: Treated as memory, uses normal MOV instructions, flexible
but reduces memory space.

 IN/OUT instructions are only for I/O mapped I/O.

 Interfacing 8-bit ports requires decoders, buffers/latches, and control signals

(/IORD, /IOWR).

 Disadvantage of memory mapped I/O: Less memory, complex OS design,

unsuitable for multitasking.

4. Design of Microcomputer (8086 Based)

1. Von Neumann’s Principle

 A computer consists of CPU, memory, and I/O connected by common buses.

 Stored program concept: Instructions and data both stored in same memory.

 Operates on fetch–decode–execute cycle.

2. 8086 Architecture

 20-bit address bus → 1 MB memory space.

 Data bus: 16-bit (8086), 8-bit (8088).

 Divided into:

o Bus Interface Unit (BIU): Address calculation, instruction fetching, queue

(6-byte).

o Execution Unit (EU): Executes instructions, ALU, control, registers.

 Registers: General (AX, BX, CX, DX), Segment (CS, DS, SS, ES), Pointers (SP, BP, SI,
DI), Flags.

3. Advantages of Pipelining and Segmentation

 Pipelining: BIU fetches next instruction while EU executes → improves speed.

 Segmentation: Memory divided into code, data, stack, extra → supports modular
programs, relocation, 64 KB per segment.
4. Simultaneity and Concurrency

 Simultaneity: Parallel fetching and execution (due to BIU & EU).

 Concurrency: Overlapping of multiple tasks → better CPU utilization.

5. Demultiplexing of Address and Data Bus

 AD0–AD15 are multiplexed → carry address during T1 and data during T2–T4.

 ALE (Address Latch Enable): Signal to latch address into 74LS373 latch.

 Provides separate stable address and data lines.

6. Even and Odd Bank, BHE (Bus High Enable)

 8086 is 16-bit; memory is organized in two 8-bit banks.

o Even bank → lower byte (D0–D7).

o Odd bank → higher byte (D8–D15).

 BHE (Bus High Enable): Active low signal selects odd bank.

 A0 selects even bank.

 Supports aligned (word at even address) and misaligned accesses.

7. Static Memory Organisation

 Uses SRAM/ROM with address, data, and control signals.

 Memory divided into segments for code, data, stack.

 Chip Select (CS) generated using address decoder.

8. Design of Memory Map

 Assign memory addresses to RAM, ROM, and I/O.

 Example:
 o ROM (F0000H–FFFFFH) → stores bootstrap loader.

o RAM (00000H–7FFFFH) → user programs and data.

 Map ensures no overlap of devices.

9. Interfacing Static Memory to 8086

 Connect memory chip’s address lines to A0–A19.

 Data bus connected to D0–D15.

 Control signals: /RD, /WR, /M/IO.

 Use decoders (74LS138) for chip select.

10. Reset in and Power-on Reset Circuit

 RESET pin → clears IP, loads CS = FFFFH, IP = 0000H. CPU starts at FFFF0H.

 Power-on reset: RC network + Schmitt trigger generates reset pulse.

11. Bus Cycle

 One bus cycle = 4 T-states (T1–T4).

 T1: Address output, ALE high.

 T2: Data transfer, control signals active.

 T3, T4: Wait or idle states.

12. Instruction Cycle

 Sequence of fetch, decode, and execute.

 BIU fetches instruction → EU decodes → executes.

 Prefetch queue improves throughput.

13. Organising Program for BIOS / Bootstrap Loader after Reset

  After reset, CS = FFFFH, IP = 0000H → physical address FFFF0H.

 Control jumps to ROM containing BIOS or bootstrap loader.

 Bootstrap loads OS or monitor program from secondary storage to RAM.

14. Clock Input, 8284 Clock Driver

 8086 requires clock (CLK), reset, and ready signals.

 8284 Clock Generator: Provides clock, reset synchronization, and READY

synchronization.

 Inputs: crystal oscillator.

 Outputs: CLK, RESET, READY.

15. Minimum Mode CPU Module

 Used in single-processor systems.

 8086 directly provides control signals:

o /RD, /WR, /M/IO, ALE, DT/R, DEN.

 No external bus controller required.

 Modules: CPU, clock generator (8284), latch (74LS373), transceivers (8286),

memory, I/O ports.

📌 Summary (One-liner Points for Revision)

 Von Neumann: Stored program, common bus.

 8086 Architecture: BIU + EU, registers, 1 MB memory.

 Pipelining/Segmentation: Faster, modular.

 Concurrency: Parallel fetch & execute.

 Demux + ALE: Separate address/data.

 Even/Odd Banks, BHE: 16-bit memory access.

 Memory Organisation: RAM/ROM mapped, chip select.

 Memory Map: Defines address allocation.

 Interfacing: Address, data, control signals with decoders.

 Reset: Starts at FFFF0H.

 Bus Cycle: T1–T4.

 Instruction Cycle: Fetch–decode–execute.

 BIOS/Boot: Loaded from ROM after reset.

 8284: Clock, reset, ready.

 Minimum Mode: Single processor, direct control signals.