EC8691 MICROPROCESSOR AND MICROCONTROLLER LTPC 3003

OBJECTIVES:

The student should be made to:

➢ Study the Architecture of 8086 microprocessor.
➢ Learn the design aspects of I/O and Memory Interfacing circuits.
➢ Study about communication and bus interfacing.
➢ Study the Architecture of 8051 microcontroller.
UNIT I THE 8086 MICROPROCESSOR 9
Introduction to 8086 – Microprocessor architecture – Addressing modes - Instruction set and
assembler directives – Assembly language programming – Modular Programming - Linking and
Relocation – Stacks - Procedures – Macros – Interrupts and interrupt service routines – Byte and
String Manipulation.
UNIT II 8086 SYSTEM BUS STRUCTURE 9
8086 signals – Basic configurations – System bus timing –System design using 8086 – IO
programming – Introduction to Multiprogramming – System Bus Structure –
Multiprocessor configurations – Coprocessor, Closely coupled and loosely Coupled
configurations
– Introduction to advanced processors.
UNIT III I/O INTERFACING
9
Memory Interfacing and I/O interfacing - Parallel communication interface – Serial
communication interface – D/A and A/D Interface - Timer – Keyboard /display controller –
Interrupt controller – DMA controller – Programming and applications Case studies: Traffic Light
control, LED display , LCD display, Keyboard display interface and Alarm Controller.
UNIT IV MICROCONTROLLER 9
Architecture of 8051 – Special Function Registers(SFRs) - I/O Pins Ports and Circuits - Instruction
set - Addressing modes - Assembly language programming.

UNIT V INTERFACING MICROCONTROLLER 9

Programming 8051 Timers - Serial Port Programming - Interrupts Programming – LCD &
Keyboard Interfacing - ADC, DAC & Sensor Interfacing - External Memory Interface- Stepper
Motor and Waveform generation, generation- Comparison of Microprocessor, Microcontroller,
PIC and ARM processors
OUTCOMES:
At the end of the course, the student should be able to:
➢ Design and implement programs on 8086 microprocessor.
➢ Design I/O circuits.
➢ Design Memory Interfacing circuits.
➢ Design and implement 8051 microcontroller based systems.
TEXT BOOKS:
1.Yu-Cheng Liu, Glenn A.Gibson, “Microcomputer Systems: The 8086 / 8088 Family -
Architecture, Programming and Design”, Second Edition, Prentice Hall of India, 2007
2. Mohamed Ali Mazidi, Janice Gillispie Mazidi, Rolin McKinlay, “The 8051 Microcontroller
and Embedded Systems: Using Assembly and C”, Second Edition, Pearson Education, 2011

REFERENCE:
1. Doughlas V.Hall, “Microprocessors and Interfacing, Programming and Hardware:,TMH, 2012

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 UNIT – I
THE 8086 MICROPROCESSOR
1.1 INTRODUCTION

What is a microprocessor?
A microprocessor is a computer processor which incorporates the functions of a computer's
central processing unit (CPU) on a single integrated circuit (IC), or at most a few integrated
circuits. The microprocessor is a multipurpose, clock driven, register based, programmable
electronic device which accepts digital or binary data as input, processes it according to
instructions stored in its memory, and provides results as output. Microprocessors contain both
combinational logic and sequential digital logic.
• Microprocessors operate on numbers and symbols represented in the binary numeral system
Microprocessor is the controlling unit or CPU of a micro-computer, fabricated on a very
small chip capable or performing ALU operations and communicating with the external
word connected to it. It forms a micro-computer when combined with memory and
Input/output devices.
• Microprocessors of different word size with varying decrease of capabilities are available.
Microprocessor comprises of all the functional components of the central processing unit of
a general purpose computer. In other words , functionally it is equivalent to a CPU.
• Cost : The most important characteristics of a microcomputer is its low cost. Because of the
widespread use of microprocessors, the volume of production is very high. That is why,
microprocessor chips are available at fairly low prices.
• Size : The second important features of a microprocessor is its small size. As a result of
improvement in fabrication technology, VLSI, electronic circuitry has become so dense that
a minute silicon chip can contain hundred and thousands of transistors constituting the
microprocessor. Its size does not exceed a few inches on any side , even in the packaged
form.
• Power Consumption: The another important characteristics is its low power consumption
microprocessors are normally manufactured by Metal-Oxide semiconductor technology.
• Versatility: The versatility of a microprocessor results from its stored program mode of
operation. Keeping the same basic hardware , a microprocessor-based system can be
configured for a number of applications simplify altering the software program. This also
makes it very flexible.
• Reliability: Another important property of VLSI devices which has also been in herniated
by microprocessors is extreme reliability . It has been established that the failure rate of an
IC is fairly uniform at the package level, regardless of its complexity.

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History of Microprocessor

Evolution of microprocessor can be viewed as five kinds of generation.

First Generation: 4-bit Microprocessors
• The first microprocessor was introduced in 1971 by Intel Corp. It was named Intel 4004 as it
was a 4 bit processor.
• It was a processor on a single chip.
• It could perform simple arithmetic and logic operations such as addition, subtraction,
boolean AND and boolean OR.
• It had a control unit capable of performing control functions like fetching an instruction
from memory, decoding it, and generating control pulses to execute it.
• It was able to operate on 4 bits of data at a time.
• Intel introduced the enhanced version of 4004, the 4040. Some other 4 bit processors are
International’s PPS4 and Thoshiba’s T3472.
Second Generation :8-bit Microprocessors
• The first 8 bit microprocessor which could perform arithmetic and logic operations on 8 bit
words was introduced in 1973 again by Intel.
• This was Intel 8008 and was later followed by an improved version, Intel 8088 ids more
powerful and faster 8 bit NMOS microprocessor.
• Some other 8 bit processors are Zilog-80 and Motorola M6800.
Third Generation:16-bit Microprocessors
• The 8-bit processors were followed by 16 bit processors. They are Intel 8086 and 80286.
• Some other 16 bit processors are Zilog-z8000 and Motorola M68000,68010.
Fourth Generation: 32-bit Microprocessors
• The 32 bit microprocessors were introduced by several companies but the most popular one
is Intel 80386,Intel 386,
• Some other 32 bit processors arePentium pro,Pentium with MMX,Pentium II
• Motorola,IBM and Apple jointly developed 32-bit RISC processors Power pc 601,603,604
and 620.
Fifth Generation: 64-bit Microprocessors
• The 64 bit microprocessors were introduced by several companies but the most popular is
Intel i860 -64 bit RISC processor.
• Some other 32 bit processors are SUN’s SPARC and ULTRASPARC, Power PC 620,Alpha
21064

.
Table 1.1 History of processor

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1.2 Microprocessor Architecture:
The 8086 CPU is divided into two independent functional parts,
the Bus interface unit (BIU)
and execution unit (EU).
The Bus Interface Unit contains
• Bus Interface Logic,
• Segment registers,
• Memory addressing logic
• Six byte instruction object code queue.
1. The BIU Sends Out Address,
2. Fetches The Instructions From Memory,
3. Read Data From Ports And Memory, And
4. Writes The Data To Ports And Memory.
The execution unit: contains
• The Data And Address Registers,
• The Arithmetic And Logic Unit,
• The Control Unit And Flags.
1. The control circuitry which directs internal operations.
2. A decoder in the EU translates instructions fetched from memory into a series of actions
which the EU carries out.
3. The EU is has a 16-bit ALU which can add, subtract, AND,OR, XOR, increment,
decrement, complement or shift binary numbers.
4. The EU is decoding an instruction or executing an instruction which does not require use of
the buses.
In other words the BIU handles all transfers of data and addresses on the buses for the execution
unit.
The Queue: The BIU fetches up to 6 instruction bytes for the following instructions. The BIU
stores these prefetched bytes in first-in-first-out register set called a queue. When the EU is ready
for its next instruction it simply reads the instruction byte(s) for the instruction from the queue in
the BIU. This is much faster than sending out an address to the system memory and waiting for
memory to send back the next instruction byte or bytes.

Fig.1.2 8086 Architecture

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Word Read: Each of 1 MB memory address of 8086 represents a byte wide location.16-bit
words will be stored in two consecutive memory locations. If first byte of the data is stored at
an even address, 8086 can read the entire word in one operation.
For example if the 16 bit data is stored at even address 00520H is 9634H
MOV BX, [00520H]
8086 reads the first byte and stores the data in BL and reads the 2nd byte and stores the data in
BH
BL= (00520H) i.e. BL=34H BH= (00521H) BH=96H
If the first byte of the data is stored at an odd address, 8086 needs two operations to read the
16 bit data.
For example if the 16 bit data is stored at even address 00521H is 3897H MOV BX, [00521H] In
first operation, 8086 reads the 16 bit data from the 00520H location and stores the data of
00521H location in register BL and discards the data of 00520H location In 2nd operation,
8086 reads the 16 bit data from the 00522H location and stores the data of
00522H location in register BH and discards the data of 00523H location.
BL= (00521H) i.e. BL=97H BH= (00522H) BH=38H

ByteRead: MOV BH, [Addr]

For Even Address:
Ex: MOV BH, [00520H]
8086 reads the first byte from 00520 location and stores the data in BH and reads the
2nd byte from the 00521H location and ignores it BH [ 00520H]
For Odd Address MOV BH, [Addr]
Ex: MOV BH, [00521H]
8086 reads the first byte from 00520H location and ignores it and reads the 2nd byte from
the 00521 location and stores the data in BH
BH = [00521H]

Physical address formation:Generation of 20 bit Address

The 8086 addresses a segmented memory. The complete physical address which is 20- bits long
is generated using segment and offset registers each of the size 16-bit.The content of a segment
register also called as segment address, and content of an offset register also called as offset
address. To get total physical address, put the lower nibble
0H to segment address and add offset address.
The content of segment register are multiplied by 10H.I.E shifted by 4 positions to the left
by inserting 4 zero bits and then the offset.i.e the contents of IP register are added to the
shifted contents of CS to generate physical address.
The fig 1.3 shows formation of 20-bit physical address.

Fig 1.3 Physical Address formation

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 The contents of CS register are 348AH, therefore the shifted contents of CS register are 348A0H.
When the BIU adds the offset of 4214H in IP to this starting address, we get 38AB4H as a 20-bit
physical address of memory.

Register organization of 8086:

All the registers of 8086 are 16-bit registers. The general purpose registers, can be used either 8-
bit registers or 16-bit registers used for holding the data, variables and intermediate results
temporarily or for other purpose like counter or for storing offset address for some particular
addressing modes etc. The special purpose registers are used as segment registers, pointers, index
registers or as offset storage registers for particular addressing modes. Fig 1.3

Fig 1.4 Register organization of 8086

AX Register: Accumulator register consists of two 8-bit registers AL and AH, which can be
combined together and used as a 16- bit register AX. AL in this case contains the low-order byte
of the word, and AH contains the high-order byte. Accumulator can be used for I/O operations,
rotate and string manipulation.
BX Register: This register is mainly used as a base register. It holds the starting base location of
a memory region within a data segment. It is used as offset storage for forming physical address
in case of certain addressing mode.
CX Register: It is used as default counter - count register in case of string and loop instructions.
DX Register: Data register can be used as a port number in I/O operations and implicit operand
or destination in case of few instructions. In integer 32-bit multiply and divide instruction the DX
register contains high-order word of the initial or resulting number.
Segment registers:
1Mbyte memory is divided into 16 logical segments. The complete 1Mbyte memory
segmentation is as shown in fig 1.4. Each segment contains 64Kbyte of memory. There are four
segment registers.
Code segment: (CS) is a 16-bit register containing address of 64 KB segment with processor
instructions. The processor uses CS segment for all accesses to instructions referenced by
instruction pointer (IP) register. CS register cannot be changed directly.

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 The CS register is automatically updated during far jump, far call and far return instructions. It is
used for addressing a memory location in the code segment of the memory, where the executable
program is stored.
Stack segment (SS) is a 16-bit register containing address of 64KB segment with program stack.
By default, the processor assumes that all data referenced by the stack pointer (SP) and base
pointer (BP) registers is located in the stack segment. SS register can be changed directly using
POP instruction. It is used for addressing stack segment of memory. The stack segment is that
segment of memory, which is used to store stack data.
Data segment (DS) is a 16-bit register containing address of 64KB segment with program data.
By default, the processor assumes that all data referenced by general registers (AX, BX, CX,
DX) and index register (SI, DI) is located in the data segment. DS register can be changed
directly using POP and LDS instructions. It points to the data segment memory where the data is
resided.
Extra segment (ES) is a 16-bit register containing address of 64KB segment, usually with
program data. By default, the processor assumes that the DI register references the ES segment
in string manipulation instructions. ES register can be changed directly using POP and LES
instructions. It also refers to segment which essentially is another data segment of the memory. It
also contains data.
Pointers and index registers.
The pointers contain within the particular segments. The pointers IP, BP, SP usually contain
offsets within the code, data and stack segments respectively
Stack Pointer (SP) is a 16-bit register pointing to program stack in stack segment.
Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP register is usually
used for based, based indexed or register indirect addressing.
Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register indirect
addressing, as well as a source data addresses in string manipulation instructions. Destination
Index (DI) is a 16-bit register. DI is used for indexed, based indexed and register indirect
addressing, as well as a destination data address in string manipulation instructions.
Flag Register:

Fig. 1.6 Flag Register

Flags Register determines the current state of the processor. They are modified automatically by
CPU after mathematical operations, this allows to determine the type of the result, and to
determine conditions to transfer control to other parts of the program. The 8086 flag register as
shown in the fig 1.5. 8086 has 9 active flags and they are divided into two categories:
1. Conditional Flags
2. Control Flags
Conditional Flags
Carry Flag (CY): This flag indicates an overflow condition for unsigned integer arithmetic. It is
also used in multiple-precision arithmetic.
Auxiliary Flag (AC): If an operation performed in ALU generates a carry/barrow from lower
nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7), the AC flag is set i.e. carry given by D3

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 bit to D4 is AC flag. This is not a general-purpose flag, it is used internally by the Processor to
perform Binary to BCD conversion.
Parity Flag (PF): This flag is used to indicate the parity of result. If lower order 8-bits of the
result contains even number of 1’s, the Parity Flag is set and for odd number of 1’s, the Parity
flag is reset.
Zero Flag (ZF): It is set; if the result of arithmetic or logical operation is zero else it is reset.
Sign Flag (SF): In sign magnitude format the sign of number is indicated by MSB bit. If the
result of operation is negative, sign flag is set.
Control Flags
Control flags are set or reset deliberately to control the operations of the execution unit.
Control flags are as follows:
Trap Flag (TF): It is used for single step control. It allows user to execute one instruction of a
program at a time for debugging. When trap flag is set, program can be run in single step mode.
Interrupt Flag (IF): It is an interrupt enable/disable flag. If it is set, the maskable interrupt of
8086 is enabled and if it is reset, the interrupt is disabled. It can be set by executing instruction
sit and can be cleared by executing CLI instruction.
Direction Flag (DF): It is used in string operation. If it is set, string bytes are accessed from
higher memory address to lower memory address. When it is reset, the string bytes are accessed
from lower memory address to higher memory address.

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1.3 INSTRUCTION SET OF 8086
The 8086 instructions are categorized into the following main types.
1. Data Copy / Transfer Instructions
2. Arithmetic and Logical Instructions
3. Shift and Rotate Instructions
4. Loop Instructions
5. Branch Instructions
6. String Instructions
7. Flag Manipulation Instructions
8. Machine Control Instructions
1.3.1 Data Copy / Transfer Instructions:
The data transfer instructions move data between memory and the general-purpose
and segment registers, and perform operations such as conditional moves, stack
access, and data conversion.
There are four basic 8086 instruction for transferring quantities to and/or from the
registers and memory such as,
• General purpose data transfer instructions
• I/O transfer instruction
• Special address transfer instruction
• Flag transfer instruction
General purpose data transfer instructions
• MOV
• PUSH
• POP
• XCHG
• XLAT
MOV:
This instruction copies a word or a byte of data from some source to a destination.
The destination can be a register or a memory location. The source can be a register, a memory
location, or an immediate number.
Syntax:
MOV destination,source
Depending on the addressing modes it can transfer information from
S.No Type of Transfer Instruction Description
1. Register to register MOV AX,BX MOV r1, r2
(Move Data; Move the content of
the one register to another).
[r1] <-- [r2]
2. Immediate operand to MOV AX,5000H MOV r, data.
a register (Move immediate data to register).
[r] <-- data.
3. Immediate operand to MOV [8010H],5000H MOV M, data.
a memory location (Move immediate data to memory).
M <-- data.
4. Memory location to MOV AX,[8010H] MOV r, m
register (Move the content of memory
register).
r <-- [M]
5. Register to Memory MOV [8010H],AX MOV M, r.
location (Move the content of register to
memory).
M <-- [r]

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 6. MOV sr, r.
Register to segment (Move the content of register to
MOV [BX],AX
register(except CS) segemnt register).
[sr] <-- [r]
7. segment register to MOV AX,[BX] MOV sr, m.
Register (Move the content of segemnt
register to register).
[r] <-- [sr]
8. Memory to segment MOV [BX],[8010H] MOV sr, m.
register(except CS) (Move the content of memory to
segemnt register ).
[sr] <-- [M]
9. segment register to MOV [8010H],[BX] MOV sr, m.
Memory (Move the content of segemnt
register to memory).
[M] <-- [sr]

Direct loading of the segment registers with immediate data is not permitted.
PUSH: Push to Stack
This instruction pushes the contents of the specified register/memory location on to the stack. The
stack pointer is decremented by 2, after each execution of the instruction
E.g. PUSH AX
PUSH DS
PUSH [5000H]
POP: Pop from Stack
This instruction when executed, loads the specified register/memory location with the contents
of the memory location of which the address is formed using the current stack segment and stack
pointer.
The stack pointer is incremented by 2
Eg. POP AX POP DS
POP [5000H]
XCHG: Exchange byte or word
This instruction exchange the contents of the specified source and destination operands
Eg. XCHG [5000H], AX
XCHG BX, AX
XLAT:Translate
Translate byte using look-up table
Eg. LEA BX, TABLE1
MOV AL, 04H
XLAT
1.3.2 Input and output port transfer instructions:

These instruction are used to move data between accumulator and I/O port using fixed port
addressing and variable port addressing.
IN:Input the port
Copy a byte or word from specified port to accumulator.
Eg. IN AL,03H
IN AX,DX

OUT:Output to the port

Copy a byte or word from accumulator specified port.
Eg. OUT 03H

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1.3.3 Special Address Transfer instructions
LEA:Load Effective Address
Load effective address of the operand into specified register
Eg: LEA BX,ADR :effective address of label ADR
LDS: Load DS register and other specified register from memory.
Eg. LDS BX,5000H
LES: Load ES register and other specified register from memory.
Eg. LES BX,5000H
1.3.4 Flag transfer instructions:
LAHF:
Load (copy to) AH with the low byte the flag register. [AH] [ Flags low byte]
SAHF:
Store (copy) AH registers to low byte of flag register. [Flags low byte] [AH]
PUSHF:
Copy flag register to top of stack.
POPF:
Copy word at top of stack to flag register.
1.3.5 Arithmetic Instructions:
The 8086 provides many arithmetic operations: addition, subtraction, negation, increment,
decrement multiplication and comparing two values.
Addition Instruction:
• Add contents of two registers with or without carry
• Add contents of a registers and a memory with or without carry
• Add immediate data to a registers or a memory with or without carry
• Increment the content of a register or a memory location
• To perform ASCII adjustment after addition
• To perform decimal adjustment after addition
ADD:
The add instruction adds the contents of the source operand to the destination operand.
Syntax: ADD oper1,oper2
ADD AX, 0100H Add immediate value to the content of AX
ADD AX, BX Add contents of AX and BX and result in AX
ADD AX, [SI] Add word from memory at offset [SI] in
DS to the content of DX
ADD AX, [5000H] Add content of data whose address is 5000H with AX and
result in AX
ADD [5000H], 0100H Add immediate value to the content of data whose address
is 5000H and result in 5000H

ADC: Add with Carry

This instruction performs the same operation as ADD instruction, but adds the carry flag to
the result.
ADC AX, 0100H Add immediate value plus carry status to the content of AX
ADC AX, BX Add contents of AX and BX plus carry status and result
in AX
ADC AX, [SI] Add word from memory at offset [SI] in
DS plus carry status to the content of
DX
ADC AX, [5000H] Add content of data whose address is 5000H plus carry
status with AX and result in AX
ADC [5000H], 0100H Add immediate value to the content of data whose address
is 5000H plus carry status and result in 5000H

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INC: Increment
• This instruction increases the contents of the specified Register or memory location by
• Immediate data cannot be operand of this instruction.
Eg. INC AX
INC [BX]
INC [5000H]
AAA: ASCII Adjust After Addition
• The AAA instruction is executed after an ADD instruction that add two ASCII coded
operand to give a byte of result in AL.
• The AAA instruction converts the resulting contents of AL to a unpacked decimal
digits.
• After the addition it will check the lower 4 bits of AL is a valid BCD number in the
range of 0 to 9
• If it is between 0 to 9 the AF is zero and AAA sets AH=0
• If lower digit of AL is between 0 to 9 AF is set,06 is added to AL.The upper 4 bits of
AL are cleared and AH is incremented by one
• If lower digit of AL greater than 9 ,then 06 is added to AL. The upper 4 bits of AL are
cleared and AH is incremented by one

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DAA: Decimal Adjust After Addition
• The DAA instruction is executed after an ADD instruction that add two ASCII coded
operand to give a byte of result in AL.
• The DAA instruction converts the resulting contents of AL to a unpacked decimal
digits.
• If lower nibble is greater than 9,after addition it will add 06 to the lower nibble in AL.
• After adding 06 to lower nibble of AL, if upper nibble of AL is greater than 9,then
adds 60H to AL.

Subtraction Instruction:
• Subtract contents of two registers with or without carry
• Subtract contents of a registers and a memory with or without carry
• Subtract immediate data to a registers or a memory with or without carry
• Decrement the content of a register or a memory location
• To perform ASCII adjustment after Subtract
• To perform decimal adjustment after Subtract
SUB: Subtract
The subtract instruction subtracts the source operand from the destination operand and the
result is left in the destination operand.
SUB AX, 0100H Subtract immediate value to the content of AX
SUB AX, BX Subtract contents of AX and BX and result in AX
SUB AX, [SI] Subtract word from memory at offset
[SI] in DS to the content of DX
SUB AX, [5000H] Subtract content of data whose address is 5000H with AX
and result in AX
SUB [5000H], 0100H Subtract immediate value to the content of data whose
address is 5000H and result in 5000H

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SBB: Subtract with Borrow
The subtract with borrow instruction subtracts the source operand and the borrow flag (CF)
which may reflect the result of the previous calculations, from the destination operand
SBB AX, 0100H Subtract immediate value plus carry status to the content of
AX
SBB AX, BX Subtract contents of AX and BX plus carry status and
result in AX
SBB AX, [SI] Subtract word from memory at offset
[SI] in DS plus carry status to the
content of DX
SBB AX, [5000H] Subtract content of data whose address is 5000H plus carry
status with AX and result in AX
SBB [5000H], 0100H Subtract immediate value to the content of data whose
address is 5000H plus carry status and result in 5000H
DEC: Decrement
The decrement instruction subtracts 1 from the contents of the specified register or
memory location.
Eg. DEC AX
DEC [5000H]
AAS: ASCII Adjust After Subtraction
• The AAA instruction is executed after an SUB instruction that subtracts two ASCII
coded operand to give a byte of result in AL.
• The AAA instruction converts the resulting contents of AL to a unpacked decimal
digits.
• After the addition it will check the lower 4 bits of AL is a valid BCD number in the
range of 0 to 9
• If it is between 0 to 9 the AF is zero and AAA sets AH=0
• If lower digit of AL is between 0 to 9 AF is set,06 is subtracted to AL. The upper 4
bits of AL are cleared and AH is incremented by one
• If lower digit of AL greater than 9, then 06 is subtracted to AL. The upper 4 bits of
AL are cleared and AH is incremented by one

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DAS: Decimal Adjust After Subtraction

• The DAA instruction is executed after an SUB instruction that subtract two ASCII
coded operand to give a byte of result in AL.
• The DAA instruction converts the resulting contents of AL to a unpacked decimal
digits.
• If lower nibble is greater than 9, after subtraction it will subtract 06 to the lower
nibble in AL.
• After subtracting 06 to lower nibble of AL, if upper nibble of AL is greater than
9,then subtract 60H to AL.

NEG: Negate
The negate instruction forms 2’s complement of the specified destination in the instruction. The
destination can be a register or a memory location. This instruction can be implemented by
inverting each bit and adding 1 to it.
Eg. NEG AL
AL = 0011 0101 35H
Replace number in AL with its 2’s complement
AL = 1100 1011 = CBH

CMP: Compare
This instruction compares the source operand, which may be a register or an immediate data or
a memory location, with a destination operand that may be a register or a memory location
Eg. CMP BX, 0100H CMP AX, 0100H
CMP [5000H], 0100H CMP BX, [SI]
CMP BX, CX

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Multiplication Instruction:

MUL:Unsigned Multiplication Byte or Word

This instruction multiplies an unsigned byte or word by the contents of AL.
Eg. MUL BH; (AX) (AL) x (BH)
MUL CX; (DX)(AX) (AX) x (CX)
MUL WORD PTR [SI]; (DX)(AX) (AX) x ([SI])
IMUL:Signed Multiplication
This instruction multiplies a signed byte in source operand by a signed byte in AL or a signed
word in source operand by a signed word in AX.
Eg. IMUL BH
IMUL CX
IMUL [SI]
AAM: ASCII Adjust after Multiplication
This instruction, after execution, converts the product available In AL into unpacked
BCD format.
Eg. MOV AL, 04; AL = 04
MOV BL ,09; BL = 09
MUL BL; AX = AL*BL; AX=24H AAM;
AH = 03, AL=06

Division Instruction:

DIV: Unsigned division

This instruction is used to divide an unsigned word by a byte or to divide an unsigned double
word by a word.
Eg. DIV CL; Word in AX / byte in CL; Quotient in AL, remainder in AH
DIV CX; Double word in DX and AX / word; in CX, and Quotient in AX;
remainder in DX
IDIV: Unsigned division
This instruction is used to divide an signed word by a byte or to divide an unsigned double
word by a word.
Eg. IDIV CL; Word in AX / byte in CL; Quotient in AL, remainder in AH
IDIV CX; Double word in DX and AX / word; in CX, and Quotient in AX;
remainder in DX
AAD: ASCII Adjust before Division
This instruction converts two unpacked BCD digits in AH and AL to the equivalent binary
number in AL. This adjustment must be made before dividing the two unpacked BCD digits in
AX by an unpacked BCD byte. In the instruction sequence, this instruction appears before DIV
instruction.
Eg. AX 05 08
AAD result in AL 00 3A 58D = 3A H in AL
The result of AAD execution will give the hexadecimal number 3A in AL and 00 in AH where
3A is the hexadecimal Equivalent of 58 (decimal).
CBW: Convert Signed Byte to Word
This instruction copies the sign of a byte in AL to all the bits in AH. AH is then said to
be sign extension of AL.
Eg. CBW
AX= 0000 0000 1001 1000 Convert signed byte in AL signed word in AX. Result in AX
= 1111 1111 1001 1000
16 Dr.P.Durgadevi,AP/RMKCET
 CWD: Convert Signed Word to Double Word
This instruction copies the sign of a byte in AL to all the bits in AH. AH is then said to
be sign extension of AL.
Eg. CWD
Convert signed word in AX to signed double word in DX: AX DX= 1111 1111 1111 1111
Result in AX = 1111 0000 1100 0001

1.3.5. Logical instructions

AND: Logical AND
This instruction bit by bit ANDs the source operand that may be an immediate register or
a memory location to the destination operand that may a register or a memory location.
The result is stored in the destination operand.

Syntax: AND destination , source

Eg. AND AX, 0008H

AND AX, BX

OR: Logical OR
This instruction bit by bit ORs the source operand that may be an immediate, register or
a memory location to the destination operand that may a register or a memory location. The
result is stored in the destination operand.
Syntax:
OR destination , source

NOT: Logical Invert

This instruction complements the contents of an operand register or a memory location,
bit by bit.
Syntax:
NOT destination

17 Dr.P.Durgadevi,AP/RMKCET
 OR: Logical Exclusive OR
This instruction bit by bit XORs the source operand that may be an immediate, register or a
memory location to the destination operand that may a register or a memory location. The result
is stored in the destination operand.
Syntax:
XOR destination ,source
Eg. XOR AX, 0098H
XOR AX, BX

TEST: Logical Compare Instruction

The TEST instruction performs a bit by bit logical AND operation on the two operands.
The result of this ANDing operation is not available for further use, but flags are affected.
Syntax:
TEST destination ,source
Eg. TEST AX, BX
TEST [0500], 06H
Shift and Rotate Instructions
SAL/SHL:
SAL and SHL are two mnemonics for the same instruction.
• This instruction shifts each bit in the specified destination to the left and 0 is stored at
LSB position.
• The MSB is shifted into the carry flag.
• The destination can be a byte or a word.
• It can be in a register or in a memory location.
• The number of shifts is indicated by count.
Syntax:
SAL / SHL destination, count.

Eg. SAL CX, 1

SHL AX, CL

18 Dr.P.Durgadevi,AP/RMKCET
 SHR: SHR destination, count
This instruction shifts each bit in the specified destination to the right and 0 is stored at
MSB position.
• The LSB is shifted into the carry flag.
• The destination can be a byte or a word.
• It can be a register or in a memory location.
• The number of shifts is indicated by count.
Syntax:
SHR destination, count.

SAR: SAR destination, count

This instruction shifts each bit in the specified destination some number of bit positions
to the right. As a bit is shifted out of the MSB position, a copy of the old MSB is put in the
MSB position. The LSB will be shifted into CF.
Syntax:
SAR destination, count

19 Dr.P.Durgadevi,AP/RMKCET
ROL Instruction: Rotate left without carry

This instruction rotates all bits in a specified byte or word to the left some number of bit
positions. MSB is placed as a new LSB and a new CF.

Syntax: ROL destination, count.

ROR Instruction: Rotate right without carry

This instruction rotates all bits in a specified byte or word to the right some number
of bit positions. LSB is placed as a new MSB and a new CF.
Syntax: ROR destination, count

20 Dr.P.Durgadevi,AP/RMKCET
RCL Instruction: Rotate left with carry
This instruction rotates all bits in a specified byte or word some number of bit positions
to the left along with the carry flag. MSB is placed as a new carry and previous carry is place
as new LSB.
Syntax: RCL destination, count.

RCR Instruction: Rotate right with carry

This instruction rotates all bits in a specified byte or word some number of bit positions to the
right along with the carry flag. LSB is placed as a new carry and previous carry is place as new
MSB.
Syntax: RCR destination, count.

1.3.6.Loop Instructions:

Unconditional LOOP Instructions

➢ LOOP: LOOP Unconditionally
This instruction executes the part of the program from the Label orAddressspecified in the
instruction upto the LOOP instruction CX number of times. At each iteration, CX is
decremented automatically and JUMP IF NOT ZERO structure.
Example: MOV CX, 0004H
Conditional LOOP Instructions
➢ LOOPZ / LOOPE Label
Loop through a sequence of instructions from label while ZF=1 and CX=0.
➢ LOOPNZ / LOOPENE Label
Loop through a sequence of instructions from label while ZF=1 and CX=0.

21 Dr.P.Durgadevi,AP/RMKCET
1.3.7. Branch Instructions:
Branch Instructions transfers the flow of execution of the program to a new Address specified
in the instruction directly or indirectly. When this type of instruction is executed, the CS and IP
registers get loaded with new values of CS and IP corresponding to the location to be transferred.
The Branch Instructions are classified into two types
1. Unconditional Branch Instructions.
2. Conditional Branch Instructions.
Unconditional Branch Instructions:
In Unconditional control transfer instructions, the execution control is transferred to the specified
location independent of any status or condition. The CS and IP are unconditionally modified to
the new CS and IP.
➢ CALL: Unconditional Call
This instruction is used to call a Subroutine (Procedure) from a main program. Address
of procedure may be specified directly or indirectly. There are two types of procedure
depending upon whether it is available in the same segment or in another segment.
i. Near CALL i.e., ±32K displacement.
ii. For CALL i.e., anywhere outside the segment.
On execution this instruction stores the incremented IP & CS onto the stack and loads the
CS & IP registers with segment and offset Addresses of the procedure to be called. RET:
➢ Return from the Procedure.
At the end of the procedure, the RET instruction must be executed. When it is executed,
the previously stored content of IP and CS along with Flags are retrieved into the CS, IP and
Flag registers from the stack and execution of the main program continues further.
➢ INT N: Interrupt Type N.
In the interrupt structure of 8086, 256 interrupts are defined corresponding to the types
from 00H to FFH. When INT N instruction is executed, the type byte N is multiplied by 4
and the contents of IP and CS of the interrupt service routine will be taken from memory
block in 0000 segment.
➢ INTO: Interrupt on Overflow
This instruction is executed, when the overflow flag OF is set. This is equivalent to a
Type 4 Interrupt instruction.
➢ JMP: Unconditional Jump
This instruction unconditionally transfers the control of execution to the specified
Address using an 8-bit or 16-bit displacement. No Flags are affected by this instruction.
➢ IRET: Return from ISR
When it is executed, the values of IP, CS and Flags are retrieved from the stack to
continue the execution of the main program.
Conditional Branch Instructions
When this instruction is executed, execution control is transferred to
theAddressspecified relatively in the instruction, provided the condition implicit in the
Opcode is satisfied. Otherwise execution continues sequentially.
➢ JZ/JE Label
Transfer execution control to Address‘Label’, if ZF=1.
➢ JNZ/JNE Label
Transfer execution control to Address‘Label’, if ZF=0
➢ JS Label
Transfer execution control to Address‘Label’, if SF=1.
➢ JNS Label
Transfer execution control to Address‘Label’, if SF=0.
22 Dr.P.Durgadevi,AP/RMKCET
 ➢ JO Label
Transfer execution control to Address‘Label’, if OF=1.
➢ JNO Label
Transfer execution control to Address‘Label’, if OF=0.
➢ JNP Label
Transfer execution control to Address‘Label’, if PF=0.

➢ JP Label
Transfer execution control to Address‘Label’, if PF=1.
➢ JB Label
Transfer execution control to Address‘Label’, if CF=1.
➢ JNB Label
Transfer execution control to Address‘Label’, if CF=0.
➢ JCXZ Label
Transfer execution control to Address‘Label’, if CX=0
1.3.8. String Manipulation Instructions
A series of data byte or word available in memory at consecutive locations, to be referred as Byte
String or Word String. A String of characters may be located in consecutive memory locations,
where each character may be represented by its ASCII equivalent. The 8086 supports a set of more
powerful instructions for string manipulations for referring to a string, two parameters are required.
I. Starting and EndAddressof the String.
II. II. Length of the String.
The length of the string is usually stored as count in the CX register. The incrementing or
decrementing of the pointer, in string instructions, depends upon the Direction Flag (DF) Status. If
it is a Byte string operation, the index registers are updated by one. On the other hand, if it is a
word string operation, the index registers are updated by two.
REP: Repeat Instruction Prefix
This instruction is used as a prefix to other instructions, the instruction to which the
REP prefix is provided, is executed repeatedly until the CX register becomes zero (at each
iteration CX is automatically decremented by one).
i. REPE / REPZ - repeat operation while equal / zero.
ii.REPNE / REPNZ - repeat operation while not equal / not zero.
These are used for CMPS, SCAS instructions only, as instruction prefixes.
MOVSB / MOVSW: Move String Byte or String Word
Suppose a string of bytes stored in a set of consecutive memory locations is to be moved to
another set of destination locations. The starting byte of source string is located in the memory
location whose Address may be computed using SI (Source Index) and DS (Data Segment)
contents. The starting Address of the destination locations where this string has to be relocated is
given by DI (Destination Index) and ES (Extra Segment) contents.
CMPS: Compare String Byte or String Word
The CMPS instruction can be used to compare two strings of byte or words. The length
of the string must be stored in the register CX. If both the byte or word strings are equal, zero
Flag is set.
The REP instruction Prefix is used to repeat the operation till CX (counter) becomes zero or the
condition specified by the REP Prefix is False.
SCAN: Scan String Byte or String Word
This instruction scans a string of bytes or words for an operand byte or word specified in the
register AL or AX. The String is pointed to by ES: DI register pair. The length of the string

23 Dr.P.Durgadevi,AP/RMKCET
 stored in CX. The DF controls the mode for scanning of the string. Whenever a match to the
specified operand is found in the string, execution stops and the zero Flag is set. If no match is
found, the zero flag is reset.
LODS: Load String Byte or String Word
The LODS instruction loads the AL / AX register by the content of a string pointed to by DS:
SI register pair. The SI is modified automatically depending upon DF, If it is a byte transfer
(LODSB), the SI is modified by one and if it is a word transfer (LODSW), the SI is modified
by two. No other Flags are affected by this instruction.
STOS: Store String Byte or String Word
The STOS instruction Stores the AL / AX register contents to a location in the string pointer
by ES: DI register pair. The DI is modified accordingly, No Flags are affected by this
instruction.
The direction Flag controls the String instruction execution, The source index SI and
Destination Index DI are modified after each iteration automatically. If DF=1, then the
execution follows auto decrement mode, SI and DI are decremented automatically after each
iteration. If DF=0, then the execution follows auto increment mode. In this mode, SI and DI
are incremented automatically after each iteration.
Flag Manipulation and Processor Control Instructions
These instructions control the functioning of the available hardware inside the
processor chip. These instructions are categorized into two types:
1. Flag Manipulation instructions.
2. Machine Control instructions.
1.3.9.Flag Manipulation instructions
The Flag manipulation instructions directly modify some of the Flags of 8086.
i. CLC – Clear Carry Flag.
ii. CMC – Complement Carry Flag. iii. STC – Set Carry Flag.
iv. CLD – Clear Direction Flag. v. STD – Set Direction Flag.
vi. CLI – Clear Interrupt Flag. vii. STI – Set Interrupt Flag.
1.3.10. Machine Control instructions
The Machine control instructions control the bus usage and execution i.
WAIT – Wait for Test input pin to go low. ii. HLT – Halt the process.
iii. NOP – No operation.
iv. ESC – Escape to external device like NDP
v. LOCK – Bus lock instruction prefix.

1.4 ADDRESSING MODES

The set of mechanisms by which an instruction can specify how to obtain its operands is known
as Addressing modes. The Addressing modes of 8086 can be broken into two categories such as,
1. Data related Addressing modes
2. Branch Addressing modes
The CPU can access the operands (data) in a number of different modes The 8086 has 12
Addressing modes can be classified into five groups.
• Addressing modes for accessing immediate and register data (register and immediate
modes).
• Addressing modes for accessing data in memory (memory modes)
• Addressing modes for accessing I/O ports (I/O modes)
• Relative Addressing mode
• Implied Addressing mode
24 Dr.P.Durgadevi,AP/RMKCET
1.Immediate Addressing mode:
In this mode, 8 or 16 bit data can be specified as part of the instruction - OP Code
Immediate Operand
Instruction
Datum

Example 1: MOV CL, 03 H: Moves the 8 bit data 03 H into CL

Example 2: MOV DX, 0525 H:
Moves the 16 bit data 0525 H into DX
In the above two examples, the source operand is in immediate mode and the
destination operand is in register mode.

A constant such as “VALUE” can be defined by the assembler EQUATE directive

such as VALUE EQU 35H
Example: MOV BH, VALUE
Used to load 35 H into BH

2.Register Addressing mode:

The operand to be accessed is specified as residing in an internal register of 8086.
Anyone internal registers can be used as a source or destination operand, however only
the data registers can be accessed as either a byte or word.
Instruction Register
Register Datum

Example 1: MOV DX,CX

MOV DX (Destination Register) , CX (Source Register) Which moves 16 bit content of

CS into DX.
Example 2: MOV CL, DL
Moves 8 bit contents of DL into CL
Example 3: MOV BX, CH is an illegal instruction.
* The register sizes must be the same.

3.Direct Addressing mode:

The instruction Opcode is followed by an affective address, this effective Address is
directly used as the 16 bit offset of the storage location of the operand from the location
specified by the current value in the selected segment register. The default segment is always
DS.The 20 bit physicalAddressof the operand in memory is normally obtained as
PA = DS:EA
Instruction Memory
EA* Datum

The data resides in a memory location in the data segment, whose effective Address may be
computed using 5000H as the offset Address and content of DS as segment address. The
effective address, here, is 10H*DS+5000H.

Example 1: MOV AX, [5000H]

25 Dr.P.Durgadevi,AP/RMKCET
 If DS = 1010H, OFFSET=5000, AX = 1000H then EA=15100H.
DS:BX ➔1010H:5000H
10*H DS➔ 10100
[BX] ➔ + 5000

EA ➔ 12100H
Example 2:
MOV CH, START
If [DS] = 3050 and START = 0040
8 bit content of memory location 30540 is moved to CH.

4.Register indirect Addressing mode:

The EA is specified in either pointer (BX) register or an index (SI or DI) register.
Example: MOV AX, [BX]
Here, data is present in a memory location in DS whose offset Address is in BX. The
effective Address of the data is given as 10H*DS+ [BX].
Instructi Memo
on Register ry
EA* EA* Datum

MOV AX, [BX]

If DS = 1010H, BX = 2000H, AX = 1000H then EA=12100H.

DS:BX ➔1010H:2000H
10*H DS➔ 10100
[BX] ➔ + 2000

EA ➔ 12100H

5.Indexed Addressing:
The offset of the operand is stored in one of the index registers. DS and ES are the default
segments for index registers SI and DI respectively.
Example: MOV AX, [SI]

Here, data is available at an offset Address stored in SI in DS. The effective address, in this case,
is computed as 10H*DS+ [SI].

If DS = 1010H, SI = 3010H, then EA=13110H.

DS: SI ➔1010H: 3010H
10*H DS➔ 10100
[BX] ➔ + 3010

EA ➔ 13110H
6.Register Relative addressing:

In this Addressing mode, the data is available at an effective Address formed by adding an 8-bit
or 16-bit displacement with the content of any one of the registers BX, BP, SI and DI in the
default (either DS or ES) segment. The example given before explains this mode.

26 Dr.P.Durgadevi,AP/RMKCET
Example: MOV AX, 5000H [BX]
Here, effective Address is given as 10H*DS+50H+ [BX].
If DS = 1010H, BX = 2000H, offset=5000 then EA=13110H.
DS:[5000+BX] ➔1010H: 5000+2000H
10*H DS ➔ 10100
Offset ➔ 5000
[BX] ➔ + 2000

EA ➔ 17100H

7.Based Indexed:
The effective Address of data is formed, in this Addressing mode, by adding content of a base
register (any one of BX or BP) to the content of an index register (any one of SI or DI). The
default segment register may be ES or DS.

Example: MOV AX, [BX] [SI]

Here, BX is the base register and SI is the index register. The effective Address is computed as
10H*DS+ [BX] + [SI]
If DS = 1010H, BX = 2000H, SI=3010 then EA=15110H.
DS:[SI+BX] ➔1010H:[3010H: 2000H]
10*H DS ➔ 10100
[SI] ➔ 3010
[BX] ➔ + 2000
EA ➔ 15110H
8.Relative Based Indexed:
The effective Address is formed by adding an 8-bit or 16-bit displacement with the sum of
contents of any one of the bases registers (BX or BP) and any one of the index registers, in a
default segment.

27 Dr.P.Durgadevi,AP/RMKCET
Example: MOV AX, 5000H [BX] [SI]
Here, 50H is an immediate displacement, BX is a base register and SI is an index register. The
effective address of data is computed as 160H*DS+ [BX] + [SI] + 50H.

If DS = 1010H, BX = 2000H, SI=3010 then EA=1A110H.

DS:[5000+BX+SI] ➔1010H: [5000+2000H+3010H]
10*H DS ➔ 10100
[SI] ➔ 3010
[BX] ➔ 2000
Offset ➔ +5000

EA ➔ 1A110H

Branch Related AddressingModes:

These type of Addressing are related to whether the Addressing is within the same
segment or to a different segment. Accordingly the Addressing modes in this category are known
as intrasegment and intersegment with direct or indirect addressing. These are explained below:
➢ Intrasegment Direct Addressing mode: The effective Address is the sum of the IP
and 8 / 16 bit displacement. It leads to a short jump if displacement is 8 bit, and this
Addressing may be used conditional or unconditional in a program.

28 Dr.P.Durgadevi,AP/RMKCET
 ➢ Intrasegment Indirect Addressing: In this Addressing mode the effective Address
may be in a register or at a memory location as accessed by any data related addressing
mode except the immediate and implied mode. This Addressing mode is called only
unconditionally.

➢ Intersegment direct Addressing mode: This Addressing mode when used replaces
the content of the CS and IP with the offset and segment part of the instruction. Used to
branch from one segment to another segment.

➢ Intersegment Indirect Addressing mode: The Addressing mode replaces the content
of the CS and IP with theAddress given in a register or in memory using any of the
data related Addressing modes.

1.5 Assembler directives:

Assembler directives help the assembler to correctly understand the assembly language
programs to prepare the codes. Another type of hint which helps the assembler to assign a
particular constant with a label or initialize particular memory locations or labels with
constants is called an operator. Rather, the operators perform the arithmetic and logical tasks
unlike directives that just direct the assembler to correctly interpret the program to code it
appropriately. The following directives are commonly used in the assembly language
programming practice using Microsoft Macro Assembler (MASM) or Turbo Assembler
(TASM).
➢ DB: Define Byte The DB directive is used to reserve byte or bytes of memory
locations in the available memory.

29 Dr.P.Durgadevi,AP/RMKCET
 LIST DB 0lH, 02H, 03H, 04H
This statement directs the assembler to reserve four memory locations for a list named LIST and
initialize them with the above specified four values.
➢
➢ DW: Define Word.
It makes the assembler reserve the number of memory words (16-bit) instead of bytes. Some
examples are given to explain this directive.
Examples WORDS DW 1234H, 4567H, 78ABH, 045CH
➢ DQ: Define Quad word This directive is used to direct the assembler to reset 4words (8
bytes) of memory for the specified variable and may initialize it with the specified values.
➢ DT: Define Ten Bytes. The DT directive directs the assembler to define the specified
variable requiring l -bytes for its storage and initialize the 10bytes with the specified
values.
➢ ASSUME: Assume Logical Segment Name The ASSUME directive is used to inform
the assembler, the names of the logical segments to be assumed for different segments
used in the program. In the assembly language program, each segment is given a name.
For example, the code segment may be given the name CODE, data segment may be given the
name DATA etc.
➢ ASSUME CS: CODE directs the assembler that the machine codes are available in a
segment named CODE, and hence the CS register is to be loaded with the
Address(segment) allotted by the operating system for the label CODE, while loading.
➢ ASSUME DS: DATA indicates to the assembler that the data items related to the
program, are available in a logical segment named DATA, and the DS register is
to be initialized by the segment Address value decided by the operating system for the
data segment, while loading.
➢ END: END of Program The END directive marks the end of an assembly language
program. When the assembler comes across this END directive, it ignores the source
lines available later on. Hence, it should be ensured that the END statement should be the
last statement in the file and should not appear in between.
➢ ENDP: END of Procedure. In assembly language programming, the subroutines are
called procedures. Thus, procedures may be independent program modules which
return particular results or values to the calling programs. The ENDP directive is used to
indicate the end of a procedure.
PROCEDURE STAR
.
.
.

STAR ENDP

➢ENDS: END of Segment This directive marks the end of a logical segment.

DATA SEGMENT
.
.
.
DATA ENDS

ASSUME CS: CODE, DS:DATA CODE SEGMENT.

30 Dr.P.Durgadevi,AP/RMKCET
 .
.
.
CODE ENDS
END
The above structure represents a simple program containing two segments named DATA
and CODE. The data related to the program must lie between the DATA SEGMENT and DATA
ENDS statements. Similarly, all the executable instructions must lie between CODE SEGMENT
and CODE ENDS statements.
➢EVEN: Align on Even Memory Address The EVEN directive updates the location counter
to the next even Address if the current location counter contents are not even, and assigns
the following routine or variable or constant to that Address.
➢EQU: Equate The directive EQU is used to assign a label with a value or a symbol. The
use of this directive is just to reduce the recurrence of the numerical values or constants in a
program code.
Example
LABEL EQU 0500H
ADDITION EQU ADD
The first statement assigns the constant 500H with the label LABEL, while the second statement
assigns another label ADDITION with mnemonic ADD
➢ EXTRN: External and PUBLIC: Public The directive EXTRN informs the assembler
that the names, procedures and labels declared after this directive have already been
defined in some other assembly language modules.
➢ GROUP: Group the Related segment The directive is used to form logical groups of
segments with similar purpose or type. This directive is used to inform the assembler to
form a logical group of the following segment names.
PROGRAM GROUP CODE, DATA, STACK

The above statement directs the loader/linker to prepare an EXE file such that CODE, DATA
and STACK segment must lie within a 64kbyte memory segment that is named as PROGRAM.
Now, for the ASSUME statement, one can use the label PROGRAM rather than CODE, DATA
and STACK as shown.
ASSUME CS: PROGRAM, DS: PROGRAM, SS: PROGRAM.
➢ LABEL: Label The Label directive is used to assign a name to the current content of the
location counter. At the start of the assembly process, the assembler initializes a location
counter to keep track of memory locations assigned to the program.
➢ LENGTH: Byte Length of a Label This directive is not available in MASM. This is
used to refer to the length of a data array or a string.
MOV CX, LENGTH ARRAY
➢ LOCAL The labels, variables, constants or procedures declared LOCAL in a module are
to be used only by that module.
➢ NAME: Logical Name of a Module the NAME directive is used to assign a name to an
assembly language program module. The module may now be referred to by its declared
name.
➢ OFFSET: Offset of a Label When the assembler comes across the OFFSET operator
along with a label, it first computes the 16-bit displacement (also called as offset

interchangeably) of the particular label, and replaces the string 'OFFSET LABEL' by the
computed displacement.
31 Dr.P.Durgadevi,AP/RMKCET
 ➢ ORG: Origin The ORG directive directs the assembler to start the memory allotment for
the particular segment, block or code from the declared Addressing the ORG statement
while starting the assembly process for a module, the assembler initializes a location
counter to keep track of the allotted addresses for the module. If the ORG statement is not
written in the program, the location counter is initialized to 0000. If an ORG 200H
statement is present at the starting of the code segment of that module, then the code will
start from 200H Addressing code segment)
➢ PROC: Procedure The PROC directive marks the start of a named procedure in the
statement.
➢ PTR: Pointer The pointer operator is used to declare the type of a label, variable or
memory operand. The operator PTR is prefixed by either BYTE or WORD. If the prefix
is BYTE, then the particular label, variable or memory operand is treated as an 8-bit
quantity, while if WORD is the prefix, then it is treated as a 16- bit quantity.
Example:
MOV AL, BYTE PTR [SI]; Moves content of memory location addressed by SI (8-bit) to
AL
➢ SEG: Segment of a Label The SEG operator is used to decide the segment Addressof the
label, variable, or procedure and substitutes the segment base Address in place of ‘SEG
label’. The example given below explain the use of SEG operator.
Example MOV AX, SEG ARRAY; This statement moves the segment address
➢ SEGMENT: Logical Segment The SEGMENT directive marks the starting of a
logical segment. The started segment is also assigned a name, i.e. label, by this
statement. The SEGMENT and ENDS directive must bracket each logical segment of a
program.
➢ TYPE The TYPE operator directs the assembler to decide the data type of the specified
label and replaces the 'TYPE label' by the decided data type. For the word type variable,
the data type is 2, for double word type, it is 4, and for byte type, it is 1. Suppose, the
STRING is a word array. The instruction
➢ GLOBAL The labels, variables, constants or procedures declared GLOBAL may be
used by other modules of the program. Once a variable is declared GLOBAL, it can be used
by any module in the program. The following statement declares the procedure ROUTINE
as a global label.
ROUTINE PROC GLOBAL
1.6 ASSEMBLY LANGUAGE PROGRAMMING
ALP for SUBition of two 16-bit numbers
ASSUME CS: CODE, DS: CODE, SS:
CODE
CODE SEGMENT ORG 1000H MOV SI, 1200H MOV DI, 1300H MOV CL,
00H MOV AX, [SI] MOV BX, [SI+02]
SUB AX, BX
JNC L1
MOV CL, 01H L1: MOV [DI], AX
MOV [DI+02], CL
INT 3H

CODE ENDS
END

32 Dr.P.Durgadevi,AP/RMKCET
ALP for Subtraction of two 16-bit numbers
ASSUME CS: CODE, DS: DATA, SS:

CODE
CODE SEGMENT
ORG 1000H
MOV SI, 1200H
MOV DI, 1300H
MOV CL, 00H
MOV AX, [SI]
MOV BX, [SI+2]
SUB AX, BX
JNC L1
MOV CL, 01H L1: MOV [DI], AX
MOV [DI+2], CL
INT 3H
CODE ENDS
END
ALP for Multiplication of two 16-bit numbers
ASSUME CS: CODE, DS: DATA, SS:
CODE
CODE SEGMENT
MOV SI, 1200H
MOV DI, 1300H
MOV AX,[SI]
MOV BX,[SI+02]
MUL BX
MOV [DI], AX
MOV [DI+02], DX
INT 3H
CODE ENDS
END
ALP for 2’s Complement 16-bit number
ASSUME CS: CODE, DS: CODE, SS:
CODE
CODE SEGMENT
ORG 1000H
MOV SI, 1200H
MOV AX, [SI]
NOT AX
INC AX
MOV [1300], AX
INT 3H
CODE ENDS
END
ALP for division of 16-bit number with 8-bit number
ASSUME CS: CODE, DS: DATA, SS:
CODE
CODE SEGMENT
ORG 1000H
MOV SI, 1200H
MOV DI, 1300H
MOV AX, [SI]
MOV BX, [SI+02]
DIV BX
33 Dr.P.Durgadevi,AP/RMKCET
 MOV [DI], AX
MOV [DI+02], DX

INT 3H
CODE ENDS
END
ALP for Searching Smallest number
ASSUME CS: CODE, DS: CODE CODE SEGMENT
ORG 1000H
START: MOV SI, 1200H
MOV DI, 1300H
MOV CL, [SI]
INC SI
MOV AL, [SI]
DEC CL,
AGAIN: INC SI
CMP AL, [SI]
JNC AHEAD / JC AHEAD MOV AL, [SI]
AHEAD: DEC CL
JNZ AGAIN
MOV [DI], AL
INT 3H
CODE ENDS
END
ALP for Find and replace

ASSUME CS: CODE, DS: CODE

CODE SEGMENT
ORG 1000H
MOV CX, 0005H
MOV DI, 1200H
MOV AL, 45H
MOV BL, 57H
CLD
REPNE SCASB
DEC DI
MOV [DI], BL
INT 3
CODE ENDS

END
1.7 MODULAR PROGRAMMING:

Complex programs are divided into many parts and each sub-part are known as modules. All the
modules perform a well-defined task. Formulation of computer code using a module is known as
modular programming.
The reason for breaking a program into small parts are
➢ Modules are easier to understand.
➢ Different modules can be assigned to different programmers.
➢ The debugging and testing can be done in a more orderly fashion.
➢ Documentation can be more easily understood.
➢ Modifications may be localized.
34 Dr.P.Durgadevi,AP/RMKCET
Most assembler languages are used in modularization process in three ways such as,
1.Allow data to be structured so that they can be accessed by several modules
2.Provide for procedures or subroutines
3.Permit sections of code,known as macros.
To perform modular programming,the following tasks must be performed.
➢ Linking and relocation
➢ Stack Operation
➢ Procedures
➢ Interrupt process
Linking And Relocation
The assembly language program can be written with an ordinary text editors such as word
star,editor etc.The assembly language program text is an input to the assembler.The assembler
translates assembly language statements to their binary equivalent known as object code. During
assembling process assembler checks for syntax errors and displays them before giving object code
module.The object code module contains the information about whwre the program or module to be
loaded in memory.If the object module is to be linked with other separate modules then it containg
additional linkage information.
At link time,separately assembled modules are combined into one single load module by the
linker.The linker also SUBs any required initialization or finalization code to allow the OS to start
the program running and to return control to OS after the program is completed.
At load time,the program loader copies the program into computer main memory and at execution
time ,the program execution begins.
If the modules in the program they are assembled separately,then there is one main module and
other modules.This main module has the first instruction to be executed and it is terminated by an
END statement with entry point satisfied.Other modules are terminated by a END statement with
no operand.

Creation and Execution of Assembly language program

Segment combination
In addition to the linker commands, the assembler provides a means of regulating the way
segments in different object modules are organized by the linker.
Segments with same name are joined together by using the modifiers attached to the
SEGMENT directives. SEGMENT directive may have the form
Segment name SEGMENT Combination-type

35 Dr.P.Durgadevi,AP/RMKCET
where the combine-type indicates how the segment is to be located within the load module.
Segments that have different names cannot be combined and segments with the same name but no
combine-type will cause a linker error.

The possible combine-types are:

PUBLIC – If the segments in different modules have the same name and combine- type
PUBLIC, then they are concatenated into a single element in the load module. The ordering in the
concatenation is specified by the linker command.
COMMON – If the segments in different object modules have the same name and the
combine-type is COMMON, then they are overlaid so that they have the same starting address.
The length of the common segment is that of the longest segment being overlaid.
STACK – If segments in different object modules have the same name and the
combine type
STACK, then they become one segment whose length is the sum of the lengths of the individually
specified segments. In effect, they are combined to form one large stack
AT – The AT combine-type is followed by an expression that evaluates to a constant which
is to be the segment address. It allows the user to specify the exact location of the segment in
memory.
MEMORY – This combine-type causes the segment to be placed at the last of the load module. If
more than one segment with the MEMORY combine-type is being linked, only the first one will
be treated as having the MEMORY combine type; the others will be overlaid as if they had
COMMON combine-type.

Fig. Segment combinations resulting from the PUBLIC and Common

Combination types

36 Dr.P.Durgadevi,AP/RMKCET
 Fig. Formation of a stack from two segments

Access to External Identifiers

If an identifier is defined in an object module, then it is said to be a local (or
internal) identifier relative to the module. If it is not defined in the module but is defined in one
of the other modules being linked, then it is referred to as an external (or global) identifier relative
to the module. Two lists are implemented by the EXTRN and PUBLIC directives, which have the
forms:

where the identifiers are the variables and labels being declared or as being available to other
modules.
The assembler must know the type of all external identifiers before it can generate the proper
machine code, a type specifier must be associated with each identifier in an EXTRN statement.
For a variable the type may be BYTE, WORD, or DWORD and for a label it may be NEAR or
FAR.
One of the primary tasks of the linker is to verify that every identifier appearing in an
EXTRN statement is matched by one in a PUBLIC statement. If this is not the case, then there
will be an undefined reference and a linker error will occur. The offsets for the local identifier will
be inserted by the assembler, but the offsets for the external identifiers and all segment addresses
must be inserted by the linking process. The offsets associated with all external references can be
assigned once all of the object modules have been found and their external symbol tables have
been examined. The assignment of the segment addresses is called relocation and is done after the
linking process has determined exactly where each segment is to be put in memory.

37 Dr.P.Durgadevi,AP/RMKCET
 STACKS
The stack is a block of memory that may be used for temporarily storing the contents of the
registers inside the CPU. It is a top-down data structure whose elements are accessed using the
stack pointer (SP) which gets decremented by two as we store a data word into the stack and gets
incremented by two as we retrieve a data word from the stack back to the CPU register.
The process of storing the data in the stack is called ‘pushing into’ the stack and the
reverse process of transferring the data back from the stack to the CPU register is known as
‘popping off’ the stack. The stack is essentially Last-In-First -Out (LIFO) data segment. This
means that the data which is pushed into the stack last will be on top of stack and will be popped
off the stack first.

The stack pointer is a 16-bit register that contains the offsetAddressof the memory location
in the stack segment. The stack segment, like any other segment, may have a memory block of a
maximum of 64 Kbytes locations, and thus may overlap with any other segments. Stack Segment
register (SS) contains the baseAddressof the stack segment in the memory.
The Stack Segment register (SS) and Stack pointer register (SP) togetherAddressthe stack-
top as explained below:

If the stack top points to a memory location 52050H, it means that the location 52050H is already
occupied with the previously pushed data. The next 16 bit push operation will decrement the stack
pointer by two, so that it will point to the new stack-top 5204EH and the decremented contents of
SP will be 204EH. This location will now be occupied by the recently pushed data.
Thus for a selected value of SS, the maximum value of SP=FFFFH and the segment can
have maximum of 64K locations. If the SP starts with an initial value of FFFFH, it will be
decremented by two whenever a 16-bit data is pushed onto the stack. After successive push
operations, when the stack pointer contains 0000H, any attempt to further push the data to the
stack will result in stack overflow.
After a procedure is called using the CALL instruction, the IP is incremented to the next
instruction. Then the contents of IP, CS and flag register are pushed automatically to the stack.
The control is then transferred to the specified Addressing the CALL instruction i.e. starting
Address of the procedure. Then the procedure is executed.

Fig. Stack –top Address calculation

38 Dr.P.Durgadevi,AP/RMKCET
PROCEDURES

A procedure is a set of code that can be branched to and returned from in such a way that the code
is as if it were inserted at the point from which it is branched to. The branch to procedure is
referred to as the call, and the corresponding branch back is known as the return. The return is
always made to the instruction immediately following the call regardless of where the call is
located.

Calls, Returns, and Procedure Definitions

The CALL instruction not only branches to the indicated address, but also pushes the
Return Address onto the stack. The RET instruction simply pops the return Address from the
stack. The registers used by the procedure need to be stored before their contents are changed, and
then restored just before their contents are changed, and then restored just before the procedure is
excited.
A CALL may be direct or indirect and intrasegment or intersegment. If the CALL is
intersegment, the return must be intersegment. Intersegment call must push both (IP) and(CS)
onto the stack. The return must correspondingly pop two words from the stack. In the case of
intrasegment call, only the contents of IP will be saved and retrieved when call and return
instructions are used.

Procedures are used in the source code by placing a statement of the form at the beginning
of the procedure

Procedure name PROC Attribute

--------
----------
Procedure name ENDP

The attribute that can be used will be either NEAR or FAR. If the attribute is NEAR, the RET
instruction will only pop a word into the IP register, but if it is FAR, it will also pop a word into
the CS register.

A procedure may be in:

1. The same code segment as the statement that calls it.

2. A code segment that is different from the one containing the statement that calls it, but in the
same source module as the calling statement.

3. A different source module and segment from the calling statement.

In the first case, the attribute could be NEAR provided that all calls are in the same code segment
as the procedure. For the latter two cases the attribute must be FAR. If the procedure is given a
FAR attribute, then all calls to it must be intersegment calls even if the call is from the same code
segment. For the third case, the procedure name must be declared in EXTRN and PUBLIC
statements.

39 Dr.P.Durgadevi,AP/RMKCET
 Saving and Restoring Registers

When both the calling program and procedure share the same set of registers, it is necessary
to save the registers when entering a procedure, and restore them before returning to the calling
program.
MSK PROC NEAR
PUSH AX
PUSH BX
PUSH CX
POP CX
POP BX
POP AX
RET
MSK ENDP

Procedure Communication

There are two general types of procedures, those operate on the same set of data and
those that may process a different set of data each time they are called.

If a procedure is in the same source module as the calling program, then the procedure can refer to
the variables directly.

When the procedure is in a separate source module it can still refer to the source module
directly provided that the calling program contains the directive PUBLIC ARY, COUNT, SUM

EXTRN ARY: WORD, COUNT: WORD, SUM: WORD

Recursive Procedures

When a procedure is called within another procedure it called recursive procedure. To make sure
that the procedure does not modify itself, each call must store its set of parameters, registers, and
all temporary results in a different place in memory
Eg. Recursive procedure to compute the factorial

MACROS

Disadvantages of Procedure

1. Linkage associated with them.

2. It sometimes requires more code to program the linkage than is needed to perform the task. If
this is the case, a procedure may not save memory and execution time is considerably increased.

Macros is needed for providing the programming ease of a procedure while avoiding the linkage.
Macro is a segment of code that needs to be written only once but whose basic structure can be
caused to be repeated several times within a source module by placing a single statement at the
point of each reference.

40 Dr.P.Durgadevi,AP/RMKCET
 A macro is unlike a procedure in that the machine instructions are repeated each time the
macro is referenced. Therefore, no memory is saved, but programming time is conserved (no
linkage is required) and some degree of modularity is achieved. The code that is to be repeated is
called the prototype code. The prototype code along with the statements for referencing and
terminating is called the macro definition.

Once a macro is defined, it can be inserted at various points in the program by using macro
calls. When a macro call is encountered by the assembler, the assembler replaces the call
with the macro code. Insertion of the macro code by the assembler for a macro call is referred to
as a macro expansion.. During a macro expansion, the first actual parameter replaces the first
dummy parameter in the prototype code, the second actual parameter replaces the second dummy
parameter, and so on.

A macro call has the form

%Macro name (Actual parameter list) with the actual parameters being separated by
commas.
%MULTIPLY (CX, VAR, XYZ[BX]

Above macro call results in following set of codes.

PUSH DX
PUSH AX
MOV AX,CX
IMUL VAR
MOV XYZ[BX],AX
POP AX
POP DX

It is possible to define a macro with no dummy parameters, but in this case the call must not include
any parameters. Consider a macro for pushing the contents at beginning of a procedure.

Macro definition consists of

%*DEFINE(SAVEREG)
( PUSH AX
PUSH BX
PUSH CX
PUSH DX
)
This macro is called using the statement
%SAVEREG
The above macro can be called at the beginning of the each procedure to save the register contents.
A similar macro could be used to restore the register contents at the end of each procedure.
%*DEFINE (RESTORE)
( POP DX
POP CX
POP BX
POP AX
)

41 Dr.P.Durgadevi,AP/RMKCET
Local Labels

Consider a macro called ABSOL which makes use of labels. This macro is used to replace the
operand by its absolute value.

%*DEFINE (ABSOL(OPER))
( CMP %OPER, 0
JGE NEXT
NEG %OPER
%NEXT: NOP)

When the macro ABSOL is called for the first time, the label NEXT will appear in the program
and, therefore it becomes defined. Any subsequent call will cause NEXT to be redefined. This will
result in an error during assembly process because NEXT has been associated with more than one
location. One solution to this problem would be to have NEXT replaced by a dummy parameter
for the label. This would require the programmer to keep track of dummy parameters used.
One solution to this problem is the use of Local Labels. Local labels are special labels
that will have suffixes that get incremented each time the macros are called. These suffixes are
two digit numbers that gets incremented by one starting from zero. Labels can be declared as local
label by attaching a prefix Local. Local List of Local labels at the end of first statement in the
macro definition.

Nested Macros

It is possible for a macro call to appear within a macro definition. This is referred to as Macro
nesting. The limitation of nested macros is that all macros included in the definition of a given
macro must be defined before the given macro is called.

INTERRUPTS AND INTERRUPT ROUTINES

Interrupt and its Need:

The microprocessors allow normal program execution to be interrupted in order to carry out a
specific task/work. The processor can be interrupted in the following ways
➢ by an external signal generated by a peripheral,

➢ by an internal signal generated by a special instruction in the program,

➢ by an internal signal generated due to an exceptional condition which occurs while executing
an instruction. (For example, in 8086 processor, divide by zero is an exceptional condition
which initiates type 0 interrupt and such an interrupt is also called execution).
The process of interrupting the normal program execution to carry out a specific task/work is
referred to as interrupt. The interrupt is initiated by a signal generated by an external device or by
a signal generated internal to the processor.
When a microprocessor receives an interrupt signal it stops executing current normal
program, save the status (or content) of various registers (IP, CS and flag registers in case of
8086) in stack and then the processor executes a subroutine/procedure in order to perform the
specific task/work requested by the interrupt. The subroutine/procedure that is executed in
response to an interrupt is also called Interrupt Service Subroutine (ISR). At the end of ISR, the
42 Dr.P.Durgadevi,AP/RMKCET
 stored status of registers in stack is restored to respective registers, and the processor resumes the
normal program execution from the point {instruction) where it was interrupted.
The external interrupts are used to implement interrupt driven data transfer scheme. The
interrupts generated by special instructions are called software interrupts and they are used to
implement system services/calls (or monitor services/calls). The system/monitor services are
procedures developed by system designer for various operations and stored in memory. The user
can call these services through software interrupts. The interrupts generated by exceptional
conditions are used to implement error conditions in the system.

Interrupt Driven Data Transfer Scheme

The interrupts are useful for efficient data transfer between processor and peripheral.

When a peripheral is ready for data transfer, it interrupts the processor by sending an appropriate
signal. Upon receiving an interrupt signal, the processor suspends the current program execution,
save the status in stack and executes an ISR to perform the data transfer between the peripheral
and processor.
At the end of ISR the processor status is restored from stack and processor resume its
normal program execution. This type of data transfer scheme is called interrupt driven data
transfer scheme.

The data transfer between the processor and peripheral devices can be implemented either by
polling technique or by interrupt method. In polling technique, the processor has to periodically
poll or check the status/readiness of the device and can perform data transfer only when the device
'is ready. In polling technique the processor time is wasted, because the processor has to suspend
its work and check the status of the device in predefined intervals.

If the device interrupts the processor to initiate a data transfer whenever it is ready then the
processor time is effectively utilized because the processor need not suspend its work and check
the status of the device in predefined intervals.

For an example, consider the data transfer from a keyboard to the processor. Normally a
keyboard has to be checked by the processor once in every 10 milliseconds for a key press.
Therefore once in every 10 milliseconds the processor has to suspend its work and then check the
keyboard for a valid key code. Alternatively, the keyboard can interrupt the processor, whenever a
key is pressed and a valid key code is generated. In this way the processor need not waste its time
to check the keyboard once in every 10 milliseconds.

Classification of Interrupts

In general the interrupts can be classified in the following three ways:

1. Hardware and software interrupts

2. Vectored and Non Vectored interrupt:

3. Maskable and Non Maskable interrupts.

43 Dr.P.Durgadevi,AP/RMKCET
The interrupts initiated by external hardware by sending an appropriate signal to the interrupt pin of
the processor is called hardware interrupt. The 8086 processor has two interrupt pins INTR and
NMI. The interrupts initiated by applying appropriate signal to these pins are called hardware
interrupts of 8086.
The software interrupts are program instructions. These instructions are inserted at desired
locations in a program. While running a program, if software interrupt instruction is encountered
then the processor initiates an interrupt. The 8086 processor has 256 types of software interrupts.
The software interrupt instruction is INT n, where n is the type number in the range 0 to 255.

When an interrupt signal is accepted by the processor, if the program control automatically
branches to a specific Address(called vector Address) then the interrupt is called vectored
interrupt. The automatic branching to vector Address is predefined by the manufacturer of
processors. (In these vector Addresses the interrupt service subroutines (ISR) are stored). In non-
vectored interrupts the interrupting device should supply the Address of the ISR to be executed in
response to the interrupt. All the 8086 interrupts are vectored interrupts. The vector Address for an
8086 interrupt is obtained from a vector table implemented in the first 1kb memory space (00000h
to 03FFFh).
The processor has the facility for accepting or rejecting hardware interrupts. Programming
the processor to reject an interrupt is referred to as masking or disabling and programming the
processor to accept an interrupt is referred to as unmasking or enabling. In 8086 the interrupt flag
(IF) can be set to one to unmask or enable all hardware interrupts and IF is cleared to zero to mask
or disable a hardware interrupts except NMI.

The interrupts whose request can be either accepted or rejected by the processor are called
maskable interrupts. The interrupts whose request has to be definitely accepted (or cannot be
rejected) by the processor are called non-maskable interrupts. Whenever a request is made by
non-maskable interrupt, the processor has to definitely accept that request and service that
interrupt by suspending its current program and executing an ISR. In 8086 processor all the
hardware interrupts initiated through INTR pin are maskable by clearing interrupt flag (IF). The
interrupt initiated through NMI pin and all software interrupts are non-maskable.

Sources of Interrupts in 8086

An interrupt in 8086 can come from one of the following three sources.

1. One source is from an external signal applied to NMI or INTR input pin of the processor. The
interrupts initiated by applying appropriate signals to these input pins are called hardware
interrupts.
2. A second source of an interrupt is execution of the interrupt instruction "INT n", where n is the
type number. The interrupts initiated by "INT n" instructions are called software interrupts.

3. The third source of an interrupt is from some condition produced in the 8086 by the execution
of an instruction. An example of this type of interrupt is divide by zero interrupt. Program
execution will be automatically interrupted if you attempt to divide an operand by zero. Such
conditional interrupts are also known as exceptions.

44 Dr.P.Durgadevi,AP/RMKCET
 Interrupts of 8086

The 8086 microprocessor has 256 types of interrupts. INTEL has assigned a type number to each
interrupt. The type numbers are in the range of 0 to 255. The 8086 processor has dual facility of
initiating these 256 interrupts. The interrupts can be initiated either by executing "INT n"
instruction where n is the type number or the interrupt can be initiated by sending an appropriate
signal to INTR input pin of the processor.

In general the interrupts can be classified as following:

1.External Hardware Interrupts
2.Non Maskable Interrupts
3.Software Interrupts
4.Internal Interrupts
5.Reset
Interrupts Priority

Hardware, software and internal interrupts are serviced on a priority basis.

Each interrupt is given a different priority level by assigning a type number. Type 0 identiifes
highest priority and type 255 identifies the lowest priority interrupt.
The interrupt priority follows,.
➢ Reset
➢ Internal interrupts
➢ Software interrupts
➢ Non maskable interrupts
➢ External hardware interrupts
Interrupt Vector Table

The first 1Kbyte of memory of 8086 (00000 to003FF) is set aside as a table for storing the starting
addresses of Interrupt Service Procedures(ISP).Since 4-bytes are required for storing starting
addresses of ISPs, the table can hold 256 Interrupt procedures.
The starting Address of an ISP is often called the Interrupt Vector or Interrupt Pointer. Therefore
the table is referred as Interrupt Vector Table. In this table, IP value is put in as low word of the
vector & CS is put in high vector.

45 Dr.P.Durgadevi,AP/RMKCET
 The operation of an interrupt on the 8086 microprocessor
1.External interface sends an interrupt signal, to the Interrupt Request (INTR) pin, or an internal
interrupt occurs.
2.The CPU finishes the present instruction and sends Interrupt Acknowledge (INTA) to hardware
interface.
3. The interrupt type N is sent to the Central Processing Unit (CPU) via the data bus from hardware
interface.
4. The contents of the flag registers are pushed onto the stack.
5. Both interrupts (IF) and (TF) flags are cleared. This disables the INTR pin and the trap or single
step feature.
6. The contents of the code segment register (CS) are pushed onto the stack.
7. The contents of the instruction pointer (IP) are pushed onto the stack.
8. The interrupt vector contents are fetched ,from(4*N) and then placed into the IP and
from(4*N+2) into the CS so that the next instruction executes at the interrupt service procedure
addressed by the interrupt vector.
9.While returning from the interrupt service routine by the Interrupt return (IRET) instruction, The
IP,CS and Flag registers are popped from the stack and return their state prior to the interrupt.

8086 Interrupt Instructions.

BYTE AND STRING HANDLING INSTRUCTIONS

The 8086 microprocessor is equipped with special instructions to handle string operations. By
string we mean a series of data words or bytes that reside in consecutive memory locations. The
string instructions of the 8086 permit a programmer to implement operations such as to move data
from one block of memory to a block elsewhere in memory. A second type of operation that is
easily performed is to scan a string and data elements stored in memory looking for a specific
value.

Other examples are to compare the elements and two strings together in order to determine
whether they are the same or different.

46 Dr.P.Durgadevi,AP/RMKCET
 Move String: MOV SB, MOV SW:

An element of the string specified by the source index (SI) register with respect to the current data
segment (DS) register is moved to the location specified by the destination index (DI) register
with respect to the current extra segment (ES) register. The move can be performed on a byte
(MOV SB) or a word (MOV SW) of data. After the move is complete, the contents of both SI &
DI are automatically incremented or decremented by 1 for a byte move and by 2 for a word move.
Address pointers SI and DI increment or decrement depends on how the direction flag DF is set.

Load and store strings: (LOD SB/LOD SW and STO SB/STO SW)
LOD SB: Loads a byte from a string in memory into AL. The Addressing SI is used relative to DS
to determine the Address of the memory location of the string element.
(AL) ¬ [(DS) + (SI)] (SI) ¬ (SI) + 1
LOD SW: The word string element at the physical Address derived from DS and SI is to be
loaded into AX. SI is automatically incremented by 2.
(AX) ¬ [(DS) + (SI)] (SI) ¬ (SI) + 2
STO SB:
Stores a byte from AL into a string location in memory. This time the contents of ES and DI are
used to form the Address of the storage location in memory.
[(ES) + (DI)] ¬ (AL) (DI) ¬ (DI) + 1
STO SW: [(ES) + (DI)] ¬ (AX) (DI) ¬ (DI) + 2
Repeat String: REP
The basic string operations must be repeated to process arrays of data. This is done by inserting a
repeat prefix before the instruction that is to be repeated. Prefix REP causes the basic string
operation to be repeated until the contents of register CX become equal to zero. Each time the
instruction is executed, it causes CX to be tested for zero, if CX is found to be nonzero it is
decremented by 1 and the basic string operation is repeated.
Example: Clearing a block of memory by repeating STOSB MOV AX, 0

MOV ES, AX
MOV DI, A000
MOV CX, OF CDF
REP STOSB NEXT:

The prefixes REPE and REPZ stand for same function. They are meant for use with the CMPS
and SCAS instructions. With REPE/REPZ the basic compare or scan operation can be repeated as
long as both the contents of CX are not equal to zero and zero flag is 1.

REPNE and REPNZ works similarly to REPE/REPZ except that now the operation is
repeated as long as CX¹0 and ZF=0. Comparison or scanning is to be performed as long as the
string elements are unequal (ZF=0) and the end of the string is not yet found (CX¹0).

Auto Indexing for String Instructions:

SI & DI addresses are either automatically incremented or decremented based on the setting of
the direction flag DF.
When CLD (Clear Direction Flag) is executed DF=0 permits auto increment by 1. When STD
(Set Direction Flag) is executed DF=1 permits auto decrement by 1.

47 Dr.P.Durgadevi,AP/RMKCET
 UNIT-II
8086 SYSTEM BUS STRUCTURE
The 8086 Microprocessor is a 16-bit CPU available in 3 clock rates, i.e. 5, 8 and 10MHz,
packaged in a 40 pin CERDIP or plastic package. The 8086 Microprocessor operates in
single processor or multiprocessor configurations to achieve high performance. The pin
configuration is as shown in fig1. Some of the pins serve a particular function in minimum
mode (single processor mode) and others function in maximum mode (multiprocessor mode)
configuration.
The 8086 signals can be categorized in three groups. The first are the signals having
common functions in minimum as well as maximum mode, the second are the signals which
have special functions in minimum mode and third are the signals having special functions
for maximum mode

2.1 8086 signals

The following signal description is common for both the minimum and maximum modes
 Fig.2.1 Bus signals

The 8086 signals can be categorized in three groups. The first are the signals having
common functions in minimum as well as maximum mode, the second are the signals which
have special functions in minimum mode and third are the signals having special functions
for maximum mode.
The following signal description are common for both the minimum and maximum modes.
AD15-AD0: These are the time multiplexed memory I/O address and data lines. Address
remains on the lines during T1 state, while the data is available on the data bus during T2,
T3, TW and T4. Here T1, T2, T3, T4 and TW are the clock states of a machine cycle. TW is
a wait state. These lines are active high and float to a tristate during interrupt acknowledge
and local bus hold acknowledge cycles.
A19/S6, A18/S5, A17/S4, A16/S3: These are the time multiplexed address and status lines.
During T1, these are the most significant address lines or memory operations. During I/O
operations, these lines are low. During memory or I/O operations, status information is
available on those lines for T2, T3, TW and T4 .The status of the interrupt enable flag
bit(displayed on S5) is updated at the beginning of each clock cycle. The S4 and S3
combinedly indicate which segment register is presently being used for memory accesses as
shown in Table 2.1.
These lines float to tri-state off (tristated) during the local bus hold acknowledge. The status
line S6 is always low (logical). The address bits are separated from the status bits using
latches controlled by the ALE signal.
 Table 2.1 Bus High Enable / status

BHE/S7-Bus High Enable/Status: The bus high enable signal is used to indicate the
transfer of data over the higher order (D15-D8) data bus as shown in Table 2.1. It goes low
for the data transfers over D15-D8 and is used to derive chip selects of odd address memory
bank or peripherals. BHE is low during T1 for read, write and interrupt acknowledge cycles,
when- ever a byte is to be transferred on the higher byte of the data bus. The status
information is available during T2, T3 and T4. The signal is active low and is tristated during
'hold'. It is low during T1 for the first pulse of the interrupt acknowledge cycle.

Table 2.2 Bus high enable status

RD-Read: Read signal, when low, indicates the peripherals that the processor is performing
a memory or I/O read operation. RD is active low and shows the state for T2, T3, TW of any
read cycle. The signal remains tristated during the 'hold acknowledge'.
READY: This is the acknowledgement from the slow devices or memory that they have
completed the data transfer. The signal made available by the devices is synchronized by the
8284A clock generator to provide ready input to the 8086. The signal is active high. INTR-
lnterrupt Request: This is a level triggered input. This is sampled during the last clock
cycle of each instruction to determine the availability of the request. If any interrupt request
is pending, the processor enters the interrupt acknowledge cycle. This can be internally
masked by resetting the interrupt enable flag. This signal is active high and internally
synchronized.
TEST: This input is examined by a 'WAIT' instruction. If the TEST input goes low,
execution will continue, else, the processor remains in an idle state. The input is
synchronized internally during each clock cycle on leading edge of clock.
NMI-Non-maskable Interrupt: This is an edge-triggered input which causes a Type2
interrupt. The NMI is not maskable internally by software. A transition from low to high
initiates the interrupt response at the end of the current instruction. This input is internally
synchronized.
RESET: This input causes the processor to terminate the current activity and start execution
from FFFF0H. The signal is active high and must be active for at least four clock cycles. It
restarts execution when the RESET returns low. RESET is also internally synchronized.
CLK-Clock Input: The clock input provides the basic timing for processor operation and bus
control activity. Its an asymmetric square wave with 33% duty cycle. The range of frequency
for different 8086 versions is from 5MHz to 10MHz.
VCC: +5V power supply for the operation of the internal circuit. GND ground for the
internal circuit.
MN/MX: The logic level at this pin decides whether the processor is to operate in
either minimum (single processor) or maximum (multiprocessor) mode.

The following pin functions are for the minimum mode operation of 8086. M/IO -
Memory/IO: This is a status line logically equivalent to S2 in maximum mode. When it is
low, it indicates the CPU is having an I/O operation, and when it is high, it indicates that the
CPU is having a memory operation. This line becomes active in the previous T4 and remains
active till final T4 of the current cycle. It is tristated during local bus "hold acknowledge".

INTA -Interrupt Acknowledge: This signal is used as a read strobe for interrupt
acknowledge cycles. In other words, when it goes low, it means that the processor has
accepted the interrupt. It is active low during T2, T3 and TW of each interrupt acknowledge
cycle.
ALE-Address latch Enable: This output signal indicates the availability of the valid
address on the address/data lines, and is connected to latch enable input of latches. This
signal is active high and is never tristated.
DT /R -Data Transmit/Receive: This output is used to decide the direction of data flow
through the transreceivers (bidirectional buffers). When the processor sends out data, this
signal is high and when the processor is receiving data, this signal is low. Logically, this is
equivalent to S1 in maximum mode. Its timing is the same as M/I/O. This is tristated during
'hold acknowledge'.
DEN-Data Enable This signal indicates the availability of valid data over the address/data
lines. It is used to enable the transreceivers (bidirectional buffers) to separate the data from
the multiplexed address/data signal. It is active from the middle ofT2 until the middle of T4
DEN is tristated during 'hold acknowledge' cycle.
HOLD, HLDA-Hold/Hold Acknowledge: When the HOLD line goes high, it indicates to
the processor that another master is requesting the bus access. The processor, after receiving
the HOLD request, issues the hold acknowledge signal on HLDA pin, in the middle of the
next clock cycle after completing the current bus (instruction) cycle. At the same time, the
processor floats the local bus and control lines. When the processor
detects the HOLD line low, it lowers the HLDA signal. HOLD is an asynchronous input and
it should be externally synchronized.
If the DMA request is made while the CPU is performing a memory or I/O cycle, it will
release the local bus during T 4 provided:
1. The request occurs on or before T 2 state of the current cycle.
2. The current cycle is not operating over the lower byte of a word (or operating on an odd
address).
3. The current cycle is not the first acknowledge of an interrupt acknowledge sequence.
4. A Lock instruction is not being executed.
So far we have presented the pin descriptions of 8086 in minimum mode.
The following pin functions are applicable for maximum mode operation of 8086.
S2, S1, S0 -Status Lines: These are the status lines which reflect the type of operation,
being carried out by the processor. These become active during T4 of the previous cycle and
remain active during T1 and T2 of the current bus cycle. The status lines return to passive
state during T3 of the current bus cycle so that they may again become active for the next
bus cycle during T4. Any change in these lines during T3 indicates the starting of a new
cycle, and return to passive state indicates end of the bus cycle. These status lines are
encoded in table 1.3.
 Table 2.3. Status lines

LOCK: This output pin indicates that other system bus masters will be prevented from
gaining the system bus, while the LOCK signal is low. The LOCK signal is activated by the
'LOCK' prefix instruction and remains active until the completion of the next instruction.
This floats to tri-state off during "hold acknowledge". When the CPU is executing a critical
instruction which requires the system bus, the LOCK prefix instruction ensures that other
processors connected in the system will not gain the control of the bus. The 8086, while
executing the prefixed instruction, asserts the bus lock signal output, which may be
connected to an external bus controller.
QS1, QS0-Queue Status: These lines give information about the status of the code prefetch
queue. These are active during the CLK cycle after which the queue operation is performed.
These are encoded as shown in Table 1.4.

Table 2.4. Queue Status

This modification in a simple fetch and execute architecture of a conventional

microprocessor offers an added advantage of pipelined processing of the instructions. The
8086 architecture has a 6-byte instruction prefetch queue. Thus even the largest (6- bytes)
instruction can be prefetched from the memory and stored in the prefetch queue. This results
in a faster execution of the instructions. In 8085, an instruction (opcode and operand) is
fetched, decoded and executed and only after the execution of this instruction, the next one is
fetched. By prefetching the instruction, there is a considerable speeding up in instruction
execution in 8086. This scheme is known as instruction pipelining. At the starting the CS:IP
is loaded with the required address from which the execution is to be started. Initially, the
queue will be empty and the microprocessor starts a fetch operation to bring one byte (the
first byte) of instruction code, if the CS:IP address is odd or two bytes at a time, if the CS:IP
address is even. The first byte is a complete opcode in case of some instructions (one byte
opcode instruction) and it is a part of opcode, in case of other instructions (two byte long
opcode instructions), the remaining part of opcode may lie in the second byte. But invariably
the first byte of an instruction is an opcode. These opcodes along with data are fetched and
arranged in the queue. When the first byte from the queue goes for decoding and
interpretation, one byte in the queue becomes empty and subsequently the queue is updated.
The microprocessor does not perform the next fetch operation till at least two bytes of the
instruction queue are emptied. The instruction execution cycle is never broken for fetch
operation. After decoding the first byte, the decoding circuit decides whether the instruction
is of single opcode byte or double opcode byte. If it is single opcode byte, the next bytes are
treated as data bytes depending upon the decoded instruction length, other wise, the next
byte in the queue is treated as the second byte of the instruction opcode. The second byte is
then decoded in continuation with the first byte to decide the instruction length and the
number of subsequent bytes to be treated as instruction data. The queue is updated after
every byte is read from the queue but the fetch cycle is initiated by BIU only if at least, two
bytes of the queue are empty and the EU may be concurrently executing the fetched
instructions. The next byte after the instruction is completed is again the first opcode byte of
the next instruction. A similar procedure is repeated till the complete execution of the
program. The main point to be noted here is, that the fetch operation of the next instruction is
overlapped with the execution of the current instruction. As shown in the architecture, there
are two separate units, namely, execution unit and bus interface unit. While the execution
unit is busy in executing an instruction, after it is completely decoded, the bus interface unit
may be fetching the bytes o( the next instruction from memory, depending upon the queue
status. Figure 1.6 explains the queue operation.
RQ/GT0, RQ/GT1-ReQuest/Grant: These pins are used by other local bus masters, in
maximum mode, to force the processor to release the local bus at the end of the processor's
current bus cycle. Each of the pins is bidirectional with RQ/GT0 having higher priority than
RQ/ GT1, RQ/GT pins have internal pull-up resistors and may be left unconnected. The
request! grant sequence is as follows:
1. A pulse one clock wide from another bus master requests the bus access to 8086.
2. During T4 (current) or T1 (next) clock cycle, a pulse one clock wide from 8086 to the
requesting master, indicates that the 8086 has allowed the local bus to float and that it will
enter the "hold acknowledge" state at next clock cycle. The CPU's bus interface unit is likely
to be disconnected from the local bus of the system.
3. A one clock wide pulse from another master indicates to 8086 that the 'hold' request is
about to end and the 8086 may regain control of the local bus at the next clock cycle. Thus
each master to master exchange of the local bus is a sequence of 3 pulses. There must be at
least one dead clock cycle after each bus exchange. The request and grant pulses are active
low. For the bus requests those are received while 8086 is performing memory or I/O cycle,
the granting of the bus is governed by the rules as discussed in case of HOLD, and HLDA in
minimum mode.

2.2 Basic configurations : Read Write Timing Diagram

✓ General Bus Operation
The 8086 has a combined address and data bus commonly referred as a time multiplexed
address and data bus. The main reason behind multiplexing address and data over the same
pins is the maximum utilization of processor pins and it facilitates the use of 40 pin standard
DIP package. The bus can be demultiplexed using a few latches and transreceivers,
whenever required.
Basically, all the processor bus cycles consist of at least four clock cycles. These are referred
to as T1, T2, T3, T4. The address is transmitted by the processor during T1, It is present on
the bus only for one cycle. The negative edge of this ALE pulse is used to separate the
address and the data or status information.
In maximum mode, the status lines S0, S1 and S2 are used to indicate the type of operation.
Status bits S3 to S7 are multiplexed with higher order address bits and the BHE signal.
Address is valid during T1 while status bits S3 to S7 are valid during T2 through T4.

Fig.2.2. General Bus operation cycle

2.3 System Bus timings: Minimum mode 8086 system and timings

In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum

mode by strapping its MN/MX* pin to logic1. In this mode, all the control signals are given
out by the microprocessor chip itself. There is a single microprocessor in the minimum mode
system. The remaining components in the system are latches, transreceivers, clock generator,
memory and I/O devices.
The opcode fetch and read cycles are similar. Hence the timing diagram can be
categorized in two parts, the first is the timing diagram for read cycle and the second is the
timing diagram for write cycle.
Fig 1.2 shows the read cycle timing diagram. The read cycle begins in T1 with the
assertion of the address latch enable (ALE) signal and also M/IO* signal. During the
negative going edge of this signal, the valid address is latched on the local bus. The BHE*
and A0 signals address low, high or both bytes. From Tl to T4, the M/IO* signal indicates a
memory or I/O operation. At T2 the address is removed from the local bus and is sent to the
output. The bus is then tristated. The read (RD*) control signal is also activated in T2 .The
read (RD) signal causes the addressed device to enable its data bus drivers. After RD* goes
low, the valid data is available on the data bus. The addressed device will drive the READY
line high, when the processor returns the read signal to high level, the addressed device will
again tristate its bus drivers.
 Fig 2.3. Minimum Mode 8086 System

A write cycle also begins with the assertion of ALE and the emission of the address. The
M/IO* signal is again asserted to indicate a memory or I/O operation. In T2 after sending the
address in Tl the processor sends the data to be written to the addressed location. The data
remains on the bus until middle of T4 state. The WR* becomes active at the beginning ofT2
(unlike RD* is somewhat delayed in T2 to provide time for floating). The BHE* and A0
signals are used to select the proper byte or bytes of memory or I/O word to be read or
written. The M/IO*, RD* and WR* signals indicate the types of data transfer as specified in
Table
Table 2.5 Read write cycle
 Fig. 2.4 Read cycle timing diagram for minimum mode

Fig 2.5 Bus request and busgrant timings in minimum mode system

2.3 System Design using 8086: Maximum mode 8086 system and timings

In the maximum mode, the 8086 is operated by strapping the MN/MX* pin to ground. In this
mode, the processor derives the status signals S2*, S1* and S0*. Another chip called bus
controller derives the control signals using this status information. In the maximum mode,
there may be more than one microprocessor in the system configuration.
The basic functions of the bus controller chip IC8288, is to derive control signals like
RD* and WR* (for memory and I/O devices), DEN*, DT/R*, ALE, etc. using the
information made available by the processor on the status lines. The bus controller chip has
input lines S2*, S1* and S0* and CLK. These inputs to 8288 are driven by the CPU. It
derives the outputs ALE, DEN*, DT/R*, MWTC*, AMWC*, IORC*, IOWC* and
AIOWC*. The AEN*, IOB and CEN pins are especially useful for multiprocessor systems.
AEN* and IOB are generally grounded. CEN pin is usually tied to +5V.

Fig. 2.6 Maximum mode configuiration

The significance of the MCE/PDEN* output depends upon the status of the IOB pin. If IOB
is grounded, it acts as master cascade enable to control cascaded 8259A; else it acts as
peripheral data enable used in the multiple bus configurations.
INTA* pin is used to issue two interrupt acknowledge pulses to the interrupt
controller or to an interrupting device.
IORC*, IOWC* are I/O read command and I/O write command signals respectively.
These signals enable an IO interface to read or write the data from or to the addressed port.
The MRDC*, MWTC* are memory read command and memory write command signals
respectively and may be used as memory read and write signals. All these command signals
instruct the memory to accept or send data from or to the bus.
For both of these write command signals, the advanced signals namely AIOWC* and
AMWTC* are available. They also serve the same purpose, but are activated one clock cycle
earlier than the IOWC* and MWTC* signals, respectively. The maximum mode system is
shown in fig. 2.1.
The maximum mode system timing diagrams are also divided in two portions as read (input)
and write (output) timing diagrams. The address/data and address/status timings are similar
to the minimum mode. ALE is asserted in T1, just like minimum mode. The only difference
lies in the status signals used and the available control and advanced command signals. The
fig. 1.2 shows the maximum mode timings for the read operation while the fig. 1.3 shows
the same for the write operation.
 Fig.2.7 Memory read cycle

Fig.2.8 Memory write cycle

Fig 2.9 RG*/GT* Timings in maximum mode

2.5 IO programming

On the 8086, all programmed communications with the I/O ports is done by the IN and
OUT instructions defined in Fig. 6-2.

✓ IN and OUT instructions

 Name Mnemonic and Format Description
Input
Long form, byte IN AL, PORT (AL) <- (PORT)
Long form, word IN AX, PORT (AX) <- (PORT+1: PORT)
Short form, byte IN AL, DX (AL) <- ((DX))
Short form, word IN AX, DX (AX) <- ((DX) + 1: (DX))
Output
Long form, byte OUT PORT, AL (PORT) <- (AL)
Long form, word OUT PORT, AX (PORT+1: PORT) <- (AX)
Short form, byte OUT DX, AL ((DX)) <- (AL)
Short form, word OUT DX, AX ((DX)+1: (DX)) <- (AX)

Note: PORT is a constant ranging from 0 to 255

Flags: No flags are affected
Addressing modes: Operands are limited as indicated above.

If the second operand is DX, then there is only one byte in the instruction and the contents
of DX are used as the port address. Unlike memory addressing, the contents of DX are not
modified by any segment register. This allows variable access to I/O ports in the range 0 to
64K. The machine language code for the IN instruction is:

Although AL or AX is implied as the first operand in an IN instruction, either AL or AX

must be specified so that the assembler can determine the W-bit.

Similar comments apply to the OUT instruction except that for it the port address is the
destination and is therefore indicated by the first operand, and the second operand is either
AL or AX. Its machine code is:

Note that if the long form of the IN or OUT instruction is used the port address must be in
the range 0000 to 00FF, but for the short form it can be any address in the range 0000 to
FFFF (i.e. any address in the I/O address space). Neither IN nor OUT affects the flags.

The IN instruction may be used to input data from a data buffer register or the status from a
status register. The instructions

IN AX, 28H
MOV DATA_WORD, AX
would move the word in the ports whose address are 0028 and 0029 to the memory
location DATA_WORD.
 2.6 Introduction to Multiprogramming
In order to adapt to as many situations as possible both the 8086 and 8088 have been given
two modes of operation, the minimum mode and the maximum mode. The minimum mode
is used for a small system with a single processor, a system in which the 8086/8088
generates all the necessary bus control signals directly (thereby minimizing the required
bus control logic). The maximum mode is for medium-size to large systems, which often
include two or more processors.
2.7 System Bus structure

Fig.2.10 Typical system Bus architecture

Table 2.6 Pins for read/ write operation

2.8 Multiprocessor Systems

Multiprocessor Systems refer to the use of multiple processors that execute instructions
simultaneously and communicate using mailboxes and semaphores
Maximum mode of 8086 is designed to implement 3 basic multiprocessor
configurations:
1. Coprocessor (8087)
2. Closely coupled (dedicated I/O processor: 8089)

3. Loosely coupled (Multi bus)

 Coprocessors and closely coupled configurations are similar - both the CPU and the
external processor share:

Memory
I/O system
Bus & bus control logic
Clock generator

2.9 Coprocessor configurations

Coprocessor Configuration:
WAIT instruction allows the processor to synchronize itself with external
hardware, eg., waiting for 8087 math co-processor.
When the CPU executes WAIT
waiting state.

TEST input is asserted (low), the waiting state is completed and execution will resume.
ESC instruction:
ESC opcode, operand, opcode: immediate value recognizable to a coprocessor as an
instruction opcode
Operand: name of a register or a memory address (in any mode)
When the CPU executes the ESC instruction, the processor accesses the memory
operand by placing the address on the address bus.
If a coprocessor is configured to share the system bus, it will recognize the ESC
instruction and therefore will get the opcode and the operand

Fig. 2.11 Synchronisation between the 8086 and its coprocesssor

Fig 2.12 Machine code formats for the ESC instruction

Fig.2.13 Coprocessor configuration

 Fig.2.14 closely coupled configuration

✓ Coprocessor cannot take control of the bus, it does everything through the CPU
✓ Closely Coupled processor may take control of the bus independently - 8089 shares
CPU’s clock and bus control logic.
✓ communication with host CPU is by way of shared memory
✓ host sets up a message (command) in memory
✓ independent processor interrupts host on completion
✓ Two 8086’s cannot be closely coupled

2.10 Closely Coupled Configuration

Fig.2.15 Interprocessor communication through shared memory

 Fig.2.16 Bus allocation schemes
Loosely Coupled Configurations:
A loosely coupled configuration provides the following advantages:
1. High system throughput can be achieved by having more than one CPU.
2. The system can be expanded in a modular form. Each bus master module is an
independent unit and normally resides on a separate PC board. Therefore, a bus
master module can be added or removed without affecting the other modules in the
system.
3. A failure in one module normally does not cause a breakdown of the entire system
and the faulty module can be easily detected and replaced.
 4. Each bus master may have a local bus to access dedicated memory or I/O devices
so that a greater degree of parallel processing can be achieved. More than one bus
master module may have access to the shared system bus
Extra bus control logic must be provided to resolve the bus arbitration
problem. The extra logic is called bus access logic and it is its responsibility to
make sure that only one bus master at a time has control of the bus.
Simultaneous bus requests are resolved on a priority basis: There are three schemes
for establishing priority:
1. Daisy chaining.
2. Polling.
3. Independent requesting

2.11 Introduction to Advanced processors: 80286 Microprocessor

2.11.1 Salient Features of 80286
✓ The 80286 is the first member of the family of advanced microprocessors with
memory management and protection abilities. The 80286 CPU, with its 24-bit address bus is
able to address 16 Mbytes of physical memory. Various versions of 80286 are available that
runs on 12.5 MHz, 10 MHz and 8 MHz clock frequencies. 80286 is upwardly compatible
with 8086 in terms of instruction set.
✓ 80286 has two operating modes namely real address mode and virtual address mode.
In real address mode, the 80286 can address upto 1Mb of physical memory address
like 8086. In virtual address mode, it can address up to 16 Mb of physical memory
address space and 1 GB of virtual memory address space.
✓ The instruction set of 80286 includes the instructions of 8086 and 80186. 80286 has
some extra instructions to support operating system and memory management. In
real address mode, the 80286 is object code compatible with 8086. In protected
virtual address mode, it is source code compatible with 8086. The performance of
80286 is five times faster than the standard 8086.
2.11.1 Need for Memory Management
The part of main memory in which the operating system and other system programs are
stored is not accessible to the users. It is required to ensure the smooth execution of the
running process and also to ensure their protection. The memory management which is an
important task of the operating system is supported by a hardware unit called memory
management unit.
Swapping in of the Program
Fetching of the application program from the secondary memory and placing it in the
physical memory for execution by the CPU.
Swapping out of the executable Program
Saving a portion of the program or important results required for further execution back to
the secondary memory to make the program memory free for further execution of another
required portion of the program.
2.11.2 Concept of Virtual Memory
Large application programs requiring memory much more than the physically available 16
Mbytes of memory, may be executed by diving it into smaller segments. Thus for the user,
there exists a very large logical memory space which is not actually available. Thus there
exists a virtual memory which does not exist physically in a system. This complete process
of virtual memory management is taken care of
by the 80286 CPU and the supporting operating system.
2.11.3 Internal Architecture of 80286
Register Organization of 80286
The 80286 CPU contains almost the same set of registers, as in 8086, namely
1. Eight 16-bit general purpose registers
2. Four 16-bit segment registers

3. Status and control registers

 4.Instruction Pointer

Fig.2.17 Register set of 80286

Fig 2.18 Flag registers

D2, D4, D6, D7 and D11 are called as status flag bits. The bits D8 (TF) and D9 (IF) are used
for controlling machine operation and thus they are called control flags. The additional
fields available in 80286 flag registers are:
1. IOPL - I/O Privilege Field (bits D12 and D13)
2. NT - Nested Task flag (bit D14)
3. PE - Protection Enable (bit D16)
4. MP - Monitor Processor Extension (bit D17)
5. EM - Processor Extension Emulator (bit D18)
6. TS – Task Switch (bit D19)
Protection Enable flag places the 80286 in protected mode, if set. This can only be cleared
by resetting the CPU. If the Monitor Processor Extension flag is set, allows WAIT
instruction to generate a processor extension not present exception.
Processor Extension Emulator flag if set, causes a processor extension absent exception and
permits
the emulation of processor extension by the CPU.
Task Switch flag if set, indicates the next instruction using extension will generate
exception 7, permitting the CPU to test whether the current processor extension is for the
current task.
Machine Status Word (MSW)
The machine status word consists of four flags – PE, MO, EM and TS of the four lower
order bits D19 to D16 of the upper word of the flag register. The LMSW and SMSW
instructions are available in the instruction set of 80286 to write and read the MSW in real
address mode.
2.11.4 Internal Block Diagram of 80286

Fig. 2.19 Internal Block diagram of 80286

The CPU contain four functional blocks

1. Address Unit (AU)
2. Bus Init (BU)
3. Instruction Unit (IU)
4. Execution Unit (EU)
The address unit is responsible for calculating the physical address of instructions and data
that the CPU wants to access. Also the address lines derived by this unit may be used to
address different peripherals. The physical address computed by the address unit is handed
over to the bus unit (BU) of the CPU. Major function of the bus unit is to fetch instruction
bytes from the memory. Instructions are fetched in advance and stored in a queue to enable
faster execution of the instructions. The bus unit also contains a bus control module that
controls the prefetcher module. These prefetched instructions are arranged in a 6-byte
instructions queue. The 6-byte prefetch queue forwards the instructions arranged in it to the
instruction unit (IU). The instruction unit accepts instructions from the prefetch queue and
an instruction decoder decodes
them one by one. The decoded instructions are latched onto a decoded instruction queue.
The output of the decoding circuit drives a control circuit in the execution unit, which is
responsible for executing the instructions received from decoded instruction queue. The
decoded instruction queue sends the data part of the instruction over the data bus. The EU
contains the register bank used for storing the data as scratch pad, or used as special purpose
registers. The ALU, the heart of the EU, carries out all the arithmetic and logical operations
and sends the results over the data bus or back to the register bank.
2.11.5 Interrupts of 80286
The Interrupts of 80286 may be divided into three categories,
1. External or hardware interrupts
2. INT instruction or software interrupts
3. Interrupts generated internally by exceptions
While executing an instruction, the CPU may sometimes be confronted with a special
situation because of which further execution is not permitted. While trying to execute a
divide by zero instruction, the CPU detects a major error and stops further execution. In
this case, we say that an exception has been generated. In other words, an instruction
exception is an unusual situation encountered during execution of an instruction that
stops further execution. The return address from an exception, in most of the cases,
points to the instruction that caused the exception.
As in the case of 8086, the interrupt vector table of 80286 requires 1Kbytes of space for
storing 256, four-byte pointers to point to the corresponding 256 interrupt service routines
(lSR). Each pointer contains a 16-bit offset followed by a 16-bit segment selector to point to
a particular ISR. The calculation of vector pointer address in the interrupt vector table from
the (8-bit) INT type is exactly similar to 8086.
Like 8086, the 80286 supports the software interrupts of type 0 (INT 00) to type FFH (INT
FFH).
Maskable Interrupt INTR: This is a maskable interrupt input pin of which the INT type is
to be provided by an external circuit like an interrupt controller. The other functional details
of this interrupt pin are exactly similar to the INTR input of 8086. Non-Maskable
Interrupt NMI: It has higher priority than the INTR interrupt.
Whenever this interrupt is received, a vector value of 02 is supplied internally to calculate
the pointer to the interrupt vector table. Once the CPU responds to a NMI request, it does
not serve any other interrupt request (including NMI). Further it does not serve the
processor extension (coprocessor) segment overrun interrupt, till either it executes IRET or
it is reset. To start with, this clears the IF flag which is set again with the execution of IRET,
i.e. return from interrupt.
Single Step Interrupt
As in 8086, this is an internal interrupt that comes into action, if trap flag (TF) of 80286 is
set. The CPU stops the execution after each instruction cycle so that the register contents
(including flag register), the program status word and memory, etc. may be examined at the
end of each instruction execution. This interrupt is useful for troubleshooting the software.
An interrupt vector type 01 is reserved for this interrupt.
Interrupt Priorities:
If more than one interrupt signals occur simultaneously, they are processed according to
their priorities as shown below:
2.11.6 Signal Description of 80286
CLK: This is the system clock input pin. The clock frequency applied at this pin is divided
by two internally and is used for deriving fundamental timings for basic operations of the
circuit. The clock is generated using 8284 clock generator. D15-D0: These are sixteen
bidirectional data bus lines.
A23-A0: These are the physical address output lines used to address memory or I/O devices.
The address lines A23 - A16 are zero during I/O transfers
BHE: This output signal, as in 8086, indicates that there is a transfer on the higher byte of
the data bus (D15 – D8) .
S1 , S0: These are the active-low status output signals which indicate initiation of a bus
cycle and with M/IO and COD/INTA, they define the type of the bus cycle.
M/ IO: This output line differentiates memory operations from I/O operations. If this signal
is it “0” indicates that an I/O cycle or INTA cycle is in process and if it is “1” it indicates
that a memory or a HALT cycle is in progress.
COD/ INTA: This output signal, in combination with M/ IO signal and S1 , S0
distinguishes different memory, I/O and INTA cycles.
LOCK: This active-low output pin is used to prevent the other masters from gaining the
control of the bus for the current and the following bus cycles. This pin is activated by a
"LOCK" instruction prefix, or automatically by hardware during XCHG, interrupt
acknowledge or descriptor table access
READY This active-low input pin is used to insert wait states in a bus cycle, for interfacing
low speed peripherals. This signal is neglected during HLDA cycle.
HOLD and HLDA This pair of pins is used by external bus masters to request for the
control of the system bus (HOLD) and to check whether the main processor has granted the
control (HLDA) or not, in the same way as it was in 8086.
INTR: Through this active high input, an external device requests 80286 to suspend the
current instruction execution and serve the interrupt request. Its function is exactly similar to
that of INTR pin of 8086.
NMI: The Non-Maskable Interrupt request is an active-high, edge-triggered input that is
equivalent to an INTR signal of type 2. No acknowledge cycles are needed to be carried out.
PEREG and PEACK (Processor Extension Request and Acknowledgement)
Processor extension refers to coprocessor (80287 in case of 80286 CPU). This pair of pins
extends the memory management and protection capabilities of 80286 to the processor
extension 80287. The PEREQ input requests the 80286 to perform a data operand transfer
for a processor extension. The PEACK active-low output indicates to the processor
extension that the requested operand is being transferred.
BUSY and ERROR: Processor extension BUSY and ERROR active-low input signals
indicate the operating conditions of a processor extension to 80286. The BUSY goes low,
indicating 80286 to suspend the execution and wait until the BUSY become inactive. In this
duration, the processor extension is busy with its allotted job. Once the job is completed the
processor extension drives the BUSY input high indicating 80286 to continue with the
program execution. An active ERROR signal causes the 80286 to perform the processor
extension interrupt while executing the WAIT and ESC instructions. The active ERROR
signal indicates to 80286 that the processor extension has committed a mistake and hence it
is reactivating the processor extension interrupt.
CAP: A 0.047 μf, 12V capacitor must be connected between this input pin and ground to
filter the output of the internal substrate bias generator. For correct operation of 80286 the
capacitor must be charged to its operating voltage. Till this capacitor charges to its full
capacity, the 80286 may be kept stuck to reset to avoid any spurious activity. Vss: This pin is
a system ground pin of 80286.
Vcc: This pin is used to apply +5V power supply voltage to the internal circuit of 80286.
RESET The active-high RESET input clears the internal logic of 80286, and reinitializes it
RESET The active-high reset input pulse width should be at least 16 clock cycles. The
80286 requires at least 38 clock cycles after the trailing edge of the RESET input signal,
before it makes the first opcode fetch cycle.

2.11.7 Real Address Mode

• Act as a fast 8086
• Instruction set is upwardly compatible
• It address only 1 M byte of physical memory using A0-A19.
• In real addressing mode of operation of 80286, it just acts as a fast 8086. The
instruction set is upward compatible with that of 8086.
The 80286 addresses only 1Mbytes of physical memory using A0- A19. The lines A20-A23
are not used by the internal circuit of 80286 in this mode. In real address mode, while
addressing the physical memory, the 80286 uses BHE along with A0- A19. The 20-bit
physical address is again formed in the same way as that in 8086.
The contents of segment registers are used as segment base addresses. The other
registers, depending upon the addressing mode, contain the offset addresses. Because of
extra pipelining and other circuit level improvements, in real address mode also, the 80286
operates at a much faster rate than 8086, although functionally they work in an identical
fashion. As in 8086, the physical memory is organized in terms of segments of 64Kbyte
maximum size.
An exception is generated, if the segment size limit is exceeded by the instruction or
the data. The overlapping of physical memory segments is allowed to minimize the memory
requirements for a task. The 80286 reserves two fixed areas of physical memory for system
initialization and interrupt vector table. In the real mode the first 1Kbyte of memory starting
from address 0000H to 003FFH is reserved for interrupt vector table. Also the addresses
from FFFF0H to FFFFFH are reserved for system initialization.
The program execution starts from FFFFH after reset and initialization. The interrupt
vector table of 80286 is organized in the same way as that of 8086. Some of the interrupt
types are reserved for exceptions, single-stepping and processor extension segment overrun,
etc
When the 80286 is reset, it always starts the execution in real address mode. In real
address mode, it performs the following functions: it initializes the IP and other registers of
80286, it prepares for entering the protected virtual address mode.
 Fig 2.20 Real Address calculation

2.11.8 Protected Virtual Address Mode (PVAM)

80286 is the first processor to support the concepts of virtual memory and memory
management. The virtual memory does not exist physically it still appears to be available
within the system. The concept of VM is implemented using Physical memory that the CPU
can directly access and secondary memory that is used as a storage for data and program,
which are stored in secondary memory initially.
The Segment of the program or data required for actual execution at that instant is
fetched from the secondary memory into physical memory. After the execution of this
fetched segment, the next segment required for further execution is again fetched from the
secondary memory, while the results of the executed segment are stored back into the
secondary memory for further references. This continues till the complete program is
executed
During the execution the partial results of the previously executed portions are again
fetched into the physical memory, if required for further execution. The procedure of
fetching the chosen program segments or data from the secondary storage into physical
memory is called swapping. The procedure of storing back the partial results or data back on
the secondary storage is called unswapping. The virtual memory is allotted per task.
The 80286 is able to address 1 G byte (230 bytes) of virtual memory per task. The
complete virtual memory is mapped on to the 16Mbyte physical memory. If a program
larger than 16Mbyte is stored on the hard disk and is to be executed, if it is fetched in terms
of data or program segments of less than 16Mbyte in size into the program memory by
swapping sequentially as per sequence of execution.
Whenever the portion of a program is required for execution by the CPU, it is
fetched from the secondary memory and placed in the physical memory is called swapping
in of the program. A portion of the program or important partial results required for further
execution, may be saved back on secondary storage to make the PM free for further
execution of another required portion of the program is called swapping out of the
executable program.
80286 uses the 16-bit content of a segment register as a selector to address a
descriptor stored in the physical memory. The descriptor is a block of contiguous memory
locations containing information of a segment, like segment base address, segment limit,
segment type, privilege level, segment availability in physical memory, descriptor type and
segment use another task.
 UNIT III
IO INTERFACING
Memory Interfacing and I/O interfacing - Parallel communication interface – Serial
communication interface – D/A and A/D Interface - Timer – Keyboard /display controller – Interrupt
controller – DMA controller – Programming and applications Case studies: Traffic Light control, LED
display , LCD display, Keyboard display interface and Alarm Controller

Interfacing

Interface is the path for communication between two components. Interfacing is of two types, memory
interfacing and I/O interfacing.

Memory Interfacing
When we are executing any instruction, we need the microprocessor to access the memory for reading
instruction codes and the data stored in the memory. For this, both the memory and the microprocessor
requires some signals to read from and write to registers.

The interfacing process includes some key factors to match with the memory requirements and
microprocessor signals. The interfacing circuit therefore should be designed in such a way that it
matches the memory signal requirements with the signals of the microprocessor.

IO Interfacing
There are various communication devices like the keyboard, mouse, printer, etc. So, we need to interface
the keyboard and other devices with the microprocessor by using latches and buffers. This type of
interfacing is known as I/O interfacing.

Block Diagram of Memory and I/O Interfacing

Few interfacing chips of 8085 and 8086

• Memory Interfacing & I/O interfacing
• Parallel communication interface {8255 PPI}
• Serial communication interface {8251 USART}
• D/A and A/D Interface {ADC 0800/0809,DAC 0800}
• Timer {or counter} {8253/8254 Timer}
• Keyboard /display controller {8279}
• Interrupt controller {8259}
• DMA controller {8237/8257}

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PARALLEL COMMUNICATION INTERFACE: 8255 (PROGRAMMABLE PERIPHERAL
INTERFACE AND INTERFACING)
The 8255 is a widely used, programmable parallel I/O device. It can be programmed to transfer data
under data under various conditions, from simple I/O to interrupt I/O. It is an important general purpose
I/O device that can be used with almost any microprocessor.
The 8255 has 24 I/O pins that can be grouped primarily into two 8 bit parallel ports: A and B, with the
remaining 8 bits as Port C. The 8 bits of port C can be used as individual bits or be grouped into two 4 bit
ports: CUpper (CU) and CLower (CL). The functions of these ports are defined by writing a control
word in the control register.
8255 can be used in two modes: Bit set/Reset (BSR) mode and I/O mode.
• The BSR mode is used to set or reset the bits in port C.
• The I/O mode is further divided into 3 modes:
➢
mode 0- all ports function as simple I/O ports
➢
mode 1 - a handshake mode whereby Port A and/or Port B use bits from Port C
as handshake signals
➢
mode 2- Port A can be set up for bidirectional data transfer using handshake
signals from Port C, and Port B can be set up either in mode 0 or mode 1.
PIN DETAILS

The signal description of 8255 is briefly presented as follows: PA7-PA0: These are eight port A lines that
acts as either latched output or buffered input lines depending upon the control word loaded into the
control word register.
PC7-PC4: Upper nibble of port C lines. They may act as either output latches or input buffers lines. This
port also can be used for generation of handshake lines in mode 1 or mode 2.
PC3-PC0: These are the lower port C lines, other details are the same as PC7-PC4 lines.
2 Dr.P.Durgadevi AP/RMKCET
PB0-PB7: These are the eight port B lines which are used as latched output lines or buffered input lines
in the same way as port A.
RD: This is the input line driven by the microprocessor and should be low to indicate read operation to
8255.
WR: This is an input line driven by the microprocessor. A low on this line indicates write operation.
CS: This is a chip select line. If this line goes low, it enables the 8255 to respond to RD and WR signals,
otherwise RD and WR signal are neglected.
A1-A0: These are the address input lines and are driven by the microprocessor. These lines A1-A0 with
RD, WR and CS from the following operations for 8255. In case of 8086 systems, if the 8255 is to be
interfaced with lower order data bus, the A0 and A1 pins of 8255 are connected with A1 and A2
respectively.
D0-D7: These are the data bus lines those carry data or control word to/from the microprocessor.
RESET: A logic high on this line clears the control word register of 8255. All ports are set as input ports
by default after reset.
8255 Block Diagram:

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Data Bus Buffer-This three-state bi-directional 8-bit buffer is used to interface the 8255 to the system
data bus. Data is transmitted or received by the buffer upon execution of input or output instructions by
the CPU. Control words and status informa-tion are also transferred through the data bus buffer.
Read/Write and Control Logic
The function of this block is to manage all of the internal and external transfers of both Data and Control
or Status words. It accepts inputs from the CPU Address and Control busses and in turn, issues commands
to both of the Control Groups.

4 Dr.P.Durgadevi AP/RMKCET
 ➢
(CS) Chip Select. A "low" on this input pin enables the communication between the 8255
and the CPU.
➢
(RD) Read. A "low" on this input pin enables 8255 to send the data or status information
to the CPU on the data bus. In essence, it allows the CPU to "read from" the 8255.
➢
(WR) Write. A "low" on this input pin enables the CPU to write data or control words
into the 8255.
➢
(A0 and A1) Port Select 0 and Port Select 1. These input signals, in conjunction with the
RD and WR inputs, control the selection of one of the three ports or the control word
register. They are normally connected to the least significant bits of the address bus (A0
and A1).
➢
(RESET) Reset. A "high" on this input initializes the control register to 9Bh and all ports
(A, B, C) are set to the input mode.

A1 A0 SELECTION

0 0 PORT A

0 1 PORT B

1 0 PORT C

1 1 CONTROL

Group A and Group B Controls

The functional configuration of each port is programmed by the systems software. Each of the Control
blocks (Group A and Group B) accepts "commands" from the Read/Write Control logic, receives "control
words" from the internal data bus and issues the proper commands to its associated ports.
Ports A, B, and C
The 8255 contains three 8-bit ports (A, B, and C). All can be configured to a wide variety of functional
characteristics by the system software but each has its own special features or "personality" to further
enhance the power and flexibility of the 8255.
➢
Port A One 8-bit data output latch/buffer and one 8-bit data input latch. Both "pull-up" and "pull-
down" bus-hold devices are present on Port A.
➢
Port B One 8-bit data input/output latch/buffer and one 8-bit data input buffer.
➢
Port C One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input). This
port can be divided into two 4-bit ports under the mode control. Each 4-bit port contains a 4-bit
latch and it can be used for the control signal output and status signal inputs in conjunction with
ports A and B.
Operation modes of 8255:
The bit pattern loaded in control word register specifies an I/O function for each port and the mode of
operation in which the ports are to be used.

5 Dr.P.Durgadevi AP/RMKCET
There are two different control word formats which specify two basic modes:
• BSR (Bit set reset) mode
• I/O mode
The two basic modes are selected by D7 bit of control register. When D7=1 it is an I/O mode and when
D7=0; it is a BSR mode.
BSR mode-
1. The BSR mode is a port C bit set/reset mode.
2. The individual bit of port C can be set or reset by writing control word in the control register.
3. The control word format of BSR mode is as shown in the figure below

1. The pin of port C is selected using bit select bits [b b b] and set or reset is decided by bit S/R .̅
2. The BSR mode affects only one bit of port C at a time. The bit set using BSR mode remains set
unless and until you change the bit. So to set any bit of port C, bit pattern is loaded in control
register.
3. If a BSR mode is selected it will not affect I/O mode.

I/O modes
There are three I/O modes of operation:
• Mode 0- Basic I/O
• Mode 1- Strobed I/O
• Mode 2- Bi-directional I/O
The I/O modes are programmed using control register.
The control word format of I/O modes is as shown in the figure below:

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Function of each bit is as follows:
1. D7– When the bit D7 = 1 then I/O mode is selected, if D7=0 then BSR mode is selected. The
function of bits D0 to D6 is independent on mode (I/O mode or BSR mode).
2. D6 and D5-In I/O mode the bits D6 and D5 specifies the different I/O modes for group A i.e.
Mode 0, Mode 1 and Mode 2 for port A and port C upper.
3. D2 – In I/O mode the bit D2 specifies the different I/O modes for group B i.e. Mode 0 and Mode
1 for port
B and port C lower.
All the 3 modes i.e. Mode 0, Mode 1 and Mode 2 are only for group A ports, but for group B only 2
modes i.e. Mode 0 and Mode 1 are provided. When 8255 is reset, it will clear control word register
contents and all the ports are set to input mode. The ports of 8255 can be programmed for other modes by
sending appropriate bit pattern to control register.

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ü I/O Modes of 8255

Mode 0: Simple Input or Output

In this mode, Port A and Port B are used as two simple 8-bit I/O ports and Port C as two4-bit I/O ports.
Each port (or half-port, in case of Port C) can be programmed to function as simply an input port or an
output port. The input/output features in mode 0 are: Outputs are latched, Inputs are not latched. Ports do
not have handshake or interrupt capability.
Mode 1: Input or Output with handshake
In mode 1, handshake signals are exchanged between the microprocessor and peripherals prior to data
transfer. The ports (A and B) function as 8-bit I/O ports. They can be configured either as input or output
ports. Each port (Port A and Port B) uses 3 lines from port C as handshake signals. The remaining two

8 Dr.P.Durgadevi AP/RMKCET
lines of port C can be used for simple I/O functions. Input and output data are latched and Interrupt logic
is supported.
Mode 1: Input control signals

STB Strobe Input): This signal (active low) is generated by a peripheral device that it has transmitted a
byte of data. The 8255, in response to, generates IBF and INTR.
IBF (Input buffer full): This signal is an acknowledgement by the 8255 to indicate that the input latch
has received the data byte. This is reset when the microprocessor reads the data.
INTR (Interrupt Request): This is an output signal that may be used to interrupt the microprocessor.
This signal is generated if , IBF and INTE are all at logic 1.
INTE (Interrupt Enable): This is an internal flip-flop to a port and needs to be set to generate the INTR
signal. The two flip-flops INTEA and INTEB are set /reset using the BSR mode. The INTEA is enabled
or disabled through PC4, and INTEB is enabled or disabled through PC2.
(Output Buffer Full): This is an output signal that goes low when the microprocessor writes data into the
output latch of the 8255. This signal indicates to an output peripheral that new data is ready to be read. It
goes high again after the 8255 receives a signal from the peripheral.
(Acknowledge): This is an input signal from a peripheral that must output a low when the peripheral
receives the data from the 8255 ports.
INTR (Interrupt Request): This is an output signal, and it is set by the rising edge of the signal. This
signal can be used to interrupt the microprocessor to request the next data byte for output. The INTR is set
and INTE are all one and reset by the rising edge of . .

9 Dr.P.Durgadevi AP/RMKCET
 INTE (Interrupt Enable): This is an internal flip-flop to a port and needs to be set to generate the INTR
signal. The two flip-flops INTEA and INTEB are set /reset using the BSR mode. The INTEA signal can
be enabled or disabled through PC6, and INTEB is enabled or disabled through PC2.
Mode 2: Bidirectional Data Transfer
OBF This mode is used primarily in applications such as data transfer between the two computers or
floppy disk controller interface. Port A can be configured as the bidirectional port and Port B either in
mode 0 or mode 1. Port A uses five signals from Port C as handshake signals for data transfer. The
remaining three lines from Port C can be used either as simple I/O or as handshake signals for Port B.

SERIAL COMMUNICATION INTERFACE -PROGRAMMABLE COMMUINCATION

INTERFACE(INTEL 8251)

The 8251 is a programmable chip designed for synchronous and asynchronous serial data communication.

USART (Universal Synchronous/Asynchronous Receiver/Transmitter) is the key component for

converting parallel data to serial form and vice versa Two types of serial data communications are widely

used

• Asynchronous communications
• Synchronous communications

10 Dr.P.Durgadevi AP/RMKCET
Pin diagram of 8251

Block diagram of 8251

Signal Description of 8251
D 0 to D 7 (l/O terminal)
This is bidirectional data bus which receive control words and transmits data from the CPU and sends
status words and received data to CPU.
RESET (Input terminal)

11 Dr.P.Durgadevi AP/RMKCET
A "High" on this input forces the 8251 into "reset status." The device waits for the writing of "mode
instruction." The min. reset width is six clock inputs during the operating status of CLK.

12 Dr.P.Durgadevi AP/RMKCET
CLK (Input terminal)
CLK signal is used to generate internal device timing. CLK signal is independent of RXC or TXC.
However, the frequency of CLK must be greater than 30 times the RXC and TXC at Synchronous mode
and Asynchronous "x1" mode, and must be greater than 5 times at Asynchronous "x16" and "x64" mode.
WR (Input terminal)
This is the "active low" input terminal which receives a signal for writing transmit data and control words
from the CPU into the 8251.
RD (Input terminal)
This is the "active low" input terminal which receives a signal for reading receive data and status words
from the 8251.
C/D (Input terminal)
This is an input terminal which receives a signal for selecting data or command words and status words
when the 8251 is accessed by the CPU. If C/D = low, data will be accessed. If C/D = high, command
word or status word will be accessed.
CS (Input terminal)
This is the "active low" input terminal which selects the 8251 at low level when the CPU accesses. Note:
The device won’t be in "standby status"; only setting CS = High.
TXD (output terminal)
This is an output terminal for transmitting data from which serial-converted data is sent out. The device is
in "mark status" (high level) after resetting or during a status when transmit is disabled. It is also possible
to set the device in "break status" (low level) by a command.
TXRDY (output terminal)
This is an output terminal which indicates that the 8251is ready to accept a transmitted data character. But
the terminal is always at low level if CTS = high or the device was set in "TX disable status" by a
command. Note: TXRDY status word indicates that transmit data character is receivable, regardless of
CTS or command. If the CPU writes a data character, TXRDY will be reset by the leading edge or WR
signal.
TXEMPTY (Output terminal)
This is an output terminal which indicates that the 8251 has transmitted all the characters and had no data
character. In "synchronous mode," the terminal is at high level, if transmit data characters are no longer
remaining and sync characters are automatically transmitted. If the CPU writes a data character,
TXEMPTY will be reset by the leading edge of WR signal. Note : As the transmitter is disabled by
setting CTS "High" or command, data written before disable will be sent out. Then TXD and TXEMPTY
will be "High". Even if a data is written after disable, that data is not sent out and TXE will be
"High".After the transmitter is enabled, it sent out. (Refer to Timing Chart of Transmitter Control and
Flag Timing)

13 Dr.P.Durgadevi AP/RMKCET
TXC (Input terminal)
This is a clock input signal which determines the transfer speed of transmitted data. In "synchronous
mode," the baud rate will be the same as the frequency of TXC. In "asynchronous mode", it is possible to
select the baud rate factor by mode instruction. It can be 1, 1/16 or 1/64 the TXC. The falling edge of
TXC sifts the serial data out of the 8251.
RXD (input terminal)
This is a terminal which receives serial data.
RXRDY (Output terminal)
This is a terminal which indicates that the 8251 contains a character that is ready to READ. If the CPU
reads a data character, RXRDY will be reset by the leading edge of RD signal. Unless the CPU reads a
data character before the next one is received completely, the preceding data will be lost. In such a case,
an overrun error flag status word will be set.
RXC (Input terminal)
This is a clock input signal which determines the transfer speed of received data. In "synchronous mode,"
the baud rate is the same as the frequency of RXC. In "asynchronous mode," it is possible to select the
baud rate factor by mode instruction. It can be 1, 1/16, 1/64 the RXC.
SYNDET/BD (Input or output terminal)
This is a terminal whose function changes according to mode. In "internal synchronous mode." this
terminal is at high level, if sync characters are received and synchronized. If a status word is read, the
terminal will be reset. In "external synchronous mode, "this is an input terminal. A "High" on this input
forces the 8251 to start receiving data characters.
In "asynchronous mode," this is an output terminal which generates "high level"output upon the detection
of a "break" character if receiver data contains a "low-level" space between the stop bits of two
continuous characters. The terminal will be reset, if RXD is at high level. After Reset is active, the
terminal will be output at low level.
DSR (Input terminal)
This is an input port for MODEM interface. The input status of the terminal can be recognized by the
CPU reading status words.
DTR (Output terminal)
This is an output port for MODEM interface. It is possible to set the status of DTR by a command.
CTS (Input terminal)
This is an input terminal for MODEM interface which is used for controlling a transmit circuit. The
terminal controls data transmission if the device is set in "TX Enable" status by a command. Data is
transmittable if the terminal is at low level.
RTS (Output terminal)
This is an output port for MODEM interface. It is possible to set the status RTS by a command.
14 Dr.P.Durgadevi AP/RMKCET
The 8251 functional configuration is programed by software. Operation between the 8251 and a CPU is
executed by program control. Table 1 shows the operation between a CPU and the device.

Table 1 Operation between a CPU and 8251

Control Words
There are two types of control word.
1. Mode instruction (setting of function)
2. Command (setting of operation)
1) Mode Instruction
Mode instruction is used for setting the function of the 8251. Mode instruction will be in "wait for write"
at either internal reset or external reset. That is, the writing of a control word after resetting will be
recognized as a "mode instruction."
Items set by mode instruction are as follows:
• Synchronous/asynchronous mode
• Stop bit length (asynchronous mode)
• Character length
• Parity bit
• Baud rate factor (asynchronous mode)
• Internal/external synchronization (synchronous mode)
• Number of synchronous characters (Synchronous mode)
The bit configuration of mode instruction is shown in Figures 2 and 3. In the case of synchronous mode, it
is necessary to write one-or two byte sync characters. If sync characters were written, a function will be
set because the writing of sync characters constitutes part of mode instruction.

15 Dr.P.Durgadevi AP/RMKCET
2) Command
Command is used for setting the operation of the 8251. It is possible to write a command whenever
necessary after writing a mode instruction and sync characters. Items to be set by command are as
follows:
• Transmit Enable/Disable
• Receive Enable/Disable
• DTR, RTS Output of data.
• Resetting of error flag.
• Sending to break characters
• Internal resetting
• Hunt mode (synchronous mode)

16 Dr.P.Durgadevi AP/RMKCET
 Status Word
It is possible to see the internal status of the 8251 by reading a status word. The bit configuration of status
word is shown in Fig. 5.

PROGRAMMABLE INTERVAL TIMER (8253/8254)

The Intel 8253 and 8254 are Programmable Interval Timers (PTIs) designed for microprocessors to
perform timing and counting functions using three 16-bit registers. Each counter has 2 input pins, i.e.
Clock & Gate, and 1 pin for “OUT” output. To operate a counter, a 16-bit count is loaded in its register.
On command, it begins to decrement the count until it reaches 0, then it generates a pulse that can be
used to interrupt the CPU.

Difference between 8253 and 8254

8253 8254
Its operating frequency is 0 - 2.6 MHz Its operating frequency is 0 - 10 MHz
It uses N-MOS technology It uses H-MOS technology
Read-Back command is not available Read-Back command is available
Reads and writes of the same counter cannot be Reads and writes of the same counter can be
interleaved. interleaved.

a
Dept. Of CSE-RMKCET

17 Dr.P.Durgadevi AP/RMKCET
Features of 8253 / 54
The most prominent features of 8253/54 are as follows −

• It has three independent 16-bit down counters. These three counters can be programmed for
either binary or BCD count.
• It can handle inputs from DC to 10 MHz.
• It is compatible with almost all microprocessors.
• 8254 has a powerful command called READ BACK command, which allows the user to check
the count value, the programmed mode, the current mode, and the current status of the counter.
8254 Architecture and Pin Description
PIN DETAILS OF 8254

CS - Chip select .When it is low,enables the communication between CPU and 8253.
WR-When it is low,the CPU output data in the form of mode information are loading counters.
RD – When it is low,the CPU reads data.
A0-A1: These pins are connected to address bus. These are used to select one of the three counters.
D0-D7: These are tri-state bidirectional data bus used to interface 8253 to the system data bus.
CLK0,CLK1,CLK2-These are clock signals for counter0,counter1 and counter2.
GATE0,GATE1,GATE2- These are gate terminals for counter0, counter1 and counter2.
OUT0,OUT1,OUT2- These are output terminals for counter0, counter1 and counter2.

18 Dr.P.Durgadevi AP/RMKCET
 The architecture of 8254 looks as follows

In the above figure, there are three counters, a data bus buffer, Read/Write control logic, and a
control register. Each counter has two input signals - CLOCK & GATE, and one output signal - OUT.

Data Bus Buffer

It is a tri-state, bi-directional, 8-bit buffer, which is used to interface the 8253/54 to the system data bus.
It has three basic functions −

• Programming the modes of 8253/54.

• Loading the count registers.

• Reading the count values.

Read/Write Logic

It includes 5 signals, i.e. RD, WR, CS, and the address lines A0 & A1. In the peripheral I/O mode, the
RD and WR signals are connected to IOR and IOW, respectively. In the memory mapped I/O mode,
these are connected to MEMR and MEMW.

Address lines A0 & A1 of the CPU are connected to lines A0 and A1 of the 8253/54, and CS is tied to a
decoded address. The control word register and counters are selected according to the signals on lines
A0 & A1.
A1 A0 Result
0 0 Counter 0
0 1 Counter 1
1 0 Counter 2
1 1 Control Word Register
X X No Selection

19 Dr.P.Durgadevi AP/RMKCET
Control Word Register
This register is accessed when lines A0 & A1 are at logic 1. It is used to write a command word,
which specifies the counter to be used, its mode, and either a read or write operation.

Following table shows the result for various control inputs.

A1 A0 RD WR CS Result
0 0 1 0 0 Write Counter 0
0 1 1 0 0 Write Counter 1
1 0 1 0 0 Write Counter 2
1 1 1 0 0 Write Control Word
0 0 0 1 0 Read Counter 0
0 1 0 1 0 Read Counter 1
1 0 0 1 0 Read Counter 2
1 1 0 1 0 No operation
X X 1 1 0 No operation
X X X X 1 No operation

Counters
Each counter consists of a single, 16 bit-down counter, which can be operated in either binary or
BCD. Its input and output is configured by the selection of modes stored in the control word register.
The programmer can read the contents of any of the three counters without disturbing the actual count in
process.

Control Word Register:

Control Word Format
D7 D6 D5 D4 D3 D2 D1 D0

SC0 SC1 RL1 RL0 M2 M1 M0 BCD

When the pins A0,A1 are 11,the control word register is selected.
The bits D7 and D6 of the control word are to select one of the 3 counters.D5 and D4 are for loading
/reading the count.D3,D2 and D1 are for the selection of operating mode of the selected counter.

20 Dr.P.Durgadevi AP/RMKCET
Operation of 8253:

The complete functional definition of the 8253/54 is programmed by the system software. Once
programmed, the 8253/54 is ready to perform whatever timing tasks it is assigned to accomplish.

WRITE Operation:

1. Write a control word into control register.

2. Load the low-order byte of a count in the counter register.

3. Load the high-order byte of count in the counter register.

21 Dr.P.Durgadevi AP/RMKCET
EAD
the Operation
count : In This
in process. somecan
applications,
be done byespecially in event
three possible counters, it is necessary to read the value of
methods:
1. Simple Read : It involves reading a count after inhibiting the counter by controlling the gate
input or the clock input of the selected counter, and two I/O read operations are performed by the CPU. The
first I/O operation reads the low-order byte, and the second I/O operation reads the high order byte.

2. Counter Latch Command : In the second method, an appropriate control word is written
into the control register to latch a count in the output latch, and two I/O read operations are performed by
the CPU. The first I/O operation reads the low-order byte, and the second I/O operation reads the high
order byte.

3. Read-Back Command (Available only for 8254) : The third method uses the Read-Back
command. This command allows the user to check the count value, programmed Mode, and current
status of the OUT pin and Null count flag of the selected counter(s).

Below figure shows the format of the control word register for Read-Back command.

8254 Modes of Operation:

1.Mode 0 (Interrupt on terminal count)

2.Mode 1 (programmable Monoshot)

3.Mode 2 (Rate Generator)

4.Mode 3 (Square Wave Generator)

5.Mode 4 (Software Triggered Strobe)

6.Mode 5 (Hardware Triggered Strobe)

Mode 0 (Interrupt on terminal count)

22 Dr.P.Durgadevi AP/RMKCET
It is used to generate an interrupt to the microprocessor after pt to the microprocessor after a certain
interval of a certain interval of time. The output is initially low after the mode is set. The output
remains LOW after the count value is loaded in the counter.

The process of decrementing the counter continues till the terminal count is reached i.e., the
count becomes zero and output goes HIGH.The output remains high until it reloads a new mode of
operation or new count.

23 Dr.P.Durgadevi AP/RMKCET
 The GATE signal is high for normal counting .When GATE goes low counting is terminated
and the current count is latched till the GATE goes high again.

Mode 1: Programmable Monoshot

The 8253/8254 can be used as a monostable multivibrator.

The gate input is used as trigger input in this mode. Normally, the output remains high until the count
is loaded and a trigger is applied.

Mode 2: Rate Generator

➢
Divide by N Counter
➢
The output is normally high after initialization
➢
If N is loaded as the count value,after N pulses,the output becomes low for one clock
cycles.
➢
Whenever the count becomes zero another low pulse is generated at the output.

24 Dr.P.Durgadevi AP/RMKCET
Mode 3:Square wave rate generator
➢
It is similar to mode 2

➢
When the count N is loaded is EVEN,half of the count will be high and half of the count
will be low.
➢
When,the count N is loaded is ODD,the N+1/2 count will be high and N-1/2 will be low.

Mode 4: Software Triggered Strobe

➢
After the mode is set,the output goes high.

➢
The counter automatically begins to decrement (count down) one clock pulse after it is
loaded with the initial value is loaded.
➢
When the GATE signal goes low the count is latched

➢
Once the terminal count,the output goes low for one clock cycle and then again goes
high.this low pulse can be used a strobe.

25 Dr.P.Durgadevi AP/RMKCET
Mode 5: Hardware Triggered Strobe

This mode generates a strobe in response to an externally generated signal.It is similar to mode 4
except that the counting is initiated by a signal at the gate input.

After it is initialized,the output goes high.

The counter starts counting after the rising edge of the trigger input(GATE)

When the terminal count is reached,the output goes low for one clock cycle.

KEYBOARD /DISPLAY CONTROLLER 8279 - PROGRAMMABLE KEYBOARD CONTROLLER

8279 programmable keyboard/display controller is designed by Intel that interfaces a keyboard
with the CPU. The keyboard first scans the keyboard and identifies if any key has been pressed. It then
sends their relative response of the pressed key to the CPU and vice-a-versa.

How Many Ways the Keyboard is Interfaced with the CPU?

The Keyboard can be interfaced either in the interrupt or the polled mode.

In the Interrupt mode, the processor is requested service only if any key is pressed, otherwise the CPU
will continue with its main task.

In the Polled mode, the CPU periodically reads an internal flag of 8279 to check whether any key is
pressed or not with key pressure.

How Does 8279 Keyboard Work?

The keyboard consists of maximum 64 keys, which are interfaced with the CPU by using the key-codes.
These key-codes are de-bounced and stored in an 8-byte FIFO RAM, which can be accessed by the CPU.
If more than 8 characters are entered in the FIFO, then it means more than eight keys are pressed at a
time. This is when the overrun status is set.

26 Dr.P.Durgadevi AP/RMKCET
If a FIFO contains a valid key entry, then the CPU is interrupted in an interrupt mode else the CPU
checks the status in polling to read the entry. Once the CPU reads a key entry, then FIFO is updated, and
the key entry is pushed out of the FIFO to generate space for new entries.

Architecture and Description

I/O Control and Data Buffer

This unit controls the flow of data through the microprocessor. It is enabled only when D is low. Its data
buffer interfaces the external bus of the system with the internal bus of the microprocessor. The pins A0,
RD, and WR are used for command, status or data read/write operations.

Control and Timing Register and Timing Control

This unit contains registers to store the keyboard, display modes, and other operations as programmed by
the CPU. The timing and control unit handles the timings for the operation of the circuit.

Scan Counter
It has two modes i.e. Encoded mode and Decoded mode. In the encoded mode, the counter provides the
binary count that is to be externally decoded to provide the scan lines for the keyboard and display.

In the decoded scan mode, the counter internally decodes the least significant 2 bits and provides a
decoded 1 out of 4 scan on SL0-SL3.

Return Buffers, Keyboard Debounce, and Control

This unit first scans the key closure row-wise, if found then the keyboard debounce unit debounces the
key entry. In case, the same key is detected, then the code of that key is directly transferred to the sensor
RAM along with SHIFT & CONTROL key status.

27 Dr.P.Durgadevi AP/RMKCET
FIFO/Sensor RAM and Status Logic
This unit acts as 8-byte first-in-first-out (FIFO) RAM where the key code of every pressed key is entered
into the RAM as per their sequence. The status logic generates an interrupt request after each FIFO read
operation till the FIFO gets empty.

In the scanned sensor matrix mode, this unit acts as sensor RAM where its each row is loaded with the
status of their corresponding row of sensors into the matrix. When the sensor changes its state, the IRQ
line changes to high and interrupts the CPU.

Display Address Registers and Display RAM

This unit consists of display address registers which holds the addresses of the word currently
read/written by the CPU to/from the display RAM.

8279 − Pin Description

The following figure shows the pin diagram of 8279 −

Data Bus Lines, DB0 - DB7

These are 8 bidirectional data bus lines used to transfer the data to/from the CPU.

CLK
The clock input is used to generate internal timings required by the microprocessor.

28 Dr.P.Durgadevi AP/RMKCET
RESET
As the name suggests this pin is used to reset the microprocessor.

CS Chip Select
When this pin is set to low, it allows read/write operations, else this pin should be set to high.

A0
This pin indicates the transfer of command/status information. When it is low, it indicates the transfer of
data.

RD, WR
This Read/Write pin enables the data buffer to send/receive data over the data bus.

IRQ
This interrupt output line goes high when there is data in the FIFO sensor RAM. The interrupt line goes
low with each FIFO RAM read operation. However, if the FIFO RAM further contains any key-code
entry to be read by the CPU, this pin again goes high to generate an interrupt to the CPU.

Vss, Vcc
These are the ground and power supply lines of the microprocessor.

SL0 − SL3
These are the scan lines used to scan the keyboard matrix and display the digits. These lines can be
programmed as encoded or decoded, using the mode control register.

RL0 − RL7
These are the Return Lines which are connected to one terminal of keys, while the other terminal of the
keys is connected to the decoded scan lines. These lines are set to 0 when any key is pressed.

SHIFT
The Shift input line status is stored along with every key code in FIFO in the scanned keyboard mode.
Till it is pulled low with a key closure, it is pulled up internally to keep it high

CNTL/STB - CONTROL/STROBED I/P Mode

In the keyboard mode, this line is used as a control input and stored in FIFO on a key closure. The line is
a strobe line that enters the data into FIFO RAM, in the strobed input mode. It has an internal pull up.
The line is pulled down with a key closure.

BD
It stands for blank display. It is used to blank the display during digit switching.

OUTA0 – OUTA3 and OUTB0 – OUTB3

These are the output ports for two 16x4 or one 16x8 internal display refresh registers. The data from
these lines is synchronized with the scan lines to scan the display and the keyboard.

Operational Modes of 8279

There are two modes of operation on 8279 − Input Mode and Output Mode.

Input Mode

29 Dr.P.Durgadevi AP/RMKCET
This mode deals with the input given by the keyboard and this mode is further classified into 3 modes.

• Scanned Keyboard Mode − In this mode, the key matrix can be interfaced using either encoded
or decoded scans. In the encoded scan, an 8×8 keyboard or in the decoded scan, a 4×8 keyboard

30 Dr.P.Durgadevi AP/RMKCET
 can be interfaced. The code of key pressed with SHIFT and CONTROL status is stored into the
FIFO RAM.
1. Scanned Keyboard Mode with 2 Key Lockout
In this mode of operation, when a key is pressed, debounce logic comes into operation. The Key
code of the identified key is entered into the FIFO with SHIFT and CNTL status, provided the
FIFO is not full.
2. Scanned Keyboard with N-key Rollover
In this mode, each key depression is treated independently. When a key is pressed, the debounce
circuit waits for 2 keyboard scans and then checks whether the key is still depressed. If it is still
depressed, the code is entered in FIFO RAM. Any number of keys can be pressed simultaneously
and recognized in the order, the Keyboard scan record them.
3. Scanned Keyboard Special Error Mode
This mode is valid only under the N-Key rollover mode. This mode is programmed using end
interrupt/error mode set command. If during a single debounce period (two Keyboard scan) two
keys are found pressed, this is considered a simultaneous depression and an error flag is set. This
flag, if set, prevents further writing in FIFO but allows generation of further interrupts to the CPU
for FIFO read.

• Scanned Sensor Matrix − In this mode, a sensor array can be interfaced with the processor
using either encoder or decoder scans. In the encoder scan, 8×8 sensor matrix or with decoder
scan 4×8 sensor matrix can be interfaced.

• Strobed Input − In this mode, when the control line is set to 0, the data on the return lines is
stored in the FIFO byte by byte.

Output Mode
This mode deals with display-related operations. This mode is further classified into two output modes.

• Display Scan − This mode allows 8/16 character multiplexed displays to be organized as dual 4-
bit/single 8-bit display units.

• Display Entry − This mode allows the data to be entered for display either from the

o right entry (Calculator Type)

o left entry ( Type

Command Words of 8279
All the command words or status words are written or read with A0 = 1 and CS = 0 to or from 8279. This
section describes the various command available in 8279.
a) Keyboard Display Mode Set – The format of the command word to select different modes of
operation of 8279 is given below with its bit definitions.

31 Dr.P.Durgadevi AP/RMKCET
Read Display RAM :
This command enables a programmer to read the display RAM data. The CPU writes this command word
to 8279 to prepare it for display RAM read operation. AI is auto increment flag and AAAA, the 4-bit
address points to the 16-byte display RAM that is to be read. If AI=1, the address will be automatically,
incremented after each read or write to the Display RAM. The same address counter is used for reading
and writing.

Write Display RAM :

AI – Auto increment Flag.
AAAA – 4 bit address for 16-bit display RAM to be written.

Programmable Interrupt Controller- INTEL 8259A

The 8259A is a programmable interrupt controller specially designed to work with Intel
microprocessor 8080, 8085A, 8086, 8088. The main features of 8259A programmable interrupt
controller are given below:
1) It can handle eight interrupt inputs. This is equivalent to providing eight interrupt pins on
the processor in place of one INTR (in 8085A)/INT(in 8086) pin.
32 Dr.P.Durgadevi AP/RMKCET
2) It can resolve eight levels of interrupt priorities in a variety of modes. The priorities of
interrupts can be changed under running condition.

33 Dr.P.Durgadevi AP/RMKCET
 3) Each of the interrupt requests can be masked individually similar to RST7.5, RST6.5
and RST5.5 interrupts of 8085A.
4) The status of pending interrupts, in service interrupts, and masked interrupts can be read at
any time similar to RST interrupts of 8085A.
6) The chip can be programmed to accept interrupt requests either as level triggered or edge
triggered interrupt request unlike your RST interrupts where some are edge triggered and
some are level triggered. However, all interrupts must be either level triggered or edge
triggered.

Pin Configuration of Intel 8259A

The 8259 A is contained in a 28 dual-in-line package that requires only +5V supply
voltage. The 8259A is upward compatible with 8259. The main difference between the two is that
the 8259A can be used with Intel 8086/8088 processor. It also includes additional features such as
level triggered mode, buffered mode and automatic end of interrupt mode.

The pin diagram and internal block diagram of PIC is shown in figure. The pins are
defined as follows:

CS (Chip Select signal): To access this chip, chip select signal CS is made low. A LOW on this
pin enables RD & WR communication between the CPU and the 8259A. This signal is made
LOW by decoding the addresses assigned to this chip. Therefore, this pin is connected to address
bus through the decoder logic circuit. Interrupt acknowledge functions to transfer the control to
interrupt service subroutine are independent of CS.

34 Dr.P.Durgadevi AP/RMKCET
WR (Write signal): A low on this pin. When CS is low enables the 8259 A to accept command
words from CPU.

RD (Read signal): A low on this pin when CS is low enables this 8259A to release status
(pending interrupts or in-service interrupts or masked interrupts) on to the data bus for the CPU.
The status includes the contents of IMR (interrupt mask register) or ISR (interrupt service
register) or IRR (interrupt request register) or a priority level.

D7-D0 (Data Bus): Bidirectional data bus. Control, status and interrupt vector information is
transferred via this data bus. This bus is connected to BDB of 8085A.

CAS2-CAS0 (Cascade lines): The CAS2-0 lines form a local 8259A bus to control multiple 8259As
in master-slave configuration, i.e., to identify a particular slave 8259A to be accessed for transfer
of vector information. These pins are automatically set as output pins for master 8259A and input
pins for a slave 8259A once the chips are programmed as master or slave.

SP/ EN (Salve Program/Enable Buffer): This is a dual function pin. When the chip is
programmed in buffered mode, the pin can be used as an output and when not in the buffered
mode it is used as an input. In non-buffered mode it is used as an input pin to determine whether
the 8259A is to be used as a master (SP/ EN = 1) or as a slave (SP/ EN = 0).

INT (Interrupt output): This pin goes high whenever a valid interrupt request is asserted. It is
used to interrupt the CPU, thus it is connected to the CPU’s interrupt pin (INTR). In case of
master-slave
configuration, the interrupt pin of slave 8259A is connected to interrupt request input of master
8259A.

INTA (Interrupt Acknowledge): This pin is used to enable 8259A interrupt vector data on the
data bus by a sequence of interrupt acknowledge pulses issued by the CPU.
IR0-IR7 (Interrupt Request inputs): These are asynchronous interrupt request input pins. An
interrupt request is executed by raising an IR input (low to high), and holding it high until it is
acknowledged. (Edge triggered mode) or just by a high level on an interrupt request input (Level
triggered mode).

A0 (A0 address line): This pin acts in conjunction with the RD , WR & CS pins. It is used by the
8259A to send various command words from the CPU and to read the status. It is normally
connected to the CPU A0 address line. Two addresses are assigned/ reserved in the I/O address

35 Dr.P.Durgadevi AP/RMKCET
space for each 8259A in the system- one with A0 =0 is called even address and other with A0 = 1
is called odd address.

36 Dr.P.Durgadevi AP/RMKCET
 Functional Description:

The 8259A (PIC) has eight interrupt request inputs – IR7 - IR0. The 8259A uses its INT
output to interrupt the 8085A via INTR pin. The 8259A receives interrupt acknowledge pulses
from the at its INTA input. Vector address, used by the 8085A to transfer control to the service
subroutine of the interrupting device, is provided by the 8259A on the data bus. The 8259A is a
programmable device that must be initialized by command words sent by the microprocessor.
After initialization the 8259A mode of operation can be changed by operation command words
from the microprocessor.

It contains following blocks-

1. Data bus buffer-

• It is used to transfer data between microprocessor and internal bus.
1. Read/write logic-
• It sets the direction of data bus buffer.
• It controls all internal read/write operations.
• It contains initialization and operation command registers.
Cascaded buffer and comparator-
• In master mode, it functions as a cascaded buffer. The cascaded buffers outputs slave
identification number on cascade lines.
• In slave mode, it functions as a comparator. The comparator reads slave identification
number from cascade lines and compares this number with its internal identification number.

37 Dr.P.Durgadevi AP/RMKCET
 • In buffered mode, it generates an (EN) ̅signal.
Control logic-
• It generates an INT signal. In response to an (INTA) ̅signal, it releases three byte CALL address
or one byte vector number.
• It controls read/write control logic, cascade buffer/comparator, in service register,
priority resolver and IRR.
Interrupt request register-
• It is used to store all pending interrupt requests.
• Each bit of this register is set at the rising edge or at the high level of the corresponding
interrupt request line.
• The microprocessor can read contents of this register by issuing appropriate command word.
In service register (InSR)-
• It is used to store all interrupt levels currently being serviced.
• Each bit of this register is set by priority resolver and reset by end of interrupt command word.
• The microprocessor can read contents of this register by issuing appropriate command word.
Priority resolver-
• It determines the priorities of the bit set in the IRR. To make decision, the priority resolver
looks at the ISR.
• If the higher priority bit in the InSR is set then it ignores the new request.
• If the priority resolvers find that the new interrupt has a higher priority than the highest
priority interrupt currently being serviced and the new interrupt is not in service, then it will
set appropriate bit in the InSR and send the INT signal to the microprocessor for new interrupt
request.
Interrupt mask register (IMR)-
• It is a programmable register.
• It is used to mask unwanted interrupt request by writing appropriate command word.
• The microprocessor can read contents of this register without issuing any command word.

Priority modes of 8259

1.Fully Nested Modes

Default mode.
IR0 has the highest priority and IR7 has the lowest one.
If the ISR (in service) bit is set, all the same or lower priority interrupts are inhibited.

38 Dr.P.Durgadevi AP/RMKCET
2.End Of Interrupt
The ISR bit can be reset either with AEOI bit of ICW1 or by EOI command.
Two types of EOI command;
a)Specific
b)Non-specific
The non-specific EOI command automatically reset the highest ISR bit.
When a mode that may disturb the fully nested structure, the specific EOI command is issued to
reset a particular ISR bit.
An ISR bit that is masked by the corresponding IMR bit, will not be cleared by a non-
specific EOI , if it is in special mode.

3.Automatic Rotation

Used in the applications where , all the interrupting devices are of equal priority.
In this mode, an IR level receives lowest priority after it is served while the next device to
be served gets the highest priority in sequence.

4.Automatic EOI Mode

Till AEOI=1 in ICW4, 8259A operates in AEOI mode.

The 8259A performs a non- specific EOI at the trailing edge of the last /INTA pulse
automatically.
AEOI should be used only when a nested multilevel interrupt structure is not required.

5.Specific Rotation

A bottom priority level can be selected, using L2, L1 and L0 inOCW2 and R=1, SL=1,EOI=0.
The selected bottom priority fixes other priorities.
COMMAND AND STATUS WORD OF 8259

39 Dr.P.Durgadevi AP/RMKCET
40 Dr.P.Durgadevi AP/RMKCET
DMA CONTROLLER(8257): DIRECT MEMORY ACCESS

It is designed by Intel to transfer data at the fastest rate. It allows the device to transfer the data
directly to/from memory without any interference of the CPU.
Using a DMA controller, the device requests the CPU to hold its data, address and control bus, so the
device is free to transfer data directly to/from the memory. The DMA data transfer is initiated only
after receiving HLDA signal from the CPU.
How DMA Operations are Performed?

The sequence of operations performed by a DMA −

• Initially, when any device has to send data between the device and the memory, the device has
to send DMA request (DRQ) to DMA controller.
• The DMA controller sends Hold request (HRQ) to the CPU and waits for the CPU to assert
the HLDA.
• Then the microprocessor tri-states all the data bus, address bus, and control bus. The CPU
leaves the control over bus and acknowledges the HOLD request through HLDA signal.
• Now the CPU is in HOLD state and the DMA controller has to manage the operations over buses
between the CPU, memory, and I/O devices.

Features of 8257

• It has four channels which can be used over four I/O devices.
• Each channel has 16-bit address and 14-bit counter.
• Each channel can transfer data up to 64kb.
• Each channel can be programmed independently.
• Each channel can perform read transfer, write transfer and verify transfer operations.
• It operates in 2 modes, i.e., Master mode and Slave mode.

41 Dr.P.Durgadevi AP/RMKCET
8257 Pin Description

DRQ0−DRQ3
These are the four individual channel DMA request inputs, which are used by the peripheral devices for
using DMA services. When the fixed priority mode is selected, then DRQ0 has the highest priority and
DRQ3 has the lowest priority among them.
DACKo − DACK3
These are the active-low DMA acknowledge lines, which updates the requesting peripheral about the
status of their request by the CPU. These lines can also act as strobe lines for the requesting devices.
Do − D7
These are bidirectional, data lines which are used to interface the system bus with the internal data bus of
DMA controller. In the Slave mode, it carries command words to 8257 and status word from 8257. In the
master mode, these lines are used to send higher byte of the generated address to the latch. This address is
further latched using ADSTB signal.
IOR
It is an active-low bidirectional tri-state input line, which is used by the CPU to read internal registers of
8257 in the Slave mode. In the master mode, it is used to read data from the peripheral devices during a
memory write cycle.
IOW
It is an active low bi-direction tri-state line, which is used to load the contents of the data bus to the 8-bit
mode register or upper/lower byte of a 16-bit DMA address register or terminal count register. In the
master mode, it is used to load the data to the peripheral devices during DMA memory read cycle.
CLK
It is a clock frequency signal which is required for the internal operation of 8257.
RESET
This signal is used to RESET the DMA controller by disabling all the DMA channels.

Dept. Of CSE-RMKCET

42 Dr.P.Durgadevi AP/RMKCET
Ao - A3
These are the four least significant address lines. In the slave mode, they act as an input, which selects one
of the registers to be read or written. In the master mode, they are the four least significant memory
address output lines generated by 8257.
CS
It is an active-low chip select line. In the Slave mode, it enables the read/write operations to/from 8257. In
the master mode, it disables the read/write operations to/from 8257.
A4 - A7
These are the higher nibble of the lower byte address generated by DMA in the master mode.
READY
It is an active-high asynchronous input signal, which makes DMA ready by inserting wait states.
HRQ
This signal is used to receive the hold request signal from the output device. In the slave mode, it is
connected with a DRQ input line 8257. In Master mode, it is connected with HOLD input of the CPU.
HLDA
It is the hold acknowledgement signal which indicates the DMA controller that the bus has been granted
to the requesting peripheral by the CPU when it is set to 1.
MEMR
It is the low memory read signal, which is used to read the data from the addressed memory locations
during DMA read cycles.
MEMW
It is the active-low three state signal which is used to write the data to the addressed memory location
during DMA write operation.
ADST
This signal is used to convert the higher byte of the memory address generated by the DMA controller
into the latches.
AEN
This signal is used to disable the address bus/data bus.
TC
It stands for ‘Terminal Count’, which indicates the present DMA cycle to the present peripheral devices.
MARK
The mark will be activated after each 128 cycles or integral multiples of it from the beginning. It indicates
the current DMA cycle is the 128th cycle since the previous MARK output to the selected peripheral
device.
Vcc
It is the power signal which is required for the operation of the circuit.

43 Dr.P.Durgadevi AP/RMKCET
Internal Architecture of 8257:

Data Bus Buffer:

The 8-bit. Tristate, bidirectional buffer interfaces the internal bus of 8257 with the external system

bus under the control of various control signals.

Read/Write Logic:

In the slave mode, the read/write logic accepts the I/O Read or I/O Write signals, decodes the

Ao-A3 lines and either writes the contents of the data bus to the addressed internal register or reads the

contents of the selected register depending upon whether IOW or IOR signal is activated.

In master mode, the read/write logic generates the IOR and IOW signals to control the data

flow to or from the selected peripheral.

Control Unit:

The control logic controls the sequences of operations and generates the required control signals like

AEN, ADSTB, MEMR,MEMW, TC and MARK along with the address lines A4-A7, in master mode.

44 Dr.P.Durgadevi AP/RMKCET
Priority Resolver:

The priority resolver resolves the priority of the four DMA channels depending upon whether normal

priority or rotating priority is programmed.

Register Organisation of 8257:

The 8257 perfroms DMA operation over four independent DMA channels such as

1.DMA Address Register

Each DMA channel has one DMA address register. The function of this register is to store the
address of the starting memory location, which will be accessed by the DMA channel. The device that
wants to transfer data over a DMA channel, will access the block of the memory with the starting address
stored in the DMA Address Register.
2.Terminal Count Registers

Each of the four DMA channels of 8257 has one terminal count register (TC). This 16-bit register
isused for ascertaining that the data transfer through a DMA channel ceases or stops after the required
number of DMA cycles.

After each DMA cycle, the terminal count register content will be decremented by one and
finally it becomes zero after the required number of DMA cycles are over.

The bits 14 and 15 of this register indicate the type of the DMA operation (transfer).

3.Mode Set Register

The mode set register is used for programming the 8257 as per the requirements of the system. The
function of the mode set register is to enable the DMA channels individually and also to set the various
modes of operation.

45 Dr.P.Durgadevi AP/RMKCET
The bits Do-D3 enable one of the four DMA channels of 8257

If the TC STOP bit is set, the selected channel is disabled after the terminal count condition is

reached, and it further prevents any DMA cycle on the channel.

If the TC STOP bit is programmed to be zero, the channel is not disabled, even after the count

reaches zero and further request are allowed on the same channel.

The auto load bit, if set, enables channel 2 for the repeat block chaining operations, without immediate

software intervention between the two successive blocks.

The extended write bit, if set to ‘1’, extends the duration of MEMW and IOW signals by activating

them earlier, this is useful in interfacing the peripherals with different access times.

4.Status register

The lower order 4-bits of this register contain the terminal count status for the four individual channels.

If any of these bits is set, it indicates that the specific channel has reached the terminal count condition.

The update flag is not affected by the read operation. This flag can only be cleared by resetting 8257.

The update flag is set every time, the channel 2 registers are loaded with contents of the channel 3

registers. It is cleared by the completion of the first DMA cycle of the new block. This register can only

read.

DMA Transfer & Operations

The 8257 is able to accompolish three types of operations such

as 1.DMA operation

2.Write Operation

3.Read Operation

46 Dr.P.Durgadevi AP/RMKCET
The complete Operational sequence of 8257 is described in below state diagram.
➢
The 8257 request any one of the 8257 DRQ inputs to transfer single byte.

➢
In response to the request, the 8257 sends HRQ signal to CPU at its HLD input and waits
for acknowledgement at the HLDA input.

➢
If the HLDA signal is received by the DMA controller it indicates that the bus is available for
the transfer.

➢
The DMA controllers generate the read and write commands to transfer the byte from/to the
I/O Device.

➢
The DACK line of the used channel is pulled down by the dma controller to I/O device that
its request for DMA transfers.

➢
The HRQ line is lowered by the DMA controller to indicate the CPU that it may regain
the control of the bus.

➢
The DRQ must be high until acknowledged and must go low before S4 state of the
DMA operation state diagram to avoid another unwanted transfer.

➢
In each s4 state ,the DRQ lines are sampled and highest priority request is recognized during
next transfer. The HRQ line is maintained active till all the DRQ line go low.

➢
READY input used to interface 8257 with low speed devices.It is checked in s3 of the state
diagram . S3=0 ,8257 enter wait state. S3=1 ,8257 continues from s4 to complete the transfer.

47 Dr.P.Durgadevi AP/RMKCET
 DMA Operation State Diagram

Interfacing DMA controller(8257) with 8086

➢
If DMA controller is initialized by a CPU properly, it is ready to take control of the
system bus on a DMA request, either from a peripheral or itself (in case of memory-
tomemory transfer). The DMA controller sends a HOLD request to the CPU and waits for
the CPU to assert the HLDA signal. The CPU relinquishes the control of the bus before
asserting the HLDA signal.

➢
Once the HLDA signal goes high, the DMA controller activates the DACK signal to the
requesting peripheral and gains the control of the system bus. The DMA controller is the sole
master of the bus, till the DMA operation is over. The CPU remains in the HOLD status (all
of its signals are tristate except HOLD and HLDA), till the DMA controller is the master of
the bus.
➢
The DMA controller interfacing circuit implements a switching arrangement for the
address, data and control busses of the memory and peripheral subsystem from/to the CPU
to/from the DMA controller.

48 Dr.P.Durgadevi AP/RMKCET
 UNIT-IV
MICROCONTROLLER

Architecture of 8051 – Special Function Registers (SFRs) - I/O Pins Ports and Circuits –
Instruction set - Addressing modes - Assembly language programming.

INTRODUCTION

The microcontroller has built in ROM, RAM, Input Output ports, Serial Port, timers,

interrupts and clock circuit. A microcontroller is an entire computer manufactured on a single

chip.

Microcontroller (MC) may be called computer on chip since it has basic features of microprocessor

with internal ROM, RAM, Parallel and serial ports within single chip. Or we can say microprocessor

with memory and ports is called as microcontroller. This is widely used in washing machines, VCD

player, microwave oven, and robotics or in industries.

Microcontrollers Vs Microprocessors

• A microprocessor requires an external memory for program/data storage. Instruction execution

requires movement of data from the external memory to the microprocessor or vice versa.

Usually, microprocessors have good computing power and they have higher clock speed to

facilitate faster computation.

• A microcontroller has required on-chip memory with associated peripherals. A microcontroller

can be thought of a microprocessor with inbuilt peripherals.

• A microcontroller does not require much additional interfacing ICs for operation and it functions

as a standalone system. The operation of a microcontroller is multipurpose, just like a Swiss

knife.

• Microcontrollers are also called embedded controllers. A microcontroller clock speed is limited

only to a few tens of MHz Microcontrollers are numerous and many of them are application

specific.

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Structure of Microprocessor and Microcontroller

Advantages of microcontroller:
• Low cost and Small size of product

• Easy to troubleshoot and maintain

• More reliable

• Additional memory, I/o can also be added

• Software security feature

• All features available with 40 pins.

• Useful for small dedicated applications and not for larger system designs which may require

many more I/O ports.

INTEL 8051 MICROCONTROLLER

Introduction:

The Intel MCS-51 (commonly referred to as 8051) is a Harvard architecture, single chip

microcontroller (µC) series which was developed by Intel in 1980 for use in embedded systems.

The 8051 architecture provides many functions (CPU, RAM, ROM, I/O, interrupt logic, timer,etc.)in a

single package.

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Features:

Various features of 8051 microcontroller are given as follows.

8-bit ALU, Accumulator, 8-bit Registers and 8-bit data bus; hence it is an 8-bit microcontroller

16-bit program counter

• 8-bit Processor Status Word (PSW)

• 8-bit Stack Pointer

• Internal RAM of 128bytes

• On chip ROM is 4KB

• Special Function Registers (SFRs) of 128 bytes

• 32 I/O pins arranged as four 8-bit ports (P0 - P3)

• Two 16-bit timer/counters : T0 and T1

• Two external and three internal vectored interrupts

UART (serial port)

Simple Block Diagram of 8051:

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PIN DIAGRAM OF 8051

Pin out Description:

Pins 1-8: Port 1 Each of these pins can be configured as an input or an output.
Pin 9 : RST A logic one on this pin disables the microcontroller and clears the contents of most
registers.
Pins10-17: Port 3 Similar to port 1, each of these pins can serve as general input or output.
Besides, all of them have alternative functions:
Pin 10: RXD Serial asynchronous communication input or Serial synchronous communication output.
Pin 11: TXD Serial asynchronous communication output or Serial synchronous communication clock
output.
Pin 12: INT0 Interrupt 0 input.
Pin 13: INT1 Interrupt 1 input.
Pin 14: T0 Counter 0 clock input.
Pin 15: T1 Counter 1 clock input.
Pin 16: WR Write to external (additional) RAM.
Pin 17: RD Read from external RAM.
Pin 18, 19: XTAL2, XTAL1 Internal oscillator input and output. A quartz crystal which specifies
operating frequency is usually connected to these pins. Later versions of microcontrollers operate at a
frequency of 0 Hz up to over 50 Hz.
Pin 20: GND Ground.
Pin 21-28: Port 2 If there is no intention to use external memory then these port pins are
configured as general inputs/outputs. In case external memory is used, the higher address byte, i.e.
addresses A8-A15 will appear on this port.
Pin 29: PSEN If external ROM is used for storing program then a logic zero (0) appears on it every
time the microcontroller reads a byte from memory.
Pin 30: ALE Prior to reading from external memory, the microcontroller puts the lower address byte
(A0 - A7) on P0 and activates the ALE output.
Pin 31: EA By applying logic zero to this pin, P2 and P3 are used for data and address transmission
with no regard to whether there is internal memory or not
Pin 32-39: Port 0 Similar to P2, if external memory is not used, these pins can be used
as general inputs/outputs. Otherwise, P0 is configured as address output (A0-A7) when the ALE pin is
driven high (1) or as data output (Data Bus) when the ALE pin is driven low (0).
Pin 40: VCC +5V power supply.
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INTERNAL ARCHITECTURE OF 8051 MICROCONTROLLER

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➢
Accumulator (Acc):
•Operand register
•Implicit or specified in the instruction
•Has an address in on chip SFR bank
➢
B Register: Used to store one of the operands for multiplication and division, otherwise, scratch
pad considered as a SFR.
➢
Program Status Word (PSW): Set of flags contains status information.
➢
Stack Pointer (SP): 8 bit wide register. Incremented before data is stored on to the stack using PUSH
or CALL instructions. Stack defined anywhere on the 128 byte RAM
➢
Data Pointer (DPTR): 16 bit register contains DPH and DPL Pointer to external RAM address.
DPH and DPL allotted separate addresses in SFR bank
➢
Port 0 To 3 Latches & Drivers: Each I/O port allotted a latch and a driver Latches allotted address in
SFR. User can communicate via these ports P0, P1, P2, and P3.
➢
Serial Data Buffer: Internally had TWO independent registers, TRANSMIT buffer (parallel in serial
out – PISO) and RECEIVE buffer (serial in parallel out –SIPO) identified by SBUF and allotted an
address in SFR.
➢
Timer Registers: for Timer0 (16 bit register – TL0 & TH0) and for Timer1 (16 bit register – TL1 &
TH1) four addresses allotted in SFR
➢
Control Registers: Control registers are IP, IE, TMOD, TCON, SCON, and PCON. These registers
contain control and status information for interrupts, timers/counters and serial port. Allotted separate
address in SFR.
➢
Timing and Control Unit: This unit derives necessary timing and control signals for internal circuit
and external system bus
➢
Oscillator: generates basic timing clock signal using crystal oscillator.
➢
Instruction Register: decodes the opcode and gives information to timing and control unit.

➢
EPROM & program address Register: provide on chip EPROM and mechanism to address it. All
versions don’t have EPROM.
➢
Ram & Ram Address Register: provide internal 128 bytes RAM and a mechanism to address internally
➢
ALU: Performs 8 bit arithmetic and logical operations over the operands held by TEMP1 and
TEMP 2.User cannot access temporary registers.
➢
SFR Register Bank: set of special function registers address range: 80 H to FF H. Interrupt, serial port
and timer units control and perform specific functions under the control of timing and control unit

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 REGISTER SET OF 8051
Accumulator
ACC is the Accumulator register. The mnemonics for accumulator-specific instructions, however,
refer to the accumulator simply as A.
B Register
The B register is used during multiply and divide operations. For other instructions it can be treated another
scratch pad register.
Program Status Word
The PSW register contains program status information as detailed in Table
below Table .PSW: Program Status Word Register

Stack Pointer
The Stack Pointer register is 8 bits wide. It is incremented before data is stored during PUSH and CAL
executions. While the stack may reside anywhere in on-chip RAM, the Stack Pointer is initialized to 07
after a reset. This causes the stack to begin at location 08H.
Data Pointer
The D ata P ointer (D PTR) cons ists of a high byte (DPH) and a low byte (D PL). Its intended function is
t hold a 16-bit address. It may be manipulated as a 16-bit register or as two independent 8-bit registers.
Ports 0 to 3
P0, P1, P2 and P3 are the SFR latches of Ports 0, 1, 2 and 3, respectively.
Serial Data Buffer
The Serial Data Buffer is actually two separate registers, a transmit buffer and a receive buffer register.
When data is moved to SBUF, it goes to the transmit buffer where it is held for serial transmission.
(Moving a byte to SBUF is what initiates the transmission.) When data is moved from SBUF, it comes
from the receive buffer.
Timer Registers
Register pairs (TH0, TL0), (TH1, TL1), and (TH2, TL2) are the 16-bit counting registers for
Timer/Counte
0, 1, and 2, respectively.
Capture Registers
The register pair (RCAP2H, RCAP2L) are the capture register for the Timer 2 ‘capture mode’. In this
mode, in response to a transition at the 80C52’s T2EX pin, TH2 and TL2 are copied into RCAP2H and
RCAP2L. Timer 2 also has a 16-bit auto-reload mode, and RCAP2H and RCAP2L hold the reload value
for this mode.
Control Registers: Special Function Registers IP, IE, TMOD, TCON, T2CON, SCON, and PCON
contain control and status bits for the interrupt system, the timer/counters, and the serial port.
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 8051 MICROCONTROLLER SPECIAL FUNCTION REGISTERS (SFRS)
The 8051 Microcontroller Special Function Registers are used to program and control different hardware
peripherals like Timers, Serial Port, I/O Ports etc. In fact, by manipulating the 8051 Microcontroller Special
Function Registers (SFRs), you can assess or change the operating mode of the 8051 Microcontroller.

List of 8051 Microcontroller Special Function Registers

The 21 Special Function Registers of 8051 Microcontroller are categorized in to seven groups. They are:
• Math or CPU Registers: A and B
• Status Register: PSW (Program Status Word)
• Pointer Registers: DPTR (Data Pointer – DPL, DPH) and SP (Stack Pointer)
• I/O Port Latches: P0 (Port 0), P1 (Port 1), P2 (Port 2) and P3 (Port 3)
• Peripheral Control Registers: PCON, SCON, TCON, TMOD, IE and IP
• Peripheral Data Registers: TL0, TH0, TL1, TH1 and SBUF

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CPU or Math Registers
A or Accumulator (ACC)
The Accumulator or Register A is the most important and most used 8051 Microcontroller SFRs. The
Register A is located at the address E0H in the SFR memory space. The Accumulator is used to hold
the data for almost all the ALU Operations.
Some of the operations where the Accumulator is used are:
• Arithmetic Operations like Addition, Subtraction, Multiplication etc.
• Logical Operations like AND, OR, NOT etc.
• Data Transfer Operations (between 8051 and External Memory)
The name “Accumulator” came from the fact this register is used to accumulate (or store) the result of all
Arithmetic and most of the Logical Operations.
B (Register B)
The B Register is used along with the ACC in Multiplication and Division operations. These two
operations are performed on data that are stored only in Registers A and B. During Multiplication
Operation, one of the operand (multiplier or multiplicand) is stores in B Register and also the higher
byte of the result.
In case of Division Operation, the B Register holds the divisor and also the remainder of the result. It
can also be used as a General Purpose Register for normal operations and is often used as an Auxiliary
Register by Programmers to store temporary results.
Register B is located at the address F0H of the SFR Address Space.

Program Status Word (PSW)

The PSW or Program Status Word Register is also called as Flag Register and is one of the important
SFRs. The PSW Register consists of Flag Bits, which help the programmer in checking the condition
of the result and also make decisions.

The following table describes the function of each flag.

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Pointer Registers
Data Pointer (DPTR – DPL and DPH)
The Data Pointer is a 16-bit Register and is physically the combination of DPL (Data Pointer Low) and
DPH (Data Pointer High) SFRs. The Data Pointer can be used as a single 16-bit register (as DPTR) or
two 8-bit registers (as DPL and DPH).
DPTR doesn’t have a physical Memory Address but the DPL (Lower Byte of DPTR) and DPH (Higher
Byte of DPTR) have separate addresses in the SFR Memory Space. DPL = 82H and DPH = 83H.
The DPTR Register is used by the programmer addressing external memory (Program – ROM or Data
– RAM).
DPH DPL
DPTR
DPL Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address=82H

DPH Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address=83H
Stack Pointer (SP)
SP or Stack Pointer points out to the top of the Stack and it indicates the next data to be accessed.
Stack Pointer can be accesses using PUSH, POP, CALL and RET Instructions. The Stack Pointer is an 8-
bit register and upon reset, the Stack Pointer is initialized with 07H.
SP Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address=81H
I/O Port Registers (P0, P1, P2 and P3)
The 8051 Microcontroller four Ports which can be used as Input and/or Output. These four ports
are P0, P1, P2 and P3. Each Port has a corresponding register with same names (the Port Registers are
also P0, P1, P2 and P3. The addresses of the Port Registers are as follows: P0 – 80H, P1 – 90H, P2 – A0H
and P2 – B0H.

Peripheral Control Registers

PCON (Power Control)
The PCON or Power Control register, as the name suggests is used to control the 8051 Microcontroller’s
Power Modes and is located at 87H of the SFR Memory Space. Using two bits in the PCON Register,
the microcontroller can be set to Idle Mode and Power Down Mode.

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SCON (Serial Control)
The Serial Control or SCON SFR is used to control the 8051 Microcontroller’s Serial Port. It is located as
an address of 98H. Using SCON, you can control the Operation Modes of the Serial Port, Baud Rate of
the Serial Port and Send or Receive Data using Serial Port.
SCON SM0 SM1 SM2 REN TB8 RB8 T1 R1 Address=98H
TCON (Timer Control)
Timer Control or TCON Register is used to start or stop the Timers of 8051 Microcontroller. It also
contains bits to indicate if the Timers has overflowed. The TCON SFR also consists of Interrupt
related bits.
TCON TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 Address=88H

TMOD (Timer Mode)

The TMOD or Timer Mode register or SFR is used to set the Operating Modes of the Timers T0 and T1.
The lower four bits are used to configure Timer0 and the higher four bits are used to configure Timer1.
IE (Interrupt Enable)
The IE or Interrupt Enable Register is used to enable or disable individual interrupts. If a bit is SET,
the corresponding interrupt is enabled and if the bit is cleared, the interrupt is disabled. The Bit7 of the
IE register i.e. EA bit is used to enable or disable all the interrupts.
IE EA -- ET2 ES ET1 EX1 ET0 EX0 Address=A8H
IP (Interrupt Priority)
The IP or Interrupt Priority Register is used to set the priority of the interrupt as High or Low. If a bit
is CLEARED, the corresponding interrupt is assigned low priority and if the bit is SET, the interrupt is
assigned high priority.
IP -- -- PT2 PS PT1 PX1 PT0 PX0 Address=B8H
Peripheral Data Registers
SBUF (Serial Data Buffer)
The Serial Buffer or SBUF register is used to hold the serial data while transmission or reception.
TL0/TH0 (Timer 0 Low/High)
The Timer 0 consists of two SFRs: TL0 and TH0. The TL0 is the lower byte and the TH0 is the
higher byte and together they form a 16-bit Timer0 Register.

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TL1/TH1 (Timer 1 Low/High)

8051 I/O pins and circuits:

8051 has four ports such as Port 0,Port 1,Port 2,Port 3.Each port of 8051 has bidirectional capability.
Port 0 is called 'true bidirectional port' as it floats (tristated) when configured as input. Port-1, 2, 3 are
called 'quasi bidirectional port'.
Port 0 pins and circuits:
Port 0 is multi functioned port of microcontroller 8051.Its SFR address is 80H.It is bit addressable port.
• Function and use : It can be used as simple input / output mode or for generating data and lower order
address bus for external memory (AD0 – AD7). In order to use the pins of the port 0 as input and output
each pin must be connected to 10KΩ pull up resistor.
Port 0 as an input:
When the port is used as an input port, '1' is written to the latch. In this situation both the output
MOSFETs are 'off'. Hence the output pin have floats hence whatever data written on pin is directly read
by read pin. When configured input port the microcontroller provides two facilities:
1. Read logic level on physical pin by asserting read pin signal.
2. Read contents of internal latch by asserting the read latch signal. The latch is read when the
instruction is read-modify-write type instruction. A read-modify-write signal is one, wherein the
instruction reads the data from the port modifies it and writes to the port.

By using the following program , port 0 is configured as input port.

MOV A,#0FFh
MOV P0,A
LOOP: MOV A,P0
MOV P1,A
SJMP LOOP

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 Port 0 as an output:
When port 0 is configured as an output port, the latch pins that are programmed to 0 will cause the lower
FET to turn ON and pin is grounded. • If a ‘1’ is written on to the latch pin the FET will turn off and the
pin is pulled HIGH by external pull up resistors

Port 1 pins and circuits :

It is not necessary to connect any pull-up resistors because it is having pull-up resistors already. Port-1
does not have any alternate function i.e. it is dedicated solely for I/O interfacing. When used as output
port, the pin is pulled up or down through internal pull-up. To use port-1 as input port, '1' has to be
written to the latch. In this input mode when '1' is written to the pin by the external device then it read
fine. But when '0' is written to the pin by the external device then the external source must sink current
due to internal pull-up.

Port 2 pins and circuits:

Port 2 of microcontroller 8051 is 8 bit multifunctional port. Its SFR address is A0H. It is bit
addressable port.

Function and use : It can be used as simple input / output or for generating the upper order address
bus for the external memory (A8 –A15).

Port ‘2’as simple input port:

When port 2 is used as an input port,’1’ must be written to the corresponding latch bit. This cause the
FET turn off. The pin and input to pin buffer are pulled to logic high by the internal pull up load. Port 2
is called as “quasi-bidirectional port” as its output is pull up resistors.

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Port 2 as simple output port :

When port 2 is used as output port, the latch pins that are programmed to 0, will cause the
lower FET turn off and input to the circuit logic 0. If “1” is written onto the latch pin then it
will drive the input of external circuit high through the pull up. The lower FET turns off.

Port 3 pins and circuits:

It is 8 bit multifunctional port. • Its SFR address is B0H. It is bit addressable port. ]

Use : Port 3 is a multifunctional port it can be used as simple input / output port.
Port 3 as simple input port :

When port 3 is used as input port, “1” must be written to the corresponding port 3 latch bit. This
causes the FET turn off. The pin and input to the pin buffer are to pulled to logic HIGH by
internal pull up load.
Port 3 as simple output port :

When port 3 is used as output port, the latched pins that are programmed to 0, will cause the
lower FET to turn on, the internal pull up to turn off and input to the circuit is logic 0. If ‘1’ is
written onto the latch pin that it will drive the input external circuit high through the pull up. The
lower FET turns off.

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Following are the alternate functions of port 3:

INTERNAL AND EXTERNAL MEMORY ORGANIZATION OF 8051

The 8051 microcontroller's memory is divided into Program Memory and Data Memory.
Program Memory (ROM) is used for permanent saving program being executed, while Data
Memory (RAM) is used for temporarily storing and keeping intermediate results and variables.
Program Memory (ROM)
Program Memory (ROM) is used for permanent saving program (CODE) being executed. The
memory is read only. Depending on the settings made in compiler, program memory may also
used to store a constant variables. The 8051 executes programs stored in program memory only.
code memory type specify is used to refer to program memory.
8051 memory organization allows external program memory to be added.
How does the microcontroller handle external memory depends on the pin EA logical state.

Internal Data Memory

Up to 256 bytes of internal data memory are available depending on the 8051 derivative.
Locations available to the user occupy addressing space from 0 to 7Fh, i.e. first 128 registers
and this part of RAM is divided in several blocks. The first 128 bytes of internal data memory
are both directly and indirectly addressable. The upper 128 bytes of data memory (from 0x80 to
0xFF) can be addressed only indirectly.

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External Data Memory

Access to external memory is slower than access to internal data memory. There may be up to
64K Bytes of external data memory. Several 8051 devices provide on-chip XRAM space that is
accessed with the same instructions as the traditional external data space. This XRAM space is
typically enabled via proper setting of SFR register and overlaps the external memory space.
Setting of that register must be manually done in code, before any access to external memory
or XRAM space is made.

INSTRUCTION SET OF 8051 MICROCONTROLLER

8051 micro controller have reach set of instruction to perform different operation in 8051
micro-controller.
There are five group of instruction which are listed below.
Arithmetic Instructions
• Logic Instructions
• Data Transfer Instructions
• Branch Instructions
• Bit-oriented Instructions

Arithmetic instruction:
Arithmetic instructions perform several basic operations such as addition, subtraction, division,
multiplication etc. After execution, the result is stored in the first operand.

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1.ADD A,Rn;Adds the register Rn to the accumulator
Description: Instruction adds the register Rn (R0-R7) to the accumulator. After addition,
the result is stored in the accumulator
Before execution: A=2Eh R4=12h
After execution: A=40h R4=12h
2.ADD A,@Ri - Adds the indirect RAM to the accumulator.
Ri: Register R0 or R1
Description: Instruction adds the indirect RAM to the accumulator. Address of indirect RAM
is stored in the Ri register (R0 or R1). After addition, the result is stored in the accumulator.
Register address:R0=4Fh
Before execution: A= 16h SUM= 33h
After execution : A= 49h
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3.ADD A,#DATA
Data: constant within 0-255 (0-FFh)
Description: Instruction adds data (0-255) to the accumulator. After addition, the result is stored
in the accumulator.
ADD A,#33h
Before execution: A= 16h
After execution: A= 49h )
4.SUBB A,direct - Subtracts the direct byte from the accumulator with a
borrow Direct: arbitrary register with address 0-255 (0-FFh)
Description: Instruction subtracts the direct byte from the accumulator with a borrow. If the
higher bit is subtracted from the lower bit then the carry flag is set. As it is direct addressing, the
direct byte can be any SFRs or general-purpose register with address 0-7Fh. (0-127 dec.). The
result is stored in the accumulator.
SUBB A,Rx
Before execution: A=C9h, DIF=53h, C=0
After execution: A=76h, C=0
5.INC A - Increments the accumulator by 1
A: accumulator
Description: This instruction increments the value in the accumulator by 1. If the
accumulator includes the number 255, the result of the operation will be 0.
Before execution: A=E4h
After execution: A=E5h
6.DEC A - Decrements the accumulator by 1
A: accumulator
Description: Instruction decrements the value in the accumulator by 1. If there is a 0 in
the accumulator, the result of the operation is FFh. (255 dec.)
Syntax: DEC A;
Byte: 1 (instruction code);
STATUS register flags: No flags are affected;
Before execution: A=E4h
After execution: A=E3h
7.DIV AB - Divides the accumulator by the register B
Description: Instruction divides the value in the accumulator by the value in the B register. After
division the integer part of result is stored in the accumulator while the register contains the
remainder. In case of dividing by 1, the flag OV is set and the result of division is unpredictable.
The 8-bit quotient is stored in the accumulator and the 8-bit remainder is stored in the B register.
Before execution: A=FBh (251dec.) B=12h (18 dec.)
After execution: A=0Dh (13dec.) B=11h (17dec.)
13·18 + 17 =251
8.DA A - Decimal adjust accumulator
Description: Instruction adjusts the contents of the accumulator to correspond to a BCD
number after two BCD numbers have been added by the ADD and ADDC instructions. The
result in form of two 4-digit BCD numbers is stored in the accumulator.
Before execution: A=56h (01010110) 56 BCD
B=67h (01100111) 67BCD
After execution: A=BDh (10111101)
After BCD conversion: A=23h (00100011), C=1 (Overflow)
(C+23=123) = 56+67
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9.MUL AB - Multiplies A and B
Description: Instruction multiplies the value in the accumulator with the value in the B register.
The low-order byte of the 16-bit result is stored in the accumulator, while the high byte
remains in the B register. If the result is larger than 255, the overflow flag is set. The carry flag
is not affected.
Before execution: A=80 (50h) B=160 (A0h)
After execution: A=0 B=32h
A·B=80·160=12800 (3200h)
Logical Instruction Of 8051 Micro-Controller
Logic instructions perform logic operations upon corresponding bits of two registers. After
execution, the result is stored in the first operand.

ANL A,Rn - AND register to the accumulator

A: accumulator
Rn: any R register (R0-R7)
Instruction performs logic AND operation between the accumulator and Rn register. The result
is stored in the accumulator.

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 ANL A,Rn
Before execution: A= C3h (11000011 Bin.)
R5= 55h (01010101 Bin.)
After execution: A= 41h (01000001 Bin.)
ORL A,Rn - OR register to the accumulator
Rn: any R register (R0-R7)
A: accumulator
Instruction performs logic OR operation between the accumulator and Rn register. The result is
stored in the accumulator.
ORL A,Rn
Before execution: A= C3h (11000011 Bin.)
R5= 55h (01010101 Bin.)
After execution: A= D7h (11010111 Bin.)
XRL A,Rn - Exclusive OR register to accumulator
Rn: any R register (R0-R7)
A: accumulator
Instruction performs exclusive OR operation between the accumulator and the Rn register.
The result is stored in the accumulator.
XRL A,Rn
Before execution: A= C3h (11000011 Bin.)
R3= 55h (01010101 Bin.)
After execution: A= 96h (10010110 Bin.)
CLR A - Clears the accumulator
A: accumulator
Instruction clears the accumulator.
CLR A
After execution: A=0
CPL A - Complements the accumulator
A: accumulator Instruction complements all the bits in the accumulator (1==>0, 0==>1).
CPL A
Before execution: A= (00110110)
After execution: A= (11001001)
RL A - Rotates the accumulator one bit left
A: accumulator
Eight bits in the accumulator are rotated one bit left, so that the bit 7 is rotated into the bit 0
position.
RL A
Before execution: A= C2h (11000010 Bin.)
After execution: A=85h (10000101 Bin.)
RR A - Rotates the accumulator one bit right
A: accumulator All eight bits in the accumulator are rotated one bit right so that the bit 0
is rotated into the bit 7 position.
RR A
Before execution: A= C2h (11000010 Bin.)
After execution: A= 61h (01100001 Bin.)

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 RLC A - Rotates the accumulator one bit left through the carry
flag A: accumulator
All eight bits in the accumulator and carry flag are rotated one bit left. After this operation, the bit
7 is rotated into the carry flag position and the carry flag is rotated into the bit 0 position.
RLC A
Before execution: A= C2h (11000010 Bin.) C=0
After execution: A= 85h (10000100 Bin.) C=1
RRC A - Rotates the accumulator one bit right through the carry
flag A: accumulator
All eight bits in the accumulator and carry flag are rotated one bit right. After this operation, the
carry flag is rotated into the bit 7 position and the bit 0 is rotated into the carry flag position.
RRC A
Before execution: A= C2h (11000010 Bin.) C=0
After execution: A= 61h (01100001 Bin.) C=0
SWAP A - Swaps nibbles within the accumulator
A: accumulator
A nibble refers to a group of 4 bits within one register (bit0-bit3 and bit4-bit7). This instruction
interchanges high and low nibbles of the accumulator.
SWAP A
Before execution: A=E1h (11100001)bin.
After execution: A=1Eh (00011110)bin.
Data Transfer Instruction of 8051
This instructions are used to copy the content of source operand to Destination operand

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MOV A,Rn - Moves the Rn register to the accumulator
The instruction moves the Rn register to the accumulator. The Rn register is not affected.
MOV A,Rn
Beforeexecution:R3=58h
After execution: R3=58h A=58h
MOV A,@Ri - Moves the indirect RAM to the accumulator
Instruction moves the indirectly addressed register of RAM to the accumulator. The register
address is stored in the Ri register (R0 or R1). The result is stored in the accumulator. The
register is not affected.
MOV A,@Ri
Register Address SUM=F2h R0=F2h
Before execution: SUM=58h
After execution: A=58h SUM=58h
MOV A,#data - Moves the immediate data to the accumulator
Instruction moves the immediate data to the accumulator.
MOV A,#28
After execution: A=28h
MOV direct,@Ri - Moves the indirect RAM to the direct byte

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Instruction moves the indirectly adressed register of RAM to the direct byte. The register is not
affected.
MOV Rx,@Ri
Register Address SUM=F3
Before execution: SUM=58h R1=F3
After execution: SUM=58h TEMP=58h
MOVC A,@A+DPTR - Moves the code byte relative to the DPTR to the accumulator
Instruction first adds the 16-bit DPTR register to the accumulator. The result of addition is then
used as a memory address from which the 8-bit data is moved to the accumulator.
MOVC A,@A+DPTR
Bit-oriented Instructions
Similar to logic instructions, bit-oriented instructions perform logic operations. The difference is
that these are performed upon single bits.

ANL C,bit - AND direct bit to the carry flag

C: Carry flag
Bit: any bit of RAM,
Instruction performs logic AND operation between the direct bit and the carry flag.
ANL C,bit
Before execution: ACC= 43h (01000011 Bin.) C=1
After execution: ACC= 43h (01000011 Bin.) C=0

CLR C - clears the carry flag

C: Carry flag, Instruction clears the carry flag.
CLR C

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After execution: C=0

CLR bit - clears the direct bit

Bit: any bit of RAM, Instruction clears the specified bit.
CLR P0.3
Before execution: P0.3=1 (input pin)
After execution: P0.3=0 (output pin)

CPL bit - Complements the direct bit

Bit: any bit of RAM, Instruction coplements the specified bit of RAM (0==>1, 1==>0).
CPL P0.3
Before execution: P0.3=1 (input pin)
After execution: P0.3=0 (output pin)

CPL C - Complements the carry flag

C: Carry flag, Instruction complements the carry flag (0==>1, 1==>0).
CPL C
Before execution: C=1
After execution: C=0

MOV bit,C - Moves the carry flag to the direct

bit C: Carry flag, Bit: any bit of RAM
Instruction moves the carry flag to the direct bit. After executing the instruction, the carry flag
is not affected.
MOV P1.2,C
After execution: If C=0 P1.2=0
If C=1 P1.2=1

MOV C,bit - Moves the direct bit to the carry

flag C: Carry flag, Bit: any bit of RAM
Instruction moves the direct bit to the carry flag. After executing the instruction, the bit is not
affected.
MOV C, P1.4
After execution: If P1.4=0 C=0
If P1.4=1 C=1

SETB C - Sets the carry flag

C: Carry flag, Instruction sets the carry flag.
SETB C
After execution: C=1
SETB bit - Sets the direct bit
Bit: any bit of RAM
Instruction sets the specified bit. The register containing that bit must belong to the group of
the so called bit addressable registers.
SETB P0.1

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Before execution: P0.1 = 34h (00110100)
pin 1 is configured as an output
After execution: P0.1 = 35h (00110101)
pin 1 is configured as an inputs
Branch Instruction Of 8051 controller
There are two kinds of branch instructions:
Unconditional jump instructions: upon their execution a jump to a new location from where
the program continues execution is executed.
Conditional jump instructions: a jump to a new program location is executed only if a
specified condition is met. Otherwise, the program normally proceeds with the next instruction.

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ADDRESSING MODE OF 8051 MICRO-CONTROLLER
what is addressing mode?
CPU access data from memory,register,immediate value.These various way to access data are
called addressing mode.
The 8051 micro-controller are five addressing mode.
immediate
1. register
2. direct
3. register indirect
4. index
Immediate:
In this addressing mode source operand is constant.
• it's come after op code in instruction.
• it must be preceded by "#" .
• its used to load data into register.
• examples:
1. MOV A,#32H ;Load 32h into A register.
2. MOV DPTR,#1234H ;Load 1234h into DPTR.
Register:
In this mode registers are used to hold data to be manipulated.
• Size of destination register and source register are always equal.
• the data between to registers Rn(n=0 to 7) and Rn(n=0 to7) do not transfer.
• examples:
1. MOV A,R0 ;copy content of R0 into A.
2. MOV R0,R1 ;not possible because data to be processed in some memory
location of RAM.
Direct:
To access data directly form RAM location.
• using this mode we can access 128Byte RAM directly.
• in this data is in a RAM memory location whose address is known.
• the difference between immediate and direct addressing mode is "#"sign.in this mode
this sign is absent.
• examples:
1. MOV R0,30H ;save content of RAM location 30h
into R0.
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 2. MOV 7,2 ;invalid (it means copy content of
R2 into R7).
Register indirect:
In this register used as pointer to the data.
• only register R0 and R1 used in this mode.
• R0 and R1 hold address of RAM location.
• both register must be preceded by "@"sign.
• looping is easily used in this mode.
• drawback of this mode is we can used two register R0 & R1 only.
• examples:
1. MOV A,@R0 ;move content of RAM location whose address stored in
R0.
2. MOV @R1,A ;move content of A into RAM location whose address stored in
R1.
Index :
In this mode data access from look up table entire located in the program memory
ROM space of 8051.
• register A and DPTR used in this addressing mode.
• here instruction MOVC used instead of MOV because C indicate
Code memory(ROM).
examples:
1. MOVC A,@A+DPTR;

Assembly Language Programming

An assembly language program has six fields: Memory Address, Machine Code, Opcode,
Operands, and Comments. Memory Address: These are 16-bit addresses of the user memory in
the system, where the machine code of the program is stored. The beginning address shown as
in the format “XX00”; the symbol XX represents the page number and 00 represents the line
number.

Machine Code: Also called as instruction code. These are the hexadecimal numbers
represents instructions that are stored in the respective memory addresses.
Label: A label is a symbol or group of symbols used to represent an address of specific
statement. Labels are usually followed by a colon. Labels are not required in a statement;
they are just inserted where they are needed.
Opcode (Operation Code): An instruction is divided into two parts: Opcode and
Operand. Opcode are the abbreviated symbols to indicate the type of operation or function
that will perform by the machine code.
Operand: The operand field of the statement contains the 8-bit or 16-bit data, the memory address,
the port address, or the name of the registers on which the instruction is to be performed.
[Label:] mnemonic [operand] [;comment]

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ASSEMBLING AND RUNNING AN 8051 PROGRAM

The steps to create an executable Assembly language program are outlined as

follows. Editor
Use an editor to type in a program Many excellent editors or word processors are available that
can be used to create and/or edit the program. A widely used editor is the MS-DOS EDIT
program (or Notepad in Windows), which comes with all Microsoft operating systems.
Asm Source files
The “asm” source file containing the program code created in step 1 is fed to an 8051 assembler.
The assembler converts the instructions into machine code. The assembler will produce an object
file and a list file. The extension for the object file is “obj” while the extension for the list file is
“1st”.
Linker
Assemblers require a third step called linking. The link program takes one or more object
files and produces an absolute object file with the extension “abs”
Abs file
Next, the “abs” file is fed into a program called “OH” (object to hex converter), which creates
a file with extension “hex” that is ready to burn into ROM.

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Assembler directives
ORG (origin):-
The origin (ORG) directive is used to indicate the beginning of the addresses the number that
comes after ORG can be either in hex or in decimal if the number is not followed by H it is
decimal and the assembler will convert it to hex some assembler use “.ORG” instead of “ORG”
for the origin directive.
Ex:- ORG 0000H
EQU (equate):-
This is used to define a constant without accupying a memory location. The EQU directive does
not set aside storage for a data item but associates a constant value with a data label so that when
the label appears in the program it constant value will be substituted for the label use EQU for
the counter constant and then the constant is used to load the R3 register. Ex:-

COUNT EQU 25
MOV R3, # COUNT
END:-
Important pseudo code is the END directive this indicates to the assembler at the end of the
source (asm) file the END directive is the last line of an 8051 program meaning that in the
source code anything after the END directive is ignored by the assembler.
DB (Define byte):-
The DB directive is the most widely used data directive in the assembler it is used to define the
8-bit data when DB is used to define data, the numbers can be in decimal binary, hex or ASCII
format for decimal “D” after the decimal number, for binary ‘B’ and hexadecimal ‘H’
required. DB directive is the only directive that can be used to define ASCII strings larger than
the character therefore it should be used for all ASCII data definitions. Ex: -

ORG 5000 H
DATA 1: DB 28 (Decimal)
DATA 2: DB 39H (HEX)
DATA 3: 0101001 B (Binary)
ALP PROGRAM IN 8051: SUB A, #06H
8-bit Addition MOV DPTR, #4500H
MOVX @DPTR, A
START: MOV A, #05H
STOP: SJMP
ADD A, #06H
MOV DPTR, #4500H
MOVX @DPTR, A 8-bit Multiplication
STOP: SJMP MOV A,#06H
8-bit Subtraction MOV B,# 02H
START: MOV A, #05H MUL AB

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EC 6504 MICROPROCESSOR AND MICROCONTROLLER II/IV Sem

MOV DPTR,#4500 H MOV X,@DPTR,A

MOVX @ DPTR,A SJMP
INC DPTR Finding square and cube of a given
MOV A ,B number
MOV X,@DPTR, A MOV DPTR, #4500
SJMP MOVX A,@DPTR
MOV B, A
8-bit Division MOV R0, A
MOV A,#06H MUL AB
MOV B,# 02 H INC DPTR
DIV AB MOVX @DPTR, A
MOV DPTR,#4500 H MOV R1, B
MOV X@ DPTR,A MOV B, R0
INC DPTR MUL AB
MOV A ,B INC DPTR
MOVX @DPTR, A ADD A , R7
MOV R2, B MOV R3, A
MOV B, R0 MOV A, R6

MOV A, R1 ADDC A, R4
MOV R2,A
MUL AB
END
ADD A, R2
INC DPTR
Sum of first 10 natural numbers
MOV A, B
ADC A, #00 MOV R1,#0AH
MOVX @DPTR, A MOV A,#00H
L1: SJMP L1 AGAIN: ADD A,R1
16 BIT ADDITION DJNZ R1, AGAIN
ORG 0000H DEC R1
MOV R7, #34H
MOV R2,A
MOV R6, #24H
END
MOV R5,#45H
MOV R4, #33H
MOV A, R5

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8051 Program to exchange data block of 10 Bytes:

MOV R0,#20H
MOV R1,#30H
MOV R2,#0AH
UP: MOV A,@R0
XCH A,@R1
MOV @R0,A
INC R0
INC R1
DJNZ R2,UP
RET

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