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CO - Notes

Computer Organization & Architecture (Mahatma Gandhi University)

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Computer Organization and Architecture

Syllabus
MODULE 1: Basic computer organization and design
Operational concepts, Instruction codes, Computer Registers, Computer Instructions, Memory
locations and addresses, Instruction cycle, Timing and control, Bus organization.
MODULE 2: Central Processing Unit:
General Register Organization, Stack Organization, Addressing modes, Instruction classification, Program control.
MODULE 3:Memory Organization
Memory Hierarchy, Main Memory, Organization of RAM, SRAM, DRAM, Read Only Memory- ROM-
PROM, EROM, EEPROM, Auxiliary memory, Cache memory, Virtual Memory, Memory mapping
Techniques.
MODULE 4:Parallel Computer Structures:
Introduction to parallel processing, Pipeline computers, Multi processing systems, Architectural
classification scheme-SISD, SIMD, MISD, MIMD.
MODULE 5: Pipelining and Vector processing
Introduction to pipelining, Instruction and Arithmetic pipelines (design) Vector processing, Array
Processors.

Previous Questions Part A

1. What is an instruction code?

2. Write the use of PC Register.
3. Write about fetch-decode-execute cycle.

4. What is the purpose of program control instructions?

5. What is stack pointer?
6. How is memory locations addressed?
7. Write about branch instructions
8. Write a note on primary memory.
9. What is SRAM and DRAM?
10. What is space-time diagram for a pipeline?
11. What is MISD?
12. What is page fault?
13. What is the significance of addressing mode? Explain any one addressing mode.
14. What is hit ratio?
15. What is status register? Explain status bits.
16. What is a super computer?
17. Define interrupt. List the types of interrupts.
18. What is control word?
19. What is SISD?
20. What is an accumulator?
21. Explain multiprocessing system.
22. What is one-address instruction? List any two one-address instructions.

Part B
1. Explain stored program organisation.
2. Differentiate RISC and CISC
3. Explain Bus organisation.
4. Explain about data transfer instructions with suitable examples.
5. Explain how magnetic tapes work.
6. Discuss the replacement algorithms foe cache memory.
7. Explain address mapping using pages.
8. Explain multiprocessing systems.
9. Explain different types of array processors. What are the advantages provided by array processors?
10. Explain different instruction code formats.
11. Explain hoe reverse polish notation is suitable for stack manipulation.

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12. Write the help of a diagram explain set associative mapping.
13. Explain microprogrammed control unit.
14. Explain vector processing.
15. Explain the memory hierarchy in a computer system.
16. Write a note on virtual memory.
17. Write different instruction classification.
Part C
1) Discuss general register organisation with the help of a neat diagram.
2) Explain memory hierarchy.
3) a) Explain CPU internal architecture.
b) Write a short note on parallel systems.
4) Explain instruction pipeline with example and neat diagram.
5) Describe the instruction cycle in detail.
6) Explain the stack organisation in CPU.
7) What is pipelining? Explain arithmetic, instruction and RISC pipeline.
8) Explain various addressing modes with the help of examples.
9) Explain the Flynn’s Classification.

Module 1
Instruction codes: Basic computer organization and design
An instruction code is a group of bits that instruct the computer to perform a specific operation. It is usually
divided into two parts. The operation code and operands. The operation code of an instruction is a group of bits that
define the operations such as add, subtract, multiply, shift, and complement. The operands are the data on which the
operation is to be performed.

Opcode Operands

Computer Registers:
Computer instructions are normally stored in consecutive memory locations and are executed sequentially one
at a time. The control unit reads an instruction from a specific address in memory and executes it. It then continues by
reading the next instruction in sequence and executes it, and so on. This type of instruction sequencing needs a counter
to calculate the address of the next instruction after execution of the current instruction is completed. It is also
necessary to provide a register in the control unit for storing the instruction code after it is read from memory. The
computer needs processor registers for manipulating data and a register for holding a memory address. Different
registers used in a computer are:

Data Register (DR): This register holds the operands.

Address Register (AR): Holds the address of data and instructions.
Accumulator (AC): An accumulator is a type of register included in a CPU. It acts as a temporary storage location
which holds an intermediate value in mathematical and logical calculations. Intermediate results of an operation are
progressively written to the accumulator, overwriting the previous value.
Instruction Register (IR): Instruction Register holds the instruction to be executed.
Memory Address Register (MAR): Memory Address Registers are those registers that holds the address for memory
unit.
Memory Buffer Register (MBR): Memory Buffer Register stores instruction and data received from the memory and
sent to the memory.
Program Counter (PC): A program counter is a register in a computer processor that contains the address (location)
of the instruction being executed at the current time. As each instruction gets fetched, the program counter
increases its stored value by 1.
Computer Instructions
A basic computer has three instruction code formats which are:
1. Memory - reference instruction

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2. Register - reference instruction
3. Input-Output instruction

Memory - reference instruction

In Memory-reference instruction, 12 bits of memory is used to specify an address and one bit to specify the
addressing mode 'I'.

Register - reference instruction

The Register-reference instructions are represented by the Opcode 111 with a 0 in the leftmost bit (bit
15) of the instruction.

Input-Output instruction

Just like the Register-reference instruction, an Input-Output instruction does not need a reference to memory
and is recognized by the operation code 111 with a 1 in the leftmost bit of the instruction. The remaining 12 bits are
used to specify the type of the input-output operation or test performed.

Memory locations and addresses(important)

• Bits - the basic unit of memory is the binary digit, a bit contains a "0" or "1".
• The memory is organized so that the contents of one word, containing n bits, can be stored or retrieved in one
basic operation.

• Addresses- distinct name for location in memory where data is stored or retrieved
• Have 2k addressable locations .
• Use numbers from 0 to 2k – 1
• Byte is 8 bits
• Word length of memory ranges from 16 to 64 bits
The name big-endian is used when lower byte addresses are used for the most significant bytes (the leftmost bytes)
of the word.
The name little-endian is used for the opposite ordering, where the lower byte addresses are used for the less
significant bytes (the rightmost bytes) of the word.

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Instruction cycle:
A program residing in the memory unit of a computer consists of a sequence of instructions. These
instructions are executed by the processor by going through a cycle for each instruction.
In a basic computer, each instruction cycle consists of the following phases:
1. Fetch instruction from memory.
2. Decode the instruction.
3. Read the effective address from memory.
4. Execute the instruction.

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Fetch Stage: The next instruction is fetched from the memory address that is currently stored in the program
counter and stored into the instruction register. At the end of the fetch operation, the PC points to the next instruction
that will be read at the next cycle.
Decode Stage: During this stage, the encoded instruction presented in the instruction register is
interpreted by the decoder.
Read the effective address: In the case of a memory instruction (direct or indirect), the execution phase will be
during the next clock pulse. If the instruction has an indirect address, the effective address is read from main memory,
and any required data is fetched from main memory to be processed and then placed into data registers. If the
instruction is direct, nothing is done during this clock pulse. If this is an I/O instruction or a register instruction, the
operation is performed during the clock pulse.
Execute Stage: The control unit of the CPU passes the decoded information as a sequence of control signals to the
relevant function units of the CPU to perform the actions required by the instruction, such as reading values from
registers, passing them to the ALU to perform mathematical or logic functions on them, and writing the result back to
a register.
Timing and control:
All sequential circuits in the Basic Computer CPU are driven by a master clock, with the exception of the
INPR register. At each clock pulse, the control unit sends control signals to control inputs of the bus, the registers, and
the ALU.
Control unit design and implementation can be done by two general methods:
 In simple words, the hardwired control unit generates the control signals to execute the instructions in a
proper sequence and at the correct time. The hardwired control unit is created with the hardware; it is a
circuitry approach. It is designed for the RISC style instruction set. A hardwired circuit organization is shown
in the figure below. Let us discuss all the components one by one, in order to understand the “generation of
control signals” from this circuitry organization.

Microprogrammed Control Unit:

1) A control unit with its binary control values stored as words in memory is called as microprogrammed control.
Each word in the control memory contains microinstruction that specifies one or more microperations for the system.
A sequence of microinstructions constitutes a micro program.
2) Microprogrammed implementation is a software approach in contrast to the hardwired approach.
3) It deals with various units of software but at the micro level i.e. micro-operation, micro instruction, micro-program
etc.
4) Different key elements used for implementation of a control unit using microprogrammed approach is shown in fig.
below:

5) Control Memory:
The set of microinstruction is stored in control Memory (CM) also called as control store.
6) Control Address Register (CAR):
It contains the address of next microinstruction to be read. This is similar to the program counter(PC) which
stores the address of the next instruction.
7) Control Buffer Register(CBR):When microinstruction is read from the control memory, it is transferred to a control Buffer
Register (CBR), which is similar to the instruction Register (IR) that stores the opcode of the instruction read from the memory.
8) Sequencing:

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It loads the control Address register with the address of the next instruction to be read and issues a read
command to control memory.
Microprogrammed Control Unit Organization:

Figure: Basic Organization of Microprogrammed Control Unit

The microroutines for all instruction in the instruction set of a computer are stored in a special memory called
the control memory (CM). The control unit can generate the the control signals for any instructions by sequentially
reading the control words of the corresponding micro-routine from the control store. To read the control words
sequentially from the control memory, a microprogram counter (µPC) is used. Every time a new instruction is loaded
into the IR the output of the block labelled ‘starting Address Generator’. is loaded into the µPC. The µPC then
automatically incremented by one, by the clock. So that successive microinstructions are fetched from the control
memory.
Difference between Hardwired and Microprogrammed control unit(important)

Hardwired control unit Microprogrammed control unit

Technology is circuit based Technology is Software based
It is implemented through flip flops , gates , Microinstructions generate signals to control the
decoder sets execution of instructions
Fixed instruction format Variable instruction format
Instructions are register based Instructions are not register based
ROM is not used ROM is used
Faster decoding Slower decoding
Difficult to modify Easily modified
Chip area is less Chip area is large
Bus organization:
Bus is a group of conducting wires which carries information, all the peripherals are connected to microprocessor
through Bus. There are three types of buses.
Address bus – It is a group of conducting wires which carries address only.
Data bus –It is a group of conducting wires which carries Data only. Data bus is bidirectional because data
flow in both directions, from microprocessor to memory or Input/Output devices and from memory or Input/Output
devices to microprocessor. When it is write operation, the processor will put the data (to be written) on the data bus,
when it is read operation, the memory controller will get the data from specific memory block and put it into the data
bus.
Control bus –It is a group of conducting wires, which is used to generate timing and control signals to
control all the associated peripherals, microprocessor uses control bus to process data, that is what to do with selected
memory location. Some control signals are:
 Memory read
 Memory write
 I/O read
 I/O Write
 Opcode fetch
Module 2
Central Processing Unit:
The architecture of the Central Processing Unit (CPU) operates the capacity to function from “Instruction Set
Architecture” to where it was designed. The architectural design of the CPU is Reduced instruction set computing
(RISC) and Complex instruction set computing (CISC).

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What is RISC?
A reduced instruction set computer is a computer that only uses simple commands that can be divided into
several instructions that achieve low-level operation within a single CLK cycle, as its name proposes “Reduced
Instruction Set”. The RISC is a Reduced Instruction Set Computer microprocessor and its architecture includes a set of
instructions that are highly customized. The main function of this is to reduce the time of instruction execution by
limiting as well as optimizing the number of commands. So each command cycle uses a single clock cycle where
every clock cycle includes three parameters namely fetch, decode & execute.

What is CISC?
A complex instruction set computer is a computer where single instructions can perform numerous low-level
operations like a load from memory, an arithmetic operation, and a memory store or are accomplished by multi-step
processes or addressing modes in single instructions, as its name proposes “Complex Instruction Set ”.So, this
processor moves to decrease the number of instructions on every program & ignore the number of cycles for each
instruction. It highlights to assemble complex instructions openly within the hardware as the hardware is always as
compared with software.

General Register Organization(Important: essay question)

Generally CPU has seven general registers. Register organization show how registers are selected
and how data flow between register and ALU. A decoder is used to select a particular register.
The output of each register is connected to two multiplexers to form the two buses A and B. The
selection lines in each multiplexer select the input data for the particular bus.
. The A and B buses form the two inputs of an ALU. The operation select lines decide the micro operation to
be performed by ALU. The result of the micro operation is available at the output bus. The
output bus connected to the inputs of all registers, thus by selecting a destination register it is possible to store the
result in it

A bus organization for seven CPU register

EXAMPLE: To perform the operation R3 = R1+R2 We have to provide following binary selection variable
to the select inputs.
SEL A: 001 -To place the contents of R1 into bus A.
SEL B: 010 - to place the contents of R2 into bus B
SEL OPR: 10010 – to perform the arithmetic addition A+B
SEL REG or SEL D: 011 – to place the result available on output bus in R3.
Register and multiplexer input selection code

Binary SEL-D or
SELA SELB
code SEL-REG

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000 Input Input ---
001 R1 R1 R1
010 R2 R2 R2
011 R3 R3 R3
100 R4 R4 R4
101 R5 R5 R5
110 R6 R6 R6
111 R7 R7 R7

Operation with symbol

Operation selection
Operation symbol
code
0000 Transfer A TSFA
0001 Increment A INC A
0010 A+B ADD
0011 A-B SUB
0100 Decrement A DEC
0101 A AND B AND
0110 A OR B OR
0111 A XOR B XOR
1000 Complement A COMA
1001 Shift right A SHR
1010 Shift left A SHL

What is CONTROL WORD? (Important)

 The combined value of a binary selection inputs specifies the control word.
 It consists of four fields SELA, SELB, and SELD or SELREG contains three bit each and SELOPR field
contains four bits thus the total bits in the control word are 14-bits.
3 3 3 5
SELREG
SEL A SELB SELOPR
OR SELD

FORMAT OF CONTROL WORD

The three bit of SELA select a source register of the A input of the ALU. The
three bits of SELB select a source registers of the B input of the ALU.
The three bits of SELED or SELREG select a destination register using the decoder. The
five bits of SELOPR select the operation to be performed by ALU.

CONTROL WORD FOR OPERATION R2 = R1+R3

SELD OR SEL -
SEL A SEL B
SEL REG OPR

001 011 010 0010

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Stack Organisation(Important Essay)

Stack is a storage structure that stores information in such a way that the last item stored is the first item
retrieved. It is based on the principle of LIFO (Last-in-first-out). The stack in digital computers is a group of memory
locations with a register called Stack Pointer that holds the address of top of element.
Stack Operations
The two operations of a stack are:
Push: Inserts an item on top of stack.
Pop: Deletes an item from top of stack.
Implementation of Stack
In digital computers, stack can be implemented in two ways:
Register Stack
Memory Stack
Register Stack
A stack can be organized as a collection of finite number of registers that are used to store temporary
information during the execution of a program. The stack pointer (SP) is a register that holds the address of top of
element of the stack.

The push operation is implemented with the following sequence of micro operations Initially
SP=0, EMPTY=1 and FULL=0
If the stack is not full(if FULL=0), a new item is inserted with a push operation SP 
SP + 1 increment SP
M[SP]  DR write item on top of the stack
If (SP=0) then (FULL  1) check if stack is full
EMPTY  0 mark the stack is not empty
Pop operation
DR  M[SP] Read item from top SP
 SP-1 Decrement SP
If (SP=0) then (EMPTY  1)check if stack is empty
FULL  0 Mark the stack is not full
Memory Stack
A stack can be implemented in a random access memory (RAM) attached to a CPU. The implementation of a
stack in the CPU is done by assigning a portion of memory to a stack operation and using a processor register as a
stack pointer. The starting memory location of the stack is specified by the processor register as stack pointer.

Stack Applications
Reverse Polish Notation

Addressing Modes(Very important essay)

The term addressing modes refers to the way in which the operand of an instruction is specified. The addressing
mode specifies a rule for interpreting or modifying the address field of the instruction before the operand is actually
executed.
An assembly language program instruction consists of two parts

Opcode Operand

Implied Mode
 In this mode the operands are specified implicitly in the definition of the instruction.
 For example, the instruction "complement accumulator" is an implied-mode instruction because the operand
in the accumulator register is implied in the definition of the instruction.

 In fact, all register reference instructions that use an accumulator are implied-mode instructions. Zero-address
instructions in a stack-organized computer are implied-mode instructions since the operands are implied to be
on top of the stack.
Immediate Mode
 In this mode the operand is specified in the instruction itself. In other words, an immediate-mode instruction
has an operand field rather than an address field.

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 The operand field contains the actual operand to be used in conjunction with the operation specified in the
instruction. Immediate-mode instructions are useful for initializing registers to a constant value.

Register Mode
 In this mode the operands are in registers that reside within the CPU. The particular register is selected from a
register field in the instruction.

Register Indirect Mode

 In this mode the instruction specifies a register in the CPU whose contents give the address of the operand in
memory. In other words, the selected register contains the address of the operand rather than the operand
itself.
 Before using a register indirect mode instruction, the programmer must ensure that the memory address of the
operand is placed in the processor register with a previous instruction.
 A reference to the register is then equivalent to specifying a memory address.

Auto increment or Auto decrement Mode

 This is similar to the register indirect mode except that the register is incremented or decremented after (or
before) its value is used to access memory.
 When the address stored in the register refers to a table of data in memory, it is necessary to increment or
decrement the register after every access to the table.
 This can be achieved by using the increment or decrement instruction.
 Sometimes the value given in the address field is the address of the operand, but sometimes it is just an
address from which the address of the operand is calculated.
 To differentiate among the various addressing modes it is necessary to distinguish between the address part of
the instruction and the effective address used by the control when executing the instruction.
 The effective address is defined to be the memory address obtained from the computation dictated by the
given addressing mode. The effective address is the address of the operand in a computational- type
instruction.
 It is the address where control branches in response to a branch-type instruction.

Direct Address Mode

 In this mode the effective address is equal to the address part of the instruction.

 The operand resides in memory and its address is given directly by the address field of the instruction. In a
branch-type instruction the address field specifies the actual branch address.

Indirect Address Mode

 In this mode the address field of the instruction gives the address where the effective address is stored in
memory. Control fetches the instruction from memory and uses its address part to access memory again to
read the effective address.
 A few addressing modes require that the address field of the instruction be added to the content of a specific
register in the CPU. The effective address in these modes is obtained from the following computation:
effective address = address part of instruction + content of CPU register
 The CPU register used in the computation may be the program counter, an index register, or a base register. In
either case we have a different addressing mode which is used for a different application.

Relative Address Mode

 In this mode the content of the program counter is added to the address part of the instruction in order to
obtain the effective address.
 The address part of the instruction is usually a signed number (in 2' s complement representation) which can
be either positive or negative. When this number is added to the content of the program

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counter, the result produces an effective address whose position in memory is relative to the address of the
next instruction.

Indexed Addressing Mode

 In this mode the content of an index register is added to the address part of the instruction to obtain the
effective address.
 The index register is a special CPU register that contains an index value.
 The address field of the instruction defines the beginning address of a data array in memory.
 Each operand in the array is stored in memory relative to the beginning address. The distance between the
beginning address and the address of the operand is the index value stored in the index register.
 Any operand in the array can be accessed with the same instruction provided that the index register contains
the correct index value.
 The index register can be incremented to facilitate access to consecutive operands. Note that if an index type
instruction does not include an address field in its format, the instruction converts to the register indirect
mode of operation.

Base Register Addressing Mode

 In this mode the content of a base register is added to the address part of the instruction to obtain the effective
address. This is similar to the indexed addressing mode except that the register is now called a base register
instead of an index register.
 The difference between the two modes is in the way they are used rather than in the way that they are
computed. An index register is assumed to hold an index number that is relative to the address part of the
instruction.
 A base register is assumed to hold a base address and the address field of the instruction gives a displacement
relative to this base address. The base register addressing mode is used in computers to facilitate the
relocation of programs in memory.
 When programs and data are moved from one segment of memory to another, as required in
multiprogramming systems, the address values of instructions must reflect this change of position.

Instruction classification
An instruction can be classified as
 Three Address
 Two address
 One Address
 Zero Address
Three Address
This type of instructions contains the address of three operands. eg:-
Add A,B,C
Two Address
This type of instructions contains the address of two operands. eg:-
Add A,B

One Address
This type of instruction contains the address of one memory operand. eg:-
Load A, Store A

Zero Address

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This type of instruction does not use an address field. A stack based computer do not use address field in instruction.

Program control
Types of Program Control Instructions
Program Control Instructions are the machine code that are used by machine or in assembly language by user to
command the processor act accordingly. These instructions are of various types.
Types of Program Control Instructions:
There are different types of Program Control Instructions:
1. Compare Instruction:
Compare instruction is specifically provided, which is similar t a subtract instruction except the result is not
stored anywhere, but flags are set according to the result.
Example:
CMP R1, R2 ;
2. Unconditional Branch Instruction:
It causes an unconditional change of execution sequence to a new location.
Example:
JUMP L2
Mov R3, R1 goto L2
3. Conditional Branch Instruction:
A conditional branch instruction is used to examine the values stored in the condition code register to determine
whether the specific condition exists and to branch if it does.
Example:

4. Subroutines:
A subroutine is a program fragment that lives in user space, performs a well-defined task. It is invoked by
another user program and returns control to the calling program when finished.
Example:
CALL and RET
5. Halting Instructions:
 NOP Instruction – NOP is no operation. It cause no change in the processor state other than an
advancement of the program counter. It can be used to synchronize timing.
 HALT – It brings the processor to an orderly halt, remaining in an idle state until restarted by interrupt, trace,
reset or external action.
6. Interrupt Instructions:
Interrupt is a mechanism by which an I/O or an instruction can suspend the normal execution of
processor and get itself serviced.
 RESET – It reset the processor. This may include any or all setting registers to an initial value or setting
program counter to standard starting location.
 TRAP – It is non-maskable edge and level triggered interrupt. TRAP has the highest priority and vectored
interrupt.
 INTR – It is level triggered and maskable interrupt. It has the lowest priority. It can be disabled by resetting
the processor.
Module 3
Memory Organization
Memory Hierarchy
The following memory hierarchy diagram is a hierarchical pyramid for computer memory. The designing of the
memory hierarchy is divided into two types such as primary (Internal) memory and secondary (External) memory.

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Memory Hierarchy Design
The memory hierarchy in computers mainly includes the following.
Registers
Usually, the register is a static RAM or SRAM in the processor of the computer which is used for holding the
data word which is typically 64 or 128 bits. The program counter register is the most important as well as found in all
the processors.
Cache Memory
Cache memory can also be found in the processor, however rarely it may be another IC (integrated circuit)
which is separated into levels. The cache holds the chunk of data which are frequently used from main memory.
Main Memory
` The main memory in the computer is nothing but, the memory unit in the CPU that communicates directly. It
is the main storage unit of the computer. This memory is fast as well as large memory used for storing the data
throughout the operations of the computer. This memory is made up of RAM as well as ROM.
Magnetic Disks
The magnetic disks in the computer are circular plates fabricated of plastic otherwise metal by magnetized
material. Frequently, two faces of the disk are utilized as well as many disks may be stacked on one spindle by read or
write heads obtainable on every plane. All the disks in computer turn jointly at high speed. The tracks in the computer
are nothing but bits which are stored within the magnetized plane in spots next to concentric circles. These are usually
separated into sections which are named as sectors.
Magnetic Tape
This tape is a normal magnetic recording which is designed with a slender magnetizable covering on an
extended, plastic film of the thin strip. This is mainly used to back up huge data. Whenever the computer requires to
access a strip, first it will mount to access the data. Once the data is allowed, then it will be unmounted. The access
time of memory will be slower within magnetic strip as well as it will take a few minutes for accessing a strip.

Main Memory

SRSM DRAM

Transistors are used to store

1. information in SRAM. Capacitors are used to store data in DRAM.

To store information for a longer time, contents of

Capacitors are not used hence no
the capacitor needs to be refreshed periodically.
2. refreshing is required.

SRAM is faster as compared to

3. DRAM. DRAM provides slow access speeds.

4. These are expensive. These are cheaper.

5. SRAMs are low density devices. DRAMs are high density devices.

6. These are used in cache memories. These are used in main memories.

Classification of ROM

MROM (Masked ROM)

The very first ROMs were hard-wired devices that contained a pre-programmed set of data or instructions.
These kind of ROMs are known as masked ROMs, which are inexpensive.

PROM (Programmable Read Only Memory)

PROM is read-only memory that can be modified only once by a user. The user buys a blank PROM and
enters the desired contents using a PROM program. Inside the PROM chip, there are small fuses which are burnt
open during programming. It can be programmed only once and is not erasable.
EPROM (Erasable and Programmable Read Only Memory)

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EPROM can be erased by exposing it to ultra-violet light for a duration of up to 40 minutes. Usually, an
EPROM eraser achieves this function. During programming, an electrical charge is trapped in an insulated gate
region. The charge is retained for more than 10 years because the charge has no leakage path. For erasing this charge,
ultra-violet light is passed through a quartz crystal window (lid). This exposure to ultra-violet light dissipates the
charge. During normal use, the quartz lid is sealed with a sticker.
EEPROM (Electrically Erasable and Programmable Read Only Memory)
EEPROM is programmed and erased electrically. It can be erased and reprogrammed about ten thousand
times. Both erasing and programming take about 4 to 10 ms (millisecond). In EEPROM, any location can be
selectively erased and programmed. EEPROMs can be erased one byte at a time, rather than erasing the entire chip.
Hence, the process of reprogramming is flexible but slow.
The advantages of ROM are as follows −

 Non-volatile in nature
 Cannot be accidentally changed
 Cheaper than RAMs
 Easy to test
 More reliable than RAMs
 Static and do not require refreshing
 Contents are always known and can be verified

Auxiliary memory

Auxiliary memory holds programs and data for future use, and, because it is non volatile (like ROM), it is
used to store inactive programs and to archive data. Early forms of auxiliary storage included punched paper tape,
punched cards, and magnetic drums. Since the 1980s, the most common forms of auxiliary storage have been magnetic
disks, magnetic tapes, and optical discs.

Magnetic Disk Drives

Magnetic disks are coated with a magnetic material such as iron oxide. There are two types: hard disks made
of rigid aluminium or glass, and removable diskettes made of flexible plastic. Hard drives generally have several disks,
or platters, with an electromagnetic read/write head for each surface; the entire assembly is called a comb. A
microprocessor in the drive controls the motion of the heads and also contains RAM to store data for transfer to and
from the disks. The heads move across the disk surface as it spins up to 15,000 revolutions per minute; the drives are
hermetically sealed, permitting the heads to float on a thin film of air very close to the disk’s surface. A small current is
applied to the head to magnetize tiny spots on the disk surface for storage; similarly, magnetized spots on the disk
generate currents in the head as it moves by, enabling data to be read. FDDs function similarly, but the removable
diskettes spin at only a few hundred revolutions per minute.
Data are stored in close concentric tracks that require very precise control of the read/write heads.
Refinements in controlling the heads have enabled smaller and closer packing of tracks—up to 20,000 tracks per inch
(8,000 tracks per cm) by the start of the 21st century—which has resulted in the storage capacity of these devices
growing nearly 30 percent per year since the 1980s. RAID (redundant array of inexpensive disks) combines multiple
disk drives to store data redundantly for greater reliability and faster access. They are used in high-performance
computer network servers.
Magnetic tape
Magnetic tape, similar to the tape used in tape recorders, has also been used for auxiliary storage, primarily
for archiving data. Tape is cheap, but access time is far slower than that of a magnetic disk because it is sequential-
access memory—i.e., data must be sequentially read and written as a tape is unwound, rather than retrieved directly
from the desired point on the tape. Servers may also use large collections of tapes or optical discs, with robotic devices
to select and load them, rather like old-fashioned jukeboxes.

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Optical discs
Another form of largely read-only memory is the optical compact disc, developed from
videodisc technology during the early 1980s. Data are recorded as tiny pits in a single spiral track on plastic discs that
range from 3 to 12 inches (7.6 to 30 cm) in diameter, though a diameter of 4.8 inches (12 cm) is most common. The
pits are produced by a laser or by a stamping machine and are read by a low- power laser and a photocell that generates
an electrical signal from the varying light reflected from the pattern of pits. Optical discs are removable and have a far
greater memory capacity than diskettes; the largest ones can store many gigabytes of information.
A common optical disc is the CD-ROM (compact disc read-only memory). It holds about 700 megabytes of
data, recorded with an error-correcting code that can correct bursts of errors caused by dust or imperfections. CD-
ROMs are used to distribute software, encyclopaedias, and multimedia text with audio and images. CD-R (CD-
recordable), or WORM (write-once read-many), is a variation of CD-ROM on which a user may record information
but not subsequently change it. CD-RW (CD-rewritable) disks can be re-recorded. DVDs (digital video, or versatile,
discs), developed for recording movies, store data more densely than does CD-ROM, with more powerful error
correction. Though the same size as CDs, DVDs typically hold 5 to 17 gigabytes—several hours of video or several
million text pages.
Cache Memory
• A small, fast memory inserted between main memory & processor
• Holds the currently active segments of a program and their data
• Effectiveness of cache mechanism is based on a property- locality of reference

Locality of reference
• Many instructions in localized areas of the program are executed repeatedly during some time period
and remainder program is accessed relatively infrequently
• 2 ways
– Temporal
• A recently executed instruction is likely to be executed again very soon
– Spatial
• Instructions in close proximity to a recently executed instruction are also likely to be
executed soon

Mapping Functions
 Associative Mapping
 Direct Mapping
 Set Associative Mapping
Associative Mapping
The associative memory stores both address and data. The address value of 15 bits is 5 digit octal numbers
and data is of 12 bits word in 4 digit octal number. A CPU address of 15 bits is placed
in argument register and the associative memory is searched for matching address.

Direct Mapping
The CPU address of 15 bits is divided into 2 fields. In this the 9 least significant bits constitute
the index field and the remaining 6 bits constitute the tag field. The number of bits in index field is equal to the
number of address bits required to access cache memory.

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Set Associative Mapping

The disadvantage of direct mapping is that two words with same index address can't reside in cache memory
at the same time. This problem can be overcome by set associative mapping. In this we can store two or more words
of memory under the same index address. Each data word is stored together with its tag and this forms a set.
Virtual Memory

• Techniques that automatically move program and data blocks into the physical main memory when they are
required for execution – virtual memory techniques
• Binary addresses that the processor issues for either instructions or data are called virtual or logical
addresses
• A special hardware unit called Memory Management Unit (MMU) translates virtual addresses into physical
addresses

PROCESSOR
Virtu

Da
Phys
MM
CACHE
Phys
Da

MAIN MEMORY
DMA

DISK STORAGE
Address Translation

• Assume all programs & data are composed of fixed length units called pages
• Pages consists of a block of words that occupy contiguous locations in main memory

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• Pages commonly range from 2K to 16K bytes in length

Process

 Each virtual address is interpreted as a virtual page number, followed by an offset that specifies the location of
a particular byte within a page
 Information about main memory location of each page is kept in a page table
 An area in the main memory that can hold one page is called a page frame
 The starting address of the page table is kept in a page table base register

Page Virtual Offs

Physical

Page Offs

Module 4
Parallel Computer Structures:
Introduction to parallel processing
Technique to provide simultaneous data processing tasks

• To increase computational speed

• Increase throughput- amount of processing that can be accomplished during a given time interval
• Amount of hardware increases with parallel processing
• Established by distributing the data among multiple functional units
Pipeline Computers
Pipeline computer is a type of parallel computer which performs overlapped computations to exploit temporal
parallelism. An instruction cycle consists of four steps:
Instruction fetch, instruction decode, operand fetch and execute.
The following figures represent the space diagram for a pipelined computer and a non pipelined computer

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Space-time diagram for Non-pipelined Processor

Space-time diagram for Overlapped Instruction

pipelined Processor

Flynn’s Classification
Flynn’s classification is based on the multiplicity o0f instructions and data streams. the term stream is used to
denote a sequence of items.
Flynn's classification divides computers into four major groups that are:
1. Single instruction stream, single data stream (SISD)
2. Single instruction stream, multiple data stream (SIMD)
3. Multiple instruction stream, single data stream (MISD)
4. Multiple instruction stream, multiple data stream (MIMD)

SISD
SISD stands for 'Single Instruction and Single Data Stream'. It represents the organization of a single
computer containing a control unit, a processor unit, and a memory unit.Instructions are executed sequentially, and
the system may or may not have internal parallel processing capabilities. Most conventional computers have SISD
architecture like the traditional Von-Neumann computers.

SIMD

SIMD stands for 'Single Instruction and Multiple Data Stream'. It represents an organization that includes
many processing units under the supervision of a common control unit. All processors receive the same instruction
from the control unit but operate on different items of data. The shared memory unit must contain multiple modules so
that it can communicate with all the processors simultaneously.

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MISD

MISD stands for 'Multiple Instruction and Single Data stream'. MISD structure is only of theoretical
interest since no practical system has been constructed using this organization. In MISD, multiple processing units
operate on one single-data stream. Each processing unit operates on the data independently via separate instruction
stream.

MIMD:

MIMD stands for 'Multiple Instruction and Multiple Data Stream'. In this organization, all processors in a
parallel computer can execute different instructions and operate on various data at the same time. In MIMD, each
processor has a separate program and an instruction stream is generated from each program.

Module 5

Pipelining and Vector processing

Arithmetic Pipeline

Arithmetic Pipelines are mostly used in high-speed computers. They are used to implement floating-point
operations, multiplication of fixed-point numbers, and similar computations encountered in scientific problems.To
understand the concepts of arithmetic pipeline in a more convenient way, let us consider an example of a pipeline unit
for floating-point addition and subtraction.The inputs to the floating- point adder pipeline are two normalized floating-
point binary numbers defined as:

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a 3
X = A * 2 = 0.9504 * 10 Y
= B * 2b = 0.8200 * 102
Where A and B are two fractions that represent the mantissa and a and b are the exponents.
The combined operation of floating-point addition and subtraction is divided into four segments. Each
segment contains the corresponding sub operation to be performed in the given pipeline. The sub operations that are
shown in the four segments are:

1. Compare the exponents by subtraction.

2. Align the mantissas.
3. Add or subtract the mantissas.
4. Normalize the result.

The following block diagram represents the sub operations performed in each segment of the pipeline.

Instruction Pipeline

Pipeline processing can occur not only in the data stream but in the instruction stream as well. Most of the
digital computers with complex instructions require instruction pipeline to carry out operations like fetch, decode and
execute instructions.

In general, the computer needs to process each instruction with the following sequence of steps.

1. Fetch instruction from memory.

2. Decode the instruction.
3. Calculate the effective address.
4. Fetch the operands from memory.
5. Execute the instruction.
6. Store the result in the proper place.
Each step is executed in a particular segment, and there are times when different segments may take different times to
operate on the incoming information. Moreover, there are times when two or more segments may require memory access at
the same time, causing one segment to wait until another is finished with the memory. The organization of an instruction
pipeline will be more efficient if the instruction cycle is divided into segments of equal duration. One of the most common
examples of this type of organization is a Four-segment instruction pipeline.

A four-segment instruction pipeline combines two or more different segments and makes it as a single
one. For instance, the decoding of the instruction can be combined with the calculation of the effective address into
one segment.

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The following block diagram shows a typical example of a four-segment instruction pipeline. The
instruction cycle is completed in four segments.

Vector Processing:
Applications

• Long range weather forecasting

• Petroleum explorations
• Seismic data analysis
• Medical diagnosis
• Space flight stimulations
• AI
• Image processing

Vector Processing
Eliminates the overhead associated with time for fetch and execution of instructions in the program loop
Allows operations to be specified with a single vector instruction of the form
C(1:100)=A(1:100)+B(1:100)
The vector instruction includes the initial address of the operands, length of vectors and operation to be
performed

Array Processors(Important)
Array processors are also known as multiprocessors or vector processors. They perform computations on
large arrays of data. Thus, they are used to improve the performance of the computer.
Types of Array Processors
There are basically two types of array processors:
• Attached Array Processors
• SIMD Array Processors

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Attached Array Processors

An attached array processor is a processor which is attached to a general purpose computer and its purpose is
to enhance and improve the performance of that computer in numerical computational tasks. It achieves high
performance by means of parallel processing with multiple functional units.

SIMD Array Processors

SIMD is the organization of a single computer containing multiple processors operating in parallel.
The processing units are made to operate under the control of a common control unit, thus providing a single
instruction stream and multiple data streams.

A general block diagram of an array processor is shown below. It contains a set of identical processing
elements (PE's), each of which is having a local memory M. Each processor element includes an ALU and registers.
The master control unit controls all the operations of the processor elements. It also decodes the instructions and
determines how the instruction is to be executed.

The main memory is used for storing the program. The control unit is responsible for fetching the
instructions. Vector instructions are send to all PE's simultaneously and results are returned to the memory. The best
known SIMD array processor is the ILLIAC IV computer developed by the Burroughs corps. SIMD processors are
highly specialized computers. They are only suitable for numerical problems that can be expressed in vector or matrix
form and they are not suitable for other types of computations.

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