MI -itiodu eti en VLST dugn £ tating

MoDULE -1
LNTRoDUCTCON

BRIEF HisTORY
’ The uhcle demain emputi ng enteed
Aomputing entud into a new aa
o elect kenic miniatuzation wth the iwertion trans to
n 1947. y Niliam B Shokley , Tohn Badeen,waltu HBrattan
ELectaonis today is chaact uised
Righ
today
aeliati tity
y

High apud
Lotw cest
Low powu disipation
’ VLSI
o! ati ng an Ic y cam bining vey
lavge nunba of thansistou en

Jack k:Lly dutt the IC in the

Bince then 4 qeneati ons Tc have evelved namely
* SSI - Smal Saale
nteqration : have thansiy tou in the
ade
Legee gotu ike 74 04 ete
MSL - Medium Saale Intqration; have sansis te in the
arder LOD- loDD . En:- M
ultiplene, centes
Lage Scale Integsation : have thansisteu pto
to, oUD. En: 8- ht paoceuou
* VLST -
teumed
Vey Lauge Saale Integation : 2cs byond 1980 wee
VLSE wth thansistos qriate Ehan io, oD.
En: l6- bit paOCes Gs eto.

-7 MooREs LAW : Akateu that the numbea ef tianscsteu cn a

chip detes eveay
’ DENNARD< ScALING : statu that au transcztou shuink, they beceme
fautu,) rans unme leu pewe and cheapu to nanuhactue
Nayana Ky Dept f ECE, sVzr
 VLSI duiga 2tulig
MOS TRANSISTOR
Metal- Oude- Semiconductor CMOS) athtue ueated
dy supainpeag seveual Layu enducbing and inutating
lateuals. TAansiatee epuation s cntaolled Jy elect a felds
hene the nane
Fild E}eet Thanster (FET).
’ CMOS technology paovedes hwo kype
tran'tou -
trars's tou-nM0S 2 pMos
hos-setion and
aate ymbel Hhese tanstoy ae shoon belo
Souue Daain Souce DAain
Poysiicorn
sio
nt nt
pt pt
p- bype bcdy /buk n-bype kodylbulk
a) nMOs thasto
b) pMOS tranuste
nMOS canstution i
’ n p- bype ubetrata Cbody lbulk), two heavely
a
doped
Ag one vae fomed y di fuion . The kwD nt eg nt
bouice and din teninals. ove aapaent
’ A thin insulading dage o
hetween the over the p-subsbat
s0e and dain tnals
Jau
Aepesent
Pelylition is
the gate tuminal. depasited ovea Si0, layee. The paSi
’ Thu
body |bulk NMOS alway gunded.

PMOs censtuction :
’ In a n-type sulstat (body/bulk), twD
agons are
kuave'y dapud pt
and dain teminds.
’ Aboe the sulstate thue is
Aimila to nMOS
Si0, laye and Poly Selien (g)
The body /buk e pmos is cannected to pascteic potertiad (Von)
3
Nayana K, Dept of ECE, SVIT
 VLSI dexqA 2 tatung
> The et weon he &ource and oan s called as charnel.
gion
Lenduction takes plae egion.
’ The gat s th centad input uhich alhed th low
vcuiien etween and d i i .

For an nMos tuansis toe Lhe Jody is swally qrounded, so

the p-n nctionu e thu sOce and uain o eseVese biased.

gote veltag u o(gounded) , thu nMOS transisto is

OFF and n0 veent tlous.
" I a poatkive votage is ayied do the gate , it eate an
electie eld tat attets heee electaons delo tho Si-sio)
inteulaa lah annet augcon)
" the pouitie vetuge i fethes ineaned
inceased aloe the
theheld vettage (Vt) an n-type channel is foamed between
seuse and dain cuating a path for eletnors do flow em
to o a i . nd tus ent can The tanss to is ON.

pMOs tanssto , the s held at e poutive vettag

kody
If the gat1 voltag is positive ) the pMOS trans's tor s OFF
and no vewent 7los.
applied to the gate, t wcate an
electic
nagate retag
fild that attacta fu beles Ctve chag) in the
vchannel.
I! the futh deceased delow the
negative velkage
thies hold velta (Ve) a P-ype chanel is fem ed wuating
ath tor hole do Blew uing in cment low. Trensstor kcN
nMOS transs boi tuns ON
OFF 6= O. PMOs t s t tuuns ON fo G=0 and tns
G= 1

AMOS: PMOS:
d

Nayana k, Dept.of ECE, SVIT 4

 VLST deqa& tuing
conecli on and ehavie o Aeues nd paallel
thansistsiu i deprcted elow.

a) n o s sew'es

OFF OFF OFF ON

b) pMos sues a

b b b
ON OFF OFF OFF

C) n MOS pauallel
a

ON ON
OFF

d) pMOS pauallel |a
a

|b
ON ON ON OFF

7The posstble cutput leves in CMOS bucd on status o

s shour below
pil-up CpMos) and put - doun (nMos)
IPULL-UP OF|PULL- UP ON
PUL-DOWN OFF
PULL- DOWN ON X

Nayarak, Dept-of ECE, SVIT

 CM0S L0GTC (Komplementasy Mos)
CMOS gate Iiar an nMOS pull- doun netwek to
Cornet the aut put do 0(GND) and pMos pull- up
netuok
do votect de out put to I(
Vop) The net works
Auch lhat
swangd
below
VDD

PMOS pMOS pases staong I cand weak o

nttwak

Inpub + -Output
nMOS
Pul-doun nMOs pases 6ticng 0 and ueakI
netwek

GND
CMOS netwonk
The nunbe tranCs bos n each netwak s
equal to tle
nunbu o inputs in the c i t .
CMOS AND opati an () coned n MOS wn seus
and PMOS n pavalle.
OR
epuat or (t) conneet nMOs
in parallel and
pMOS in
nMO S PMOS

AND (A8) OR(A+B) AND (A.B) OR (A+ B)

opertion operaion opeatien
SERIes PARALLEL PARALLEL S ERIES

Nayana k, Dept o ECE, S\I1

 VLSI duiga tutig
) CMO0s CNVER TER
-’ The symbol) schem atc and thut talte an invte i shown
below
VbD
S

A PMOS
D
A
D

a)symbol n MOS
c) Tauth table

GND
b) shemati'c
b) shous the schemaic e! CNOS a'hvtei 0 NoT gau
constauct ed n MOS and ono pMOS tYul'ste.
’ Whun inpt A iu o , nMOs tans'stoe is OFF annd p MOS tarsUs tay
A ON , thus te otput Y is puled p to ', becose it is
cennet ed &houn belo
VDD

A=o ON

Y=
A=0
OFF

7 When input Au1 nMOS than'sto rs ON and

pMos
tranu' to thes the cutput pulled doun to o'
because to GND as &hor lelow
VDD

A=l

Y=0
A-

Nayona Ky, Dept. e ECE,sVIT

 VLS
denga teutig
ii) NAND gat
’ 1he symbol, & hematie and tuth tate 2-1)P NAND
gat
adown delou

A A B
Y= AB PI P2

B D

Y=AB
a) symbol A

c) tauth tablo
N 2
s
VGND
b) shematic
Suith model
o) A= ,B=0 o) A = o, B
* When A=0, B=0 * hen A=0, Bl>
Pl,?2 ae ON
PI is oN, P2i's OFF
NI,N2 ae oFF,
Y NI s OFF, N2 i ON
Output Yùpuled p Y=
Output Yi pulled p
to VDD thsough prMos ko Vop thueugh pMas
trans'stor thcss tor.
GND

") A=1, B=

* hlhen A=l,B=0 =) * When A-), Bl)

PI is OFF, P2 is ON
jo Pl ) P2. ae oFE
NIiB CN, N2 IB DEF N, N2 au ON
Yelo
Dutput y u pulld up Qutput Y pulled down
to VDo
transte
thueugh p oS to GND thwaugh nMos
trans to
4ND

Nayana- k, Dept. o ECE, SVIT

 VLSE duiga ktuting
iii) NoR GATE
Vpo

A Y= A+B A-
B

-L
ABY
A Yx A+B

iv) CoMPOUND 6ATE

Cambination 6ees and puale s u th t Aucte
y= AB+CD * y= (A+ B+c ).D
VDD
T Von

Y AB+ Co
-Y=A+ Bt).D

Y= APt CO is AND-OR- INVERT(A0T) Y=(A+ B+ C).D ç OR-AND-INVERT[OAI)

NoTE:
CMOS «ineuts , aay give cemplementay outputi
invatng autpud. To clt ain uncempleentay non-invatu rg cutpuly
an additiona invete is used at the autput
nMOS -Sr'es nMOS- pauatlel
A ND
operation pMOS- seies
pMOS- paralles

Nay ara K, Dept. o ECE, SVIT

 VLSI desiqa tang
v) PA SS TRANSISTOR and TRANSMISSTON GATES

" PASS TRANSIS10R

hou
’ The stngth
signal
yiomate an ideal vottage strenge ngnal , tho
more cunent t can
The powe supply hails (VDp & GND) aue the sQWce o< the stronget
An nMOs tauns'ste putet suith uhen
thus nMos Pases STRONG 0 .
pauing a o

’ But the n Mos transsto

a | ' . The
nat a
pestet s t h uhrn
is leus thn Vpp
pauing
thus e nMOs
hugh veltage devel
Puses lEAK)
’A pMOS tar'st has opposcke dehaieL . It paue STRON6I
ond hEAK O
-’ When us ed inei'v duay these trorsLS tos aie knoun ay PASS Thanss
Enput Output
OMOS

WEAK I
J input Output
þMoS WEA Ko

STRONGI

TRANSMISSION GATE
A Parallel cembinatien nMOS and pMOS trsCs te u
called tiansmsion s shoun n below

Symbels o tarm'sier
gati
iput output
b
a

trnmu'sion
gate ques Jetth the cantiel input cq)
and t cemplemnt Cgb) This called clouble nail logic
kihen g= gb=O , beth nMOs RpMos awee ON )we say Th is ON.
klhen g=0, qb=l, both n MOs & p MOs ae DFF, we Say TG I8 OFF.
Nayra., Dept. o ECE ,SV1T lo
 VLSL deuiqnk tsiag
’SLce TG wses both OMOS nd pMbs , Lt overcomes the preblern
(degaded olP:) A TG gevea beth STRONG and 'o
Input g=, gb=o Output
STRONG o
glgbs o
&TRONGI

CONTROL INPUT TG stats OUT PUT VALVE

g=l> gb=o output -unput (strong ol)

Ta is OEF output = z (highinpedana)

Vi) TRISTATES
’ Tcstates indiicates 3 states namaly O, I 2 z (tiyhimpedana)
TRISTATE BUFFER

En
En En A
4 En=l, output
Y=A
A X
|En al En =0, cutput c lating

TRISTATE INVERTER

and c e ' t tu'stte invete u shoun blow

En -Vbp VDD
A

A
A
En

" When En =0, En=l, both

enalo thanssteu ae DFF. -y-
thu cutput will float|Y=z|
En

"When En=l, En =D, beth

enalte tharscatos ae ON.
the cutput ul e VGND GND
GND
comphment of input|y- En0 En= |
Y=A
Nayana.K, Dept .o ÉCE, SVTT
 VLSI desgn 2 tubrg
viii) MULTIPLEXERS
’A utiplenea aelects the eutput hom sevua input
Uased on the select signal
’A 2: MUX has 2 inputs CDO DI) , one selet ure Cs) and olp y.
It selec input Do when S=0 and DI Auhen
uhen S=
S= | as shown bele

DO Do DIY
DI
X
X Y= SD0 + SDI
X
X

Two tiusmu'sion
a sheun lelow. Thegatea
can le eanneted to a 2'|Mux
selet s and S enae only one Ta at atime as shouh

DO
S=0,3-I
DO
Do

-Y=Do -y- DI
S=i,3=o
DI
D) --
ix) SEQUENTTAL
VLST desaga Etesting
CIRCUITS i- hawe memoy , thi o<Ps
LATCHES Aoth unent and phevcaudapends
hputs,
-> latehes e level
taiggud. A D- lateh u'lt jhem
thomn 221 MUx
end two inveite shon un in a lelow. The
The nveutes at
Aike a eedback path
CLK

CLIC D
D
LAtCH
X Q(Previty
Stak )

a) D-lateh wag MUX b) ynbol and tuth tab

’ The MUx can e hut
g(> hem a pai o t aenumusion g ates
When lk =| the datch (enabed)
is tansparert and D
’ When ek= 0, the
ateh tho
uend the nvete
halds the ewent atate
fudback
I.e the eutput hemains andene telyl67)
prev'ou state
D D

LK

CL K
d) ceK=.,a-D e) cLK=0, =Q
'g ) D- Leth us T-4 (prevstato)

The-latdh s evel-senste leceLy e the tate the autpt is

oependant An the levee the clo ck as &hsun lelow.
’ This d a posctive devel-sens ve leth
cenet ony by hveting the contisl
ko the TG, the lotch beceuy negtir - level sensitie.
CLK
input D ç
changu in input
D heflect ed at the eutput only
Uk=| ) else t emans n
pev'eus state
13
Nayona K, Dept. of ECE, SVIT
 Btauetuaal aepresertati on
A stauctural ape'ation speerties how component! ase
intecenncted to ' peuterm the Aequi'ned kunction
A tctunas desiption language modd s kattie dogi't kay
the
follag
Paxt gatname (npuct) ’outpt
thanscste dlain gat
-P£et
End.
*stuctwal speciicatian of an iwert
Vop
Past uv( in)’ ut PFeT
Nget cut ln -put
Pet aut in vdd
NFET
End
The st ine declasu a pat called inv
inv followed by
input lhere `in' ) The eutput Caut) a lhist of
the aymbel -’ appeas on the othesido f
Follewng thie
connetiony Tho
s a ist e taauistos
w'th thein bype k4
ldain= out, gte = atatemt descubes an n- taans Cs tor uth
* The 2nol toctement Vss/
duc
Jdaain p-transsto wuth
/sttual. dRptien
vddy
2-iput NAND VD
Pat nd2(a, b)’ out
i1
a
D
act a

N7t
Pt ut
Ves

Vdd
atil
b
Pfat 9t Vdd
Bnd
iateeediat sgaal i1 s ceclaed 8chg Keyuod graly
 * stRuctual des aiptian o 2-in put AND gado neth capatane
and tan'ste szng
VDD

Part nand2 (a, b) ’ ot -dL2 2I b

N7t i4 a VsS - out

Nyet ut b

P7t vdd sze =2

50

Pyt ot Vdd sCze-2

S0
Capaewtanco a
capaeitata 100
Capacitanio cut 200
Brd

btuetusal de cuptien o taam'scon

t Con gate nMODEL
çb
Paut TG (a, c) cb)->b
d IP s
Net a Cb
Phet a ch b
End
4 sthuctual decwptiono p - o p CD-Lateh)
Paxt fipHlop (in, dd, dba, 4, qba)
Bignal o
qbay
TG Cin, id, id ba)’a
iny Ca) ’. qba
inv 'Cq ba)> q
TG Ca,ldbas, ld)’Q
End
Phyial aepacteutation
* The phycal apeecat on fo
a cau't i sed to delene how tly
pauti cular pat has to be orututed lo yield a peeutc stucuy
avd bharie

A bypical phy cat epntabon fon a traitoe woulol oist

kwo Aectangles ( difuson and poyeiton ) ovealapped to
fabicate tihe tan'tot.
Desgn ules 4peety the 'i each
wctange
The bacc Mos Lae
) n- dilhuac'on
2) p- dißbuscan
3) metal

4) Pely olicon
A tans'ste is femud utian dufucon and polyacliton ouetlap
Phycvcal 4ypmbot o nMOs

~polys

ndi

’
n-dill
Phyrcal ymbol o pmos
Phyical derwption f a CMOS inveale
metaf

FApoys
p-tans's te,
|Dot
J ut

| n-tunss to
VSS
t T r r u D vss
Smetal

Phyieal decuiption of traumsion gate peys

cbas ptransrse,

1eut metl

Dut

n- transi's ha

polysi
Phyaas Laye inteuacti on -a

P-daf poy si metalCAL)

n-dff Taaniiatr

X Trans¯stor Ok (c)
Poysi Thanssto eanusto
oK(c) OK(c)
 CMOS nMOS

logic levelo Fully uteed k

Von

Rize and fall tin ae a ¥ Ri'se tana iu sloues than all tine
* Pouuer i'spatin
Amort 'o static pousu discate
Powe à diepated duwhg tiauie eutput o a yate = 0 along uu th
pouuer dpated d g teansin
* Packingdauucty
Reo'es 2N tans'stouy
N hput CMOS gats
* Pouw suppy
Voltag eaned to &uuth a Dependut
gate
A Pu- p to pull-doen catio
Rati'o obypcally /:|o 2:
Layoudt
Kagula dagut Depletin load and ditferet
tuansista sizes des not uppat
layeut agiauiy
}*Pawtu'ste passes stog O,
Paue eth <bnong o Ashog) Value
degradad