Module 3- CMOS Process Technology & Circuit characterization VLSI Design & Testing (BEC602)

Module 3a: CMOS Process Technology

CMOS Process Technology: Silicon Semiconductor Technology, CMOS Technologies, Layout
Design Rules

1. Silicon Semiconductor Technology

1.1 INTRODUCTION

➢ Silicon, in its pure (intrinsic) state, is a semiconductor with an electrical resistance that
lies between that of a conductor and an insulator. Unlike metals, whose conductivity is
primarily due to free electrons, silicon’s electrical properties can be significantly modified
by introducing impurities into its crystal lattice.
➢ The process of adding impurity atoms to silicon to alter its conductivity is called doping.
The introduced atoms, known as dopants, can either donate free electrons or create
electron vacancies (holes)
➢ Certain impurity elements accept electrons from the silicon lattice, creating holes as the
majority charge carriers. These dopants are called acceptors, and common examples
include boron (B) and gallium (Ga).
➢ Other impurity elements contribute free electrons to the silicon lattice, making electrons
the majority charge carriers. These dopants are called donors, with common examples
being phosphorus (P) and arsenic (As).
➢ When n-type and p-type silicon materials are brought together, a transition region known
as a PN junction is formed. This junction plays a crucial role in semiconductor devices.
➢ By arranging multiple PN junctions in specific physical structures, various
semiconductor devices such as diodes, transistors, and integrated circuits (ICs) can be
designed.
➢ Semiconductor fabrication has evolved significantly, allowing precise control over
junction properties, leading to highly efficient and miniaturized electronic components.

1.2 WAFER PROCESSING

➢ Semiconductor manufacturing begins with silicon wafers, thin disks of single-crystal

silicon, typically 75 mm to 150 mm in diameter and less than 1 mm thick. These
wafers are cut from ingots grown using the Czochralski method, the most common
technique for producing high-purity silicon.

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Module 3- CMOS Process Technology & Circuit characterization VLSI Design & Testing (BEC602)

➢ CZOCHRALSKI METHOD

Figure 1: Czochralski process for manufacturing silicon ingots

➢ High-purity polycrystalline silicon is melted in a quartz crucible, surrounded by a

graphite radiator, and heated using radio frequency induction.
➢ The temperature is maintained slightly above 1425o C, with an inert gas (helium or
argon) preventing contamination.
➢ A seed crystal is dipped into the melt and slowly withdrawn while rotating. The molten
silicon solidifies, maintaining the single-crystal structure of the seed. The ingot diameter
is controlled by the withdrawal rate and rotation speed, with growth rates ranging from
30 mm/hour to 180 mm/hour.

Wafer Slicing and Polishing

➢ The grown ingot is sliced into wafers using diamond-tipped blades, with thicknesses
between 0.25 mm and 1.0 mm, depending on diameter. At least one face is polished to
a mirror finish to remove surface irregularities and ensure a defect-free surface for
semiconductor fabrication.

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Module 3- CMOS Process Technology & Circuit characterization VLSI Design & Testing (BEC602)

1.3 OXIDATION

➢ Silicon dioxide (SiO2) plays a crucial role in the fabrication of silicon integrated circuits.
Many manufacturing techniques depend on its insulating and passivating properties,
making reliable SiO2 formation essential.
➢ Silicon oxidation is achieved by heating silicon wafers in an oxidizing atmosphere, such
as oxygen or water vapor. The process consumes silicon and results in an SiO2 layer
that expands in both vertical directions.

The two common oxidation methods are:

1. Wet Oxidation:
• Uses an oxidizing atmosphere containing water vapor.
• Operates at 900 ◦C to 1000 ◦C.
• Provides a faster oxidation rate.
2. Dry Oxidation:
• Uses pure oxygen as the oxidizing agent.
• Requires higher temperatures (1200 ◦C) for acceptable growth rates.
• Produces a denser and higher-quality oxide layer.

➢ Since SiO2 has roughly twice the volume of the consumed silicon, the oxide layer grows
almost equally above and below the original silicon surface. This effect is illustrated in
n-channel MOS devices, where the field oxide projects in both directions.

Figure 2: An nMOS transistor showing the growth of field oxide in both vertical directions

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 Module 3- CMOS Process Technology & Circuit characterization VLSI Design & Testing (BEC602)

1.4 SELECTIVE DIFFUSION

➢ Selective diffusion is a process used to introduce controlled amounts of donor or acceptor

impurities into specific areas of a silicon wafer. The ability of silicon dioxide (SiO 2) to act
as a diffusion barrier allows precise patterning of doped regions.

Selective diffusion involves the following steps:

• Opening windows in an SiO2 layer grown on the wafer surface.

• Removing SiO2 selectively using a suitable etching technique.
• Exposing the silicon to a controlled dopant source to alter its electrical properties.

➢ The removal of SiO2 is achieved using a process called photolithography, which involves:
• Coating the wafer with a photosensitive resist (PR).
• Exposing PR to ultraviolet (UV) light through a patterned mask.
• Developing the PR to remove unpolymerized areas.
• Etching away the exposed SiO2, allowing selective diffusion of dopants.
➢ Conventional UV-based lithography limits feature sizes to about 1.5m to 2m due to
diffraction effects.

Figure 3: Simplified steps involved in the patterning of Si02

➢ Electron beam lithography (EBL) has emerged as a more precise technique, achieving line
widths of approximately 0.5 m. Key advantages of EBL include:
• Direct patterning from digital data without masks.
• High flexibility, allowing different patterns in different wafer regions.
• Quick modifications to design layouts.

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Module 3- CMOS Process Technology & Circuit characterization VLSI Design & Testing (BEC602)

1.5 The Silicon Gate Process

➢ In addition to single-crystal silicon and silicon dioxide (SiO2), polysilicon (polycrystalline
silicon) plays a crucial role in semiconductor fabrication. It is used as an interconnect
in integrated circuits and as the gate electrode in MOS transistors.
➢ The self-aligned nature of polysilicon gates enables precise definition of source and drain
regions, improving circuit performance.
➢ Steps in the Silicon Gate Process
The silicon gate process involves multiple cycles of photomasking and oxide etching,
as illustrated in figure below.

Figure 4: Fabrication steps for a silicon gate nMOS transistor

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Module 3- CMOS Process Technology & Circuit characterization VLSI Design & Testing (BEC602)
➢ Step 1: Field Oxide Formation
A thick layer of SiO2 (field oxide) is grown over the wafer surface. This oxide is selectively
etched in areas where transistors will be placed.

➢ Step 2: Gate Oxide Growth

A thin, controlled layer of SiO2, called the gate oxide, is grown on the exposed silicon
surface. This serves as the insulating layer beneath the polysilicon gate.

➢ Step 3: Polysilicon Deposition

A layer of undoped polysilicon is deposited across the wafer. This layer is later etched
to form transistor gates and interconnections.

➢ Step 4: Dopant Diffusion

The wafer is exposed to a dopant source, leading to: Formation of source and drain
junctions in the silicon substrate. Doping of polysilicon, reducing its resistivity.
The polysilicon gate acts as a mask, ensuring that the source and drain regions do not
extend beneath it. This self-aligned process enhances device performance.

➢ Step 5: Final Processing

The structure is covered with an SiO2 layer. Contact holes are etched for electrical
connections. A metallic layer (e.g., aluminum) is deposited and etched to complete the
circuit.

2. CMOS TECHNOLOGIES

2.1 The p-well process

➢ CMOS (Complementary Metal-Oxide-Semiconductor) technology is a fundamental
building block in modern VLSI (Very Large-Scale Integration) circuits. Among the various
CMOS fabrication techniques, the p-well process is a widely used method.
➢ In this approach, a moderately doped n-type substrate (wafer) is used as the starting
material.
➢ A p-type well is created in this substrate to accommodate the n-channel MOS
transistors, while the native n-type substrate is used for fabricating p-channel MOS
transistors.
➢ This process allows for the integration of both n-channel and p-channel transistors on
the same wafer, enabling complementary circuit operation.
➢ The fabrication of CMOS devices involves multiple steps, including photolithography,
diffusion, ion implantation, oxidation, and metallization.

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Module 3- CMOS Process Technology & Circuit characterization VLSI Design & Testing (BEC602)
Step 1: P-Well Formation
➢ The first step involves defining the p-well region using a photolithographic mask.
The field oxide (FOX) is etched away in the designated p-well regions. A deep diffusion or
ion implantation process introduces p-type dopants (typically boron) into the n-type
substrate. The depth and concentration of the p-well must be carefully controlled, as they
influence the threshold voltage and breakdown voltage of the nMOS transistors.

Figure 5: P-Well Formation

Step 2: Thin Oxide Growth

➢ A thin, high-quality silicon dioxide (SiO2) layer is thermally grown on the exposed silicon
surface. This oxide layer acts as the gate insulator for MOS transistors.
The thickness of this layer is crucial for transistor performance and determines the gate
capacitance.

Figure 6: Thin Oxide Growth

Step 3: Polysilicon Gate Formation

➢ A layer of polycrystalline silicon (polysilicon) is deposited over the entire wafer. This
layer serves as the gate electrode for MOS transistors. Using photolithography and
etching, the polysilicon is patterned to define transistor gates and interconnections.

Figure 7: Polysilicon Gate Formation

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Step 4: Source and Drain Implantation

➢ A p-plus (p+) mask is used to define regions where p-type dopants will be implanted. In
the absence of the p+ mask, the remaining thin oxide areas are doped with n-type
impurities, forming n+ regions. These diffusion regions serve as the source and drain
terminals for nMOS and pMOS transistors.
➢ The polysilicon gate acts as a mask, ensuring precise alignment of source and drain
regions, which is known as the self-aligned process.

Figure 8: Source and Drain Implantation

Step 5: Oxide Deposition and Contact Formation

➢ A thick insulating layer of silicon dioxide (SiO2) is deposited over the entire wafer.
Photolithography is used to etch contact holes in the oxide layer, exposing selected diffusion
and polysilicon regions.

Figure 9: Oxide Deposition and Contact Formation

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Module 3- CMOS Process Technology & Circuit characterization VLSI Design & Testing (BEC602)
Step 6: Metallization

➢ A thin layer of aluminum or another conductive metal is deposited over the wafer. The
metal layer is patterned and etched to form interconnections between various circuit
elements.

Figure 10: Metallization

Step 7: Passivation and Final Processing

➢ A protective passivation layer (such as silicon nitride) is deposited to shield the circuit
from contamination and environmental damage. Openings are etched to allow external
connections to bonding pads.

2.2 The Twin-Tub Process

➢ CMOS technology has evolved through various fabrication techniques to improve

performance and design flexibility. One such advancement is the Twin-Well or Twin-
Tub CMOS Process, which enables independent optimization of both p-type and n-type
transistors.
➢ This process allows the threshold voltage, body effect, and gain associated with n-channel
and p-channel transistors to be individually optimized, leading to improved circuit
performance.
➢ The Twin-Tub process offers several advantages over the conventional p-well process:
• Independent Optimization: The twin-tub approach allows separate control of p-
well and n-well properties, leading to better transistor performance.
• Threshold Voltage Control: The use of separate wells makes it possible to fine-tune
the threshold voltages of both p-type and n-type MOSFETs.
• Improved Body Effect and Gain: The body effect, which influences the threshold
voltage, can be optimized separately for nMOS and pMOS transistors.
• Reduced Latch-up Susceptibility: The process starts with an epitaxial silicon layer
to enhance latch-up immunity by isolating the wells from the substrate.

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 Module 3- CMOS Process Technology & Circuit characterization VLSI Design & Testing (BEC602)
➢ The fabrication sequence of the Twin-Tub CMOS process is similar to the p-well process,
with the key difference being that both p-well and n-well regions are formed independently
to achieve the desired electrical properties.

The key steps are as follows:

1. Substrate Preparation:
A lightly doped silicon wafer (typically p-type) is used as the starting material. A thin oxide
layer is grown to serve as a protective layer. An epitaxial silicon layer is deposited to improve
performance and minimize latch-up issues.
2. Twin-Tub Formation:
Both p-well and n-well are created by selective ion implantation. The process allows
separate optimization of the electrical properties of p-channel and n-channel MOSFETs.
3. Threshold Voltage Adjustment:
A threshold adjustment implant is introduced to control the transistor threshold voltages.
4. Field Oxidation and Isolation:
Field oxide is grown to isolate different transistor regions. LOCOS (Local Oxidation of
Silicon) may be used to create field oxide regions.
5. Polysilicon Deposition and Gate Formation:
A thin gate oxide layer is thermally grown. Polysilicon is deposited and patterned to form
the gate electrode.
6. Source and Drain Implantation:
Arsenic (n-type) is implanted into the p-well to form nMOS source and drain. Boron (p-
type) is implanted into the n-well to form pMOS source and drain.
7. Contact Cut Definition:
Openings are etched to allow metal contacts to connect to the source, drain, and gate
terminals.
8. Metallization:
Metal layers (usually aluminum) are deposited and patterned to create interconnections. A
passivation layer is deposited for protection.

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Module 3- CMOS Process Technology & Circuit characterization VLSI Design & Testing (BEC602)
MASK 1 (WELL
DEFINITION)

(WELL FORMATION)

MASK 2 (THINOX
DEFINITION)

MASK 3

MASK 4 (POLYSILICON
PATTERNING)

MASK 5

MASK 6

MASK 7

MASK 8

Figure 11: AT&T Bell Laboratories’ twin-tub CMOS process steps

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Module 3- CMOS Process Technology & Circuit characterization VLSI Design & Testing (BEC602)

3. LAYOUT DESIGN RULES

➢ Layout design rules, also known as design rules, serve as guidelines for preparing the
photomasks used in the fabrication of integrated circuits (ICs).
➢ These rules act as a critical communication bridge between the circuit designer and the
process engineer, ensuring that the manufacturing process is both efficient and reliable.
➢ The primary objective of layout design rules is to achieve the highest possible yield
while maintaining a compact geometry without compromising circuit reliability. A trade-
off exists:
– Conservative rules ⇒ Higher reliability but may limit performance.
– Aggressive rules ⇒ Potential performance gains but may reduce fabrication yield.

Purpose of Design Rules

➢ Design rules define geometric constraints for layout , ensuring that the processed wafer
maintains the intended topology and geometry of the design. It is important to note:
Design rules do not represent a strict boundary between correct and incorrect
fabrication.
➢ A layout that violates some design rules may still function, but frequent violations
increase the risk of fabrication failures.
➢ Two critical aspects of design rules include:
1. Line Widths:
Too narrow: May cause discontinuities, leading to circuit failure.
Too close: Can result in short circuits between adjacent conductive paths.
2. Interlayer Registration:
Ensures proper alignment between different material layers in the fabrication
process. Incorrect spacing between layers can cause electrical and manufacturing
defects.

Types of Design Rules

Several approaches exist for defining design rules:

1. Micron-Based Rules:
Specifies minimum feature sizes and spacings in absolute micron values (e.g.,
minimum thinox width = 4 µm). Commonly used in industrial fabrication processes.
2. Alpha (α) and Beta (β) Rules:
Uses β as a reference for feature sizes and α as the minimum required grid spacing.
These parameters are related by a constant factor.

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Module 3- CMOS Process Technology & Circuit characterization VLSI Design & Testing (BEC602)
3. Lambda (λ)-Based Rules:
Introduced by Mead and Conway, lambda-based rules use a single parameter (λ) to
define all feature sizes. Enables scaling of circuit layouts across different technology
nodes. Allows rules to be expressed compactly, often on a single page.
However, λ-based scaling is only an approximation and may not be suitable for
commercial circuits.

Derivation of Lambda-Based Rules

A representative example of how lambda (λ)-based rules are derived from micron-based
rules is shown in table below.

Mask Feature Micron Rule (µm) Lambda Rule (λ)

Thinox Minimum thinox width 4µm 2λ

Minimum thinox spacing 4µm 2λ
Minimum p-thinox to n-thinox 8µm 4λ
spacing
Polysilicon Minimum poly width 3.75µm 2λ
Minimum poly spacing 3.75µm 2λ
Minimum gate poly width (p) 4.5µm 3λ
Minimum gate poly width (n) 4µm 2λ
Minimum gate poly extension 3.5µm 2λ
Aluminum Minimum Al width 4.5µm 3λ
Minimum Al spacing 4.5µm 3λ

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Module 3- CMOS Process Technology & Circuit characterization VLSI Design & Testing (BEC602)

Module 3b: CMOS Process Technology

Circuit Characterization and Performance Estimation: Introduction, Resistance
Estimation, Capacitance Estimation, Switching Characteristics, CMOS gate transistor
sizing, Determination of conductor size, Power consumption, Charge sharing, Scaling of
MOS transistor sizing, Yield.

1. INTRODUCTION
➢ An MOS structure is created by superimposing multiple layers of conducting, insulating,
and transistor-forming materials.
➢ A conventional silicon gate MOS device consists of a gate-forming region and a
source/drain-forming region, which includes diffusion, polysilicon, and metal layers
separated by insulating layers.
➢ Each of these layers exhibits resistance and capacitance, which are fundamental in
determining the performance of a circuit or system.
➢ While these layers also have inductive characteristics, for simplicity, we assume their
effects to be negligible. The key focus is on developing simple models to analyze system
behavior and estimate key performance metrics such as signal delays and power
dissipation.
➢ These models help in understanding the design and optimization of MOS circuits.
The key areas to be considered are
1. Resistance and Capacitance Calculations :Each layer in an MOS structure has a
specific resistance and capacitance. These parameters impact signal integrity and circuit
speed.
2. Delay Estimations: Delays arise due to the resistance-capacitance (RC) time constant of
interconnects. Understanding delays is essential for high-speed circuit design.
3. Determination of Conductor Size for Power and Clock Distribution: Proper conductor
sizing ensures minimal power loss and maintains signal integrity. Efficient clock
distribution minimizes skew and ensures synchronization across the circuit.
4. Power Consumption: Includes both dynamic power and static power. Optimization is
necessary for energy-efficient circuit design.
5. Charge Storage Mechanism: MOS capacitors store charge, playing a crucial role in logic
transitions and memory operations.
6. Effects of Scaling: As MOS devices scale down, resistance, capacitance, and power
consumption change. Scaling impacts device performance and requires careful
consideration in design.

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Module 3- CMOS Process Technology & Circuit characterization VLSI Design & Testing (BEC602)

2. RESISTANCE ESTIMATION

Sheet Resistance

The resistance R of a uniform slab of conducting material is given by:

where:
ρ = resistivity of the material,
t = thickness of the conductor,
l = conductor length,
w = conductor width.
This equation can be rewritten using sheet resistance Rs (measured in ohms per square)
as:

➢ Thus, the resistance of a thin conducting layer can be calculated by multiplying the sheet
resistance, Rs by the length-to-width ratio of the conductor.
Consider the following figure 1:

Figure 1 : Determination of layer resistance

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 Module 3- CMOS Process Technology & Circuit characterization VLSI Design & Testing (BEC602)

2.1 Channel Resistance in MOS Transistors

➢ Although the voltage-current characteristics of an MOS transistor are nonlinear, an
approximate channel resistance can be used for performance estimation.
➢ The channel resistance Rc in the linear region is:

where

For both n-channel and p-channel MOSFETs, k typically ranges from 5,000 to 30,000
Ω/sq.

2.2 Resistance of Non-Rectangular Regions

➢ In VLSI layouts, conducting paths often take non-rectangular shapes, such as bends or
junctions. The resistance of such regions is more complex to calculate than for simple
rectangles.
➢ A common approach is to divide a complex shape into simpler rectangular sections and
calculate resistance accordingly. Figure 2 below presents standard resistance values for
commonly encountered VLSI layout shapes.

Figure 2: Resistance of commonly encountered shapes.

➢ These values serve as useful approximations when designing complex circuits. Figure
below illustrates practical layout geometries encountered in integrated circuit design.

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Module 3- CMOS Process Technology & Circuit characterization VLSI Design & Testing (BEC602)

Figure 3: Examples of non-rectangular layout shapes in practical VLSI designs.

➢ These shapes often require careful estimation of resistance due to their irregular
dimensions. These values can also be used to estimate the effective W/L ratio for irregular
MOS transistors.

3 CAPACITANCE ESTIMATION
➢ The dynamic response of MOS systems, particularly the switching speed, is significantly
influenced by the parasitic capacitances associated with MOS devices and
interconnections.
➢ These capacitances arise from metal, polysilicon, and diffusion wires (often referred to as
“runners”) in combination with transistor and conductor resistances. The total load
capacitance at the output of an MOS gate consists of the following components:

1. Gate Capacitance: Due to other inputs connected to the output of the gate.
2. Diffusion Capacitance: Arises from the drain regions connected to the output.
3. Routing Capacitance: Results from the connections between the output and other
inputs.
➢ Understanding the sources and variations of these parasitic loads is crucial in MOS
circuit design, where system performance is largely dictated by switching speed.

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Module 3- CMOS Process Technology & Circuit characterization VLSI Design & Testing (BEC602)

3.1 MOS Capacitor Characteristics

➢ The capacitance-voltage characteristics of an MOS structure depend on the state of the
semiconductor surface. As the gate voltage (VG) varies, the surface can be in one of the
following three states:
1. Accumulation
2. Depletion
3. Inversion
➢ Figure 4 below illustrates the MOS structure.

Figure 4: MOS capacitor structure

Accumulation Mode
➢ In a p-substrate MOS capacitor, an accumulation layer forms when VG < 0 (for an n-
substrate, this occurs when VG > 0). . The negative charge on the gate attracts holes to
the silicon surface, forming a high concentration of charge carriers.
➢ Under these conditions, the MOS structure behaves like a parallel plate capacitor, where:
– The gate conductor forms one [Link] accumulated hole layer in the p-substrate (or
electron layer in an n-substrate) forms the second plate.
➢ Since the accumulation layer is directly connected to the substrate, the gate capacitance
can be approximated as: C0 = εSio2 ε0 A
tox
where: A = area of the gate
ϵSiO2 = 3.9, the relative permittivity of ϵSiO2
Depletion Mode
➢ When a small positive voltage is applied to an n-device gate with respect to the p-
substrate, a depletion layer forms. The positive gate voltage repels holes, leaving behind
a negatively charged region depleted of carriers.
➢ A similar effect occurs in an n-substrate device for a small negative gate voltage. The
charge density per unit area in the depletion region depends on:

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Module 3- CMOS Process Technology & Circuit characterization VLSI Design & Testing (BEC602)
– Doping concentration (N)
– Electronic charge (q)
– Depletion layer depth (d)
➢ As the gate-to-substrate voltage increases, the depletion depth (d) also increases, causing
a decrease in capacitance. The depletion capacitance is given by:
Cdep = ε0 εSi A
d
where: d = depletion layer depth ϵSi = dielectric constant of Si taken as 12
➢ Since the depletion capacitance is in series with the gate oxide capacitance, the total
capacitance in depletion mode is:

➢ This equation shows that as d increases, the total gate-to-substrate capacitance

decreases.
Inversion Mode
➢ As the gate voltage increases further, minority carriers (electrons for a p-substrate)
accumulate at the surface, forming an inversion layer that effectively turns the surface
into an n-type channel.
➢ This results in a high-conductivity layer under the gate. At low frequencies (< 100 Hz),
the capacitance returns to Co. At higher frequencies, the limited supply of minority
carriers prevents the charge from following rapid gate voltage variations.
➢ Consequently, the dynamic capacitance remains at the depletion value, given by:

➢ Figure5 below illustrates the variation of dynamic gate capacitance as a function of gate
voltage.

Figure 5: MOS capacitance variation as a function of Vgs

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Module 3- CMOS Process Technology & Circuit characterization VLSI Design & Testing (BEC602)

3.2 MOS Device Capacitances

➢ In practical MOS transistors, several parasitic capacitances exist due to the physical
structure of the device. Figure 6 below presents a diagrammatic representation of these
parasitic capacitances.
➢ For simplicity, we assume that the overlap of the gate over the drain and source is
negligible. This is a valid first-order approximation in self-aligned silicon gate processes.

Figure 6: Representation of parasitic capacitance for an MOS transistor

The following capacitances are identified:

➢ Cgs and Cgd: Gate-to-channel capacitances, which are lumped at the source and
drain regions of the channel.
➢ Csb and Cdb: Source and drain diffusion capacitances to the bulk (or substrate)
➢ Cgb: Gate-to-bulk capacitance.
➢ It is possible to represent this model using circuit symbols, as shown in figure below.

Figure 7: Circuit symbols for parasitic capacitance

➢ The total gate capacitance (Cg) of an MOS transistor is given by:

Cg = Cgb + Cgs + Cgd
➢ The behavior of the gate capacitance depends on the region of operation of the MOS
transistor. The capacitance values can be approximated using simple models in each
region:

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Module 3- CMOS Process Technology & Circuit characterization VLSI Design & Testing (BEC602)
1. Off Region (VGS < Vt):
➢ When the MOS transistor is “OFF”, there is no conducting channel, meaning
Cgs = Cgd = 0.
➢ The gate-to-bulk capacitance (Cgb) can be modeled as the series combination of the gate
oxide capacitance (Co) and the depletion capacitance (Cdep), as discussed earlier.
2. Linear Region (VGS > Vt, VDS < VGS − Vt):
➢ In this region, the depletion layer depth remains relatively constant. Consequently, Cgb
remains constant.
➢ As a conducting channel forms, the gate-to-channel capacitances Cgs and Cgd become
significant.
➢ These capacitances depend on the gate voltage and can be estimated as:

3. Saturation Region (VGS > Vt, VDS > VGS − Vt):

➢ In this region, the channel is heavily inverted, and the drain end of the channel is
pinched off. This causes Cgd to be approximately zero, while Cgs increases to:

➢ The behavior of the input capacitances in the three regions of operation is summarized
in table below

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Module 3- CMOS Process Technology & Circuit characterization VLSI Design & Testing (BEC602)

3.3 Diffusion Capacitance

➢ In MOSFETs, the source and drain regions are formed by shallow n+ and p+ diffusions.
These diffusion regions also act as interconnects in some layouts.
➢ All diffusion regions have capacitance to the substrate (or well), known as diffusion
capacitance (Cd). Cd arises due to the reverse-biased junction between diffusion and
substrate. It depends on:
– Voltage across the junction (Vj)
– Area of the depletion region:
* Base area (horizontal)
* Sidewall area (vertical, due to diffusion depth)
Capacitance Model
Let:
• Cja = Capacitance per unit area (pF/μm2)
• Cjp = Capacitance per unit periphery (pF/μm)
• a = Width of diffusion region (μm)
• b = Length of diffusion region (μm)
Then the total diffusion capacitance is: Cd = Cja(ab) + Cjp(2a + 2b)

Figure 8: Area and peripheral components of diffusion capacitance

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Module 3- CMOS Process Technology & Circuit characterization VLSI Design & Testing (BEC602)

3.4 Routing Capacitance

➢ Routing capacitance arises between interconnect layers (e.g., metal, poly) and the
substrate or other layers. It is crucial in estimating interconnect delay and dynamic power
consumption. Capacitance between layers can be estimated using the parallel-plate
capacitor model where:
C = Capacitance (F)
ε = Dielectric constant of the insulating material
A = Overlapping area of the plates
t = Thickness of the dielectric (insulator)
➢ The parallel-plate model ignores fringing fields. Fringing fields increase the effective area
and hence increase the capacitance. Actual capacitance can be up to twice than
predicted.
➢ Interlayer capacitance (e.g., metal-to-poly) is also enhanced by fringing effects.

Figure 9: Effect of fringing fields on capacitance

➢ With technology scaling, wire widths (w) and heights reduce less than separations (l).
➢ Thus, fringing fields become more prominent in deep submicron technologies. A fringing
factor between 1.5 and 3 is typically used in modern processes.
➢ Another source of error in capacitance estimation arises from differences between the
drawn layout (on mask) and the actual fabricated geometry. This is particularly
pronounced for diffusion regions.
.

Figure 10: Effect of processing on drawn geometry

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4. Switching Characteristics
➢ The switching speed of a CMOS gate is limited primarily by the time it takes to charge
and discharge the load capacitance CL.
➢ When an input transition occurs, the output undergoes a corresponding transition —
either charging CL toward VDD or discharging it toward VSS.

Figure 10: Switching characteristic for CMOS Inverter

➢ Figure 10 (a) shows a standard CMOS inverter driving a capacitive load C L. This
capacitance models:
• The input capacitance of subsequent stages
• The output capacitance of the driving gate
• The routing (interconnect) capacitance
➢ The voltage response Vo(t) of the output node is of primary interest when the input Vin(t)
is a step waveform, as shown in figure (b). The analysis of Vo(t) under such conditions
allows us to estimate the inverter’s delay and transition behavior in practical digital
circuits.

• Rise time (tr): Time for a voltage waveform to rise from 10% to 90% of its final steady-
state value.
• Fall time (tf ): Time for a voltage waveform to fall from 90% to 10% of its steady-state
value.
• Delay time (td): Time difference between the 50% transition level of the input and the
corresponding 50% level of the output. This represents the time for the logic transition to
propagate through the gate.

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Module 3- CMOS Process Technology & Circuit characterization VLSI Design & Testing (BEC602)

4.1 Fall time determination

Figure 11: Equivalent circuits for fall time determination

The total fall time is given by: tf = tf1 + tf2 where:
. tf1 is the time during which VO drops from 0.9VDD to VDD − Vtn (saturation region),
. tf2 is the time during which VO drops from VDD − Vtn to 0.1VDD (linear region).

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Module 3- CMOS Process Technology & Circuit characterization VLSI Design & Testing (BEC602)

4.2 Rise Time Determination

Figure 12: Equivalent circuits for rise time determination

➢ When the input to a CMOS inverter goes from high to low, the pMOS turns ON and the nMOS
turns OFF. The output voltage rises from 0 to VDD through the pMOS, charging the load
capacitor CL.
➢ Rise time can be divided into two regions tr = tr1 + tr2 ,where:
• tr1: VO rises from 0.1VDD to VDD − |Vtp| (pMOS in saturation),
• tr2: VO rises from VDD − |Vtp| to 0.9VDD (pMOS in linear).

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Module 3- CMOS Process Technology & Circuit characterization VLSI Design & Testing (BEC602)

4.3 Delay Time

➢ In a CMOS digital circuit, the gate delay is the time taken by the output to respond to a
change in input. This delay is mainly dominated by the time it takes to charge or discharge
the output load capacitor CL, which corresponds to the rise time (tr) and fall time (tf ),
respectively. Rising and Falling Propagation Delays
➢ The propagation delay during a rising transition is defined as:
➢ This corresponds to the average time taken for the output voltage to transition from low to
high (e.g., from 0.1VDD to 0.9VDD), typically measured at the 50% point of the output voltage
swing.
➢ Similarly, the propagation delay during a falling transition is:

➢ Average Gate Delay, τav is the average of the rising and falling propagation delays:

➢ This quantity τav is widely used in delay modeling of CMOS gates in digital circuit design.

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Module 3- CMOS Process Technology & Circuit characterization VLSI Design & Testing (BEC602)

5. Power Consumption
➢ In CMOS circuits, the total power dissipation arises from two primary components:
1. Static dissipation — due to leakage current
2. Dynamic dissipation — due to:

• Switching transient currents

• Charging and discharging of load capacitances

1. Static Dissipation
➢ Consider a complementary CMOS gate as shown in figure below:

Figure 13: CMOS inverter states for static dissipation calculations

➢ When the input is at logic ‘0’, the nMOS is OFF and the pMOS is ON, pulling the output
to VDD.
➢ When the input is logic ‘1’, the nMOS is ON and the pMOS is OFF, pulling the output to
ground (VSS).
➢ In both states, one transistor is OFF, and there is no direct current path from VDD to VSS.
➢ Hence, under ideal conditions, the quiescent current and power dissipation are
[Link], there exists a small leakage current due to reverse-biased junctions
between the diffusion regions and the substrate. A model illustrating these parasitic
diodes in a CMOS inverter is shown in figure below:

Figure 14: Model describing parasitic diodes

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Module 3- CMOS Process Technology & Circuit characterization VLSI Design & Testing (BEC602)
➢ The diode D1 models leakage from the p-well to substrate. . The reverse-biased leakage
current is modeled by the diode equation:

where:
– is = reverse saturation current
– V = voltage across the diode
– q = electronic charge
– k = Boltzmann’s constant
– T = temperature (in Kelvin)
➢ The static power dissipation is given by:
where n = number of devices

2. Dynamic Dissipation
➢ When the output switches states (either from ‘0’ to ‘1’ or ‘1’ to ‘0’), both nMOS and pMOS
devices conduct for a brief interval.
➢ This causes a short-duration current pulse from VDD to VSS.
➢ Additionally, current is drawn to charge
and discharge the load capacitance,
which is typically the dominant
component of dynamic power.
➢ This short-circuit power dissipation is
important in I/O buffer design and is
influenced by gate design and
capacitance.
➢ Assuming a step input with rise/fall
times much smaller than the repetition
period, the average dynamic power
dissipation for a square-wave input with
frequency fp = 1/tp (as shown in figure
aside) is:
Pd = CLVDD2fp
where:
– CL = load capacitance Figure 15: Waveforms for determination of dynamic power dissipation
– VDD = supply voltage
– fp = switching frequency
➢ This equation shows that dynamic power is proportional to both the capacitance and the
square of the supply voltage, and it increases linearly with frequency. It is independent of
transistor parameters.
Total Power Dissipation
The total power consumed by a CMOS circuit is the sum of the static and dynamic components:

Ptotal = Ps + Pd

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Module 3- CMOS Process Technology & Circuit characterization VLSI Design & Testing (BEC602)

6. Charge Sharing
➢ In many digital CMOS circuits, especially during dynamic logic or bus operations, charge
sharing is a critical consideration for maintaining signal integrity.

Charge Sharing Model

➢ A bus can be modeled as a capacitor Cb, as

shown in figure aside.
➢ Often, a signal from this bus is sampled via a
switching element connected to another
capacitor Cs.
➢ This configuration can be analyzed by
modeling the pre- and post-switching charge
conditions.
Figure 16: Charge sharing mechanism
➢ Initial Conditions
Before the switch is closed: Qb = CbVb, Qs = CsVs
Total initial charge: QT = CbVb + CsVs
Total capacitance after switching: CT = Cb + Cs

➢ Final Voltage After Sharing

Once the switch closes, the charge redistributes, and both capacitors settle at a common
voltage VR:

➢ Case: Vs ≈ 0, Assuming Vb = VDD and Vs ≈ 0, the resulting voltage becomes:

➢ This shows that VR is reduced compared to VDD, and the amount of drop depends on the
ratio Cs/Cb.

7. Scaling of MOS Transistor Sizing

➢ As CMOS fabrication technology evolves, the dimensions of transistors are continually

reduced to improve performance and increase packing density.
➢ First-order MOS scaling theory assumes that the electric fields in the device are kept
constant as dimensions are reduced. If all critical parameters—such as device
dimensions (length L, width W, oxide thickness tox, and junction depth Xj), voltages (VDD),

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Module 3- CMOS Process Technology & Circuit characterization VLSI Design & Testing (BEC602)
and doping concentrations — are scaled by a factorα > 1, then the key electrical properties
of the device can still be preserved.
➢ The scaling is applied as follows:
– All horizontal and vertical dimensions are scaled by 1/α.
– Voltages are scaled by 1/α.
– Doping concentrations are scaled by α.
➢ This approach results in a new device that is physically smaller, uses lower voltage, but
maintains the same electric field intensities. The outcome of such scaling is illustrated in
figure and table shown below.

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 Module 3- CMOS Process Technology & Circuit characterization VLSI Design & Testing (BEC602)

8. Yield
➢ Yield is a critical factor in the manufacturing of VLSI (Very-Large-Scale Integration)
circuits. Although yield is not directly a performance parameter, it significantly affects
the economic feasibility of fabrication and is influenced by several factors:
– Technology used in fabrication
– Chip area
– Layout strategy
➢ Yield is defined as:

➢ Yield depends primarily on the chip area (A) and the defect density (D) (number of lethal
defects per cm2).
Two widely accepted models describe how yield relates to these parameters.

1. Seed’s Yield Model: This model is used primarily when:

• The chip area is large
• The yield is expected to be less than 30%
• The yield is expressed as: Y = e−√AD
where
A = chip area (in cm2)
D = defect density (lethal defects/cm2)
As chip area increases or defect density rises, the exponent becomes more negative,
causing yield to drop exponentially.

2. Murphy’s Yield Model: This model is preferred when:

• Chip area is relatively small
• Yield is expected to be greater than 30%
Murphy’s model gives:

➢ This formulation softens the drastic yield drop for small areas, making it more accurate
for high-yield conditions.

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