PIC16F913/914/916/917/946

Data Sheet
28/40/44/64-Pin Flash-Based,
8-Bit CMOS Microcontrollers with
LCD Driver and nanoWatt Technology

 2007 Microchip Technology Inc. DS41250F

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, Accuron,
and may be superseded by updates. It is your responsibility to dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC,
ensure that your application meets with your specifications. PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and
MICROCHIP MAKES NO REPRESENTATIONS OR SmartShunt are registered trademarks of Microchip
WARRANTIES OF ANY KIND WHETHER EXPRESS OR Technology Incorporated in the U.S.A. and other countries.
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, AmpLab, FilterLab, Linear Active Thermistor, Migratable
INCLUDING BUT NOT LIMITED TO ITS CONDITION, Memory, MXDEV, MXLAB, PS logo, SEEVAL, SmartSensor
QUALITY, PERFORMANCE, MERCHANTABILITY OR and The Embedded Control Solutions Company are
FITNESS FOR PURPOSE. Microchip disclaims all liability registered trademarks of Microchip Technology Incorporated
arising from this information and its use. Use of Microchip in the U.S.A.
devices in life support and/or safety applications is entirely at Analog-for-the-Digital Age, Application Maestro, CodeGuard,
the buyer’s risk, and the buyer agrees to defend, indemnify and dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,
hold harmless Microchip from any and all damages, claims, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
suits, or expenses resulting from such use. No licenses are In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,
conveyed, implicitly or otherwise, under any Microchip MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,
intellectual property rights. PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2007, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

DS41250F-page ii  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946
28/40/44/64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with
LCD Driver and nanoWatt Technology
High-Performance RISC CPU: Low-Power Features:
• Only 35 instructions to learn: • Standby Current:
- All single-cycle instructions except branches - <100 nA @ 2.0V, typical
• Operating speed: • Operating Current:
- DC – 20 MHz oscillator/clock input - 11 A @ 32 kHz, 2.0V, typical
- DC – 200 ns instruction cycle - 220 A @ 4 MHz, 2.0V, typical
• Program Memory Read (PMR) capability • Watchdog Timer Current:
• Interrupt capability - 1 A @ 2.0V, typical
• 8-level deep hardware stack
Peripheral Features:
• Direct, Indirect and Relative Addressing modes
• Liquid Crystal Display module:
Special Microcontroller Features: - Up to 60/96/168 pixel drive capability on
• Precision Internal Oscillator: 28/40/64-pin devices, respectively
- Factory calibrated to ±1%, typical - Four commons
- Software selectable frequency range of • Up to 24/35/53 I/O pins and 1 input-only pin:
8 MHz to 125 kHz - High-current source/sink for direct LED drive
- Software tunable - Interrupt-on-change pin
- Two-Speed Start-up mode - Individually programmable weak pull-ups
- External Oscillator fail detect for critical • In-Circuit Serial Programming™ (ICSP™) via two
applications pins
- Clock mode switching during operation for • Analog comparator module with:
power savings - Two analog comparators
• Software selectable 31 kHz internal oscillator - Programmable on-chip voltage reference
• Power-Saving Sleep mode (CVREF) module (% of VDD)
• Wide operating voltage range (2.0V-5.5V) - Comparator inputs and outputs externally
accessible
• Industrial and Extended temperature range
• A/D Converter:
• Power-on Reset (POR)
- 10-bit resolution and up to 8 channels
• Power-up Timer (PWRT) and Oscillator Start-up
• Timer0: 8-bit timer/counter with 8-bit
Timer (OST)
programmable prescaler
• Brown-out Reset (BOR) with software control
• Enhanced Timer1:
option
- 16-bit timer/counter with prescaler
• Enhanced Low-Current Watchdog Timer (WDT)
- External Timer1 Gate (count enable)
with on-chip oscillator (software selectable
- Option to use OSC1 and OSC2 as Timer1
nominal 268 seconds with full prescaler) with
oscillator if INTOSCIO or LP mode is
software enable
selected
• Multiplexed Master Clear with pull-up/input pin • Timer2: 8-bit timer/counter with 8-bit period
• Programmable code protection register, prescaler and postscaler
• High-Endurance Flash/EEPROM cell: • Addressable Universal Synchronous
- 100,000 write Flash endurance Asynchronous Receiver Transmitter (AUSART)
- 1,000,000 write EEPROM endurance • Up to 2 Capture, Compare, PWM modules:
- Flash/Data EEPROM retention: > 40 years - 16-bit Capture, max. resolution 12.5 ns
- 16-bit Compare, max. resolution 200 ns
- 10-bit PWM, max. frequency 20 kHz
• Synchronous Serial Port (SSP) with I2C™

 2007 Microchip Technology Inc. DS41250F-page 1

PIC16F913/914/916/917/946

Program
Data Memory LCD
Memory 10-bit A/D Timers
Device I/O (segment CCP
Flash SRAM EEPROM (ch) 8/16-bit
drivers)
(words/bytes) (bytes) (bytes)
PIC16F913 4K/7K 256 256 24 5 16(1) 1 2/1
PIC16F914 4K/7K 256 256 35 8 24 2 2/1
PIC16F916 8K/14K 352 256 24 5 16(1) 1 2/1
PIC16F917 8K/14K 352 256 35 8 24 2 2/1
PIC16F946 8K/14K 336 256 53 8 42 2 2/1
Note 1: COM3 and SEG15 share the same physical pin on the PIC16F913/916, therefore SEG15 is not available
when using 1/4 multiplex displays.

Pin Diagrams – PIC16F914/917, 40-Pin

40-pin PDIP

RE3/MCLR/VPP 1 40 RB7/ICSPDAT/ICDDAT/SEG13
RA0/AN0/C1-/SEG12 2 39 RB6/ICSPCLK/ICDCK/SEG14
RA1/AN1/C2-/SEG7 3 38 RB5/COM1
RA2/AN2/C2+/VREF-/COM2 4 37 RB4/COM0
RA3/AN3/C1+/VREF+/SEG15 5 36 RB3/SEG3
RA4/C1OUT/T0CKI/SEG4 6 35 RB2/SEG2
RA5/AN4/C2OUT/SS/SEG5 7 34 RB1/SEG1
RE0/AN5/SEG21 8 33 RB0/INT/SEG0
PIC16F914/917

RE1/AN6/SEG22 9 32 VDD
RE2/AN7/SEG23 10 31 VSS
VDD 11 30 RD7/SEG20
VSS 12 29 RD6/SEG19
RA7/OSC1/CLKIN/T1OSI 13 28 RD5/SEG18
RA6/OSC2/CLKOUT/T1OSO 14 27 RD4/SEG17
RC0/VLCD1 15 26 RC7/RX/DT/SDI/SDA/SEG8
RC1/VLCD2 16 25 RC6/TX/CK/SCK/SCL/SEG9
RC2/VLCD3 17 24 RC5/T1CKI/CCP1/SEG10
RC3/SEG6 18 23 RC4/T1G/SDO/SEG11
RD0/COM3 19 22 RD3/SEG16
RD1 20 21 RD2/CCP2

DS41250F-page 2  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946
1.0 DEVICE OVERVIEW
The PIC16F91X/946 devices are covered by this data
sheet. They are available in 28/40/44/64-pin packages.
Figure 1-1 shows a block diagram of the PIC16F913/916
device, Figure 1-2 shows a block diagram of the
PIC16F914/917 device, and Figure 1-3 shows a block
diagram of the PIC16F946 device. Table 1-1 shows the
pinout descriptions.

FIGURE 1-1: PIC16F913/916 BLOCK DIAGRAM

INT
Configuration
13 8
Data Bus PORTA
Program Counter RA0
Flash
RA1
4K/8K x 14 RA2
Program RAM RA3
8-Level Stack (13-bit)
Memory 256/352 bytes RA4
File
RA5
Registers
RA7
Program 14
Bus Program Memory Read RAM Addr
(PMR) 9 PORTB
Addr MUX RB0
Instruction Reg RB1
Direct Addr 7 Indirect RB2
8 Addr RB3
RB4
FSR Reg RB5
RB6
STATUS Reg RB7
8
PORTC
RC0
3 RC1
MUX
RC2
RC3
Instruction
Decode and RC4
Control ALU RC5
RC6
OSC1/CLKIN RC7
8
Timing
OSC2/CLKOUT Generation W Reg PORTE

Internal RE3/MCLR
Oscillator
Block

VDD VSS

Data EEPROM
256 bytes
Timer0 Timer1 Timer2 10-bit A/D

Addressable
Comparators CCP1 SSP PLVD LCD
USART

 2007 Microchip Technology Inc. DS41250F-page 15

PIC16F913/914/916/917/946
FIGURE 1-2: PIC16F914/917 BLOCK DIAGRAM
INT
Configuration
13 8
Data Bus PORTA
Program Counter RA0
Flash RA1
4K/8K x 14 RA2
Program RA3
RAM
8-Level Stack (13-bit) RA4
Memory 256/352 bytes
RA5
File
Registers RA6
RA7
Program 14
Bus Program Memory Read RAM Addr
(PMR) 9 PORTB
Addr MUX RB0
Instruction Reg RB1
Direct Addr 7 Indirect RB2
8 Addr RB3
RB4
FSR Reg RB5
RB6
STATUS Reg RB7
8
PORTC
RC0
3 RC1
MUX
Power-up RC2
Timer RC3
Instruction
RC4
Decode and Oscillator
Control Start-up Timer ALU RC5
RC6
OSC1/CLKIN Power-on RC7
8
Reset
Timing PORTD
OSC2/CLKOUT Generation Watchdog W Reg
Timer RD0
RD1
Brown-out
RD2
Reset
RD3
Internal
Oscillator RD4
Block RD5
RD6
VDD VSS RD7

PORTE
RE0
RE1
RE2
RE3/MCLR

Timer0 Timer1 Timer2 10-bit A/D Data EEPROM

256 bytes

Addressable
Comparators CCP1 CCP2 SSP PLVD LCD
USART

DS41250F-page 16  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946
FIGURE 1-3: PIC16F946 BLOCK DIAGRAM
INT
PORTA
Configuration RA0
13 8
Data Bus RA1
Program Counter RA2
Flash RA3
RA4
8K x 14
RA5
Program RAM RA6
8-Level Stack (13-bit)
Memory 336 x 8 bytes RA7
File
Registers PORTB
Program 14 RB0
Program Memory Read RAM Addr RB1
Bus
(PMR) 9 RB2
RB3
Addr MUX
Instruction Reg RB4
7 Indirect RB5
Direct Addr
8 Addr RB6
RB7
FSR Reg PORTC
RC0
8 STATUS Reg RC1
RC2
RC3
Power-up RC4
Timer 3 RC5
MUX
RC6
Oscillator RC7
Instruction Start-up Timer
Decode and PORTD
Control Power-on ALU RD0
Reset RD1
OSC1/CLKIN
Watchdog 8 RD2
Timing Timer RD3
OSC2/CLKOUT Generation W Reg RD4
Brown-out
RD5
Reset
RD6
RD7
Internal PORTE
Oscillator
Block VDD VSS RE0
RE1
RE2
RE3/MCLR
RE4
RE5
RE6
RE7
PORTF
RF0
RF1
RF2
RF3
RF4
RF5
RF6
RF7
PORTG

RG0
RG1
RG2
RG3
AVDD AVSS RG4
RG5

Data EEPROM
Timer0 Timer1 Timer2 10-bit A/D 256 bytes

Addressable
Comparators CCP1 CCP2 SSP PLVD LCD
USART

 2007 Microchip Technology Inc. DS41250F-page 17

PIC16F913/914/916/917/946
TABLE 1-1: PIC16F91X/946 PINOUT DESCRIPTIONS
Input Output
Name Function Description
Type Type
RA0/AN0/C1-/SEG12 RA0 TTL CMOS General purpose I/O.
AN0 AN — Analog input Channel 0.
C1- AN — Comparator 1 negative input.
SEG12 — AN LCD analog output.
RA1/AN1/C2-/SEG7 RA1 TTL CMOS General purpose I/O.
AN1 AN — Analog input Channel 1.
C2- AN — Comparator 2 negative input.
SEG7 — AN LCD analog output.
RA2/AN2/C2+/VREF-/COM2 RA2 TTL CMOS General purpose I/O.
AN2 AN — Analog input Channel 2.
C2+ AN — Comparator 2 positive input.
VREF- AN — External A/D Voltage Reference – negative.
COM2 — AN LCD analog output.
(1) RA3 TTL CMOS General purpose I/O.
RA3/AN3/C1+/VREF+/COM3 /
SEG15 AN3 AN — Analog input Channel 3.
C1+ AN — Comparator 1 positive input.
VREF+ AN — External A/D Voltage Reference – positive.
COM3(1) — AN LCD analog output.
SEG15 — AN LCD analog output.
RA4/C1OUT/T0CKI/SEG4 RA4 TTL CMOS General purpose I/O.
C1OUT — CMOS Comparator 1 output.
T0CKI ST — Timer0 clock input.
SEG4 — AN LCD analog output.
RA5/AN4/C2OUT/SS/SEG5 RA5 TTL CMOS General purpose I/O.
AN4 AN — Analog input Channel 4.
C2OUT — CMOS Comparator 2 output.
SS TTL — Slave select input.
SEG5 — AN LCD analog output.
RA6/OSC2/CLKOUT/T1OSO RA6 TTL CMOS General purpose I/O.
OSC2 — XTAL Crystal/Resonator.
CLKOUT — CMOS TOSC/4 reference clock.
T1OSO — XTAL Timer1 oscillator output.
RA7/OSC1/CLKIN/T1OSI RA7 TTL CMOS General purpose I/O.
OSC1 XTAL — Crystal/Resonator.
CLKIN ST — Clock input.
T1OSI XTAL — Timer1 oscillator input.
RB0/INT/SEG0 RB0 TTL CMOS General purpose I/O. Individually enabled pull-up.
INT ST — External interrupt pin.
SEG0 — AN LCD analog output.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels P = Power
HV = High Voltage XTAL = Crystal
Note 1: COM3 is available on RA3 for the PIC16F913/916 and on RD0 for the PIC16F914/917 and PIC16F946.
2: Pins available on PIC16F914/917 and PIC16F946 only.
3: Pins available on PIC16F946 only.
4: I2C Schmitt trigger inputs have special input levels.

DS41250F-page 18  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946
TABLE 1-1: PIC16F91X/946 PINOUT DESCRIPTIONS (CONTINUED)
Input Output
Name Function Description
Type Type
RB1/SEG1 RB1 TTL CMOS General purpose I/O. Individually enabled pull-up.
SEG1 — AN LCD analog output.
RB2/SEG2 RB2 TTL CMOS General purpose I/O. Individually enabled pull-up.
SEG2 — AN LCD analog output.
RB3/SEG3 RB3 TTL CMOS General purpose I/O. Individually enabled pull-up.
SEG3 — AN LCD analog output.
RB4/COM0 RB4 TTL CMOS General purpose I/O. Individually controlled
interrupt-on-change. Individually enabled pull-up.
COM0 — AN LCD analog output.
RB5/COM1 RB5 TTL CMOS General purpose I/O. Individually controlled
interrupt-on-change. Individually enabled pull-up.
COM1 — AN LCD analog output.
RB6/ICSPCLK/ICDCK/SEG14 RB6 TTL CMOS General purpose I/O. Individually controlled
interrupt-on-change. Individually enabled pull-up.
ICSPCLK ST — ICSP™ clock.
ICDCK ST — ICD clock.
SEG14 — AN LCD analog output.
RB7/ICSPDAT/ICDDAT/SEG13 RB7 TTL CMOS General purpose I/O. Individually controlled inter-
rupt-on-change. Individually enabled pull-up.
ICSPDAT ST CMOS ICSP Data I/O.
ICDDAT ST CMOS ICD Data I/O.
SEG13 — AN LCD analog output.
RC0/VLCD1 RC0 ST CMOS General purpose I/O.
VLCD1 AN — LCD analog input.
RC1/VLCD2 RC1 ST CMOS General purpose I/O.
VLCD2 AN — LCD analog input.
RC2/VLCD3 RC2 ST CMOS General purpose I/O.
VLCD3 AN — LCD analog input.
RC3/SEG6 RC3 ST CMOS General purpose I/O.
SEG6 — AN LCD analog output.
RC4/T1G/SDO/SEG11 RC4 ST CMOS General purpose I/O.
T1G ST — Timer1 gate input.
SDO — CMOS Serial data output.
SEG11 — AN LCD analog output.
RC5/T1CKI/CCP1/SEG10 RC5 ST CMOS General purpose I/O.
T1CKI ST — Timer1 clock input.
CCP1 ST CMOS Capture 1 input/Compare 1 output/PWM 1 output.
SEG10 — AN LCD analog output.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels P = Power
HV = High Voltage XTAL = Crystal
Note 1: COM3 is available on RA3 for the PIC16F913/916 and on RD0 for the PIC16F914/917 and PIC16F946.
2: Pins available on PIC16F914/917 and PIC16F946 only.
3: Pins available on PIC16F946 only.
4: I2C Schmitt trigger inputs have special input levels.

 2007 Microchip Technology Inc. DS41250F-page 19

PIC16F913/914/916/917/946
TABLE 1-1: PIC16F91X/946 PINOUT DESCRIPTIONS (CONTINUED)
Input Output
Name Function Description
Type Type
RC6/TX/CK/SCK/SCL/SEG9 RC6 ST CMOS General purpose I/O.
TX — CMOS USART asynchronous serial transmit.
CK ST CMOS USART synchronous serial clock.
SCK ST CMOS SPI clock.
SCL ST(4) OD I2C™ clock.
SEG9 — AN LCD analog output.
RC7/RX/DT/SDI/SDA/SEG8 RC7 ST CMOS General purpose I/O.
RX ST — USART asynchronous serial receive.
DT ST CMOS USART synchronous serial data.
SDI ST CMOS SPI data input.
SDA ST(4) OD I2C™ data.
SEG8 — AN LCD analog output.
RD0/COM3(1, 2) RD0 ST CMOS General purpose I/O.
COM3 — AN LCD analog output.
RD1(2) RD1 ST CMOS General purpose I/O.
RD2/CCP2(2) RD2 ST CMOS General purpose I/O.
CCP2 ST CMOS Capture 2 input/Compare 2 output/PWM 2 output.
RD3/SEG16(2) RD3 ST CMOS General purpose I/O.
SEG16 — AN LCD analog output.
RD4/SEG17(2) RD4 ST CMOS General purpose I/O.
SEG17 — AN LCD analog output.
(2)
RD5/SEG18 RD5 ST CMOS General purpose I/O.
SEG18 — AN LCD analog output.
RD6/SEG19(2) RD6 ST CMOS General purpose I/O.
SEG19 — AN LCD analog output.
RD7/SEG20(2) RD7 ST CMOS General purpose I/O.
SEG20 — AN LCD analog output.
(2)
RE0/AN5/SEG21 RE0 ST CMOS General purpose I/O.
AN5 AN — Analog input Channel 5.
SEG21 — AN LCD analog output.
RE1/AN6/SEG22(2) RE1 ST CMOS General purpose I/O.
AN6 AN — Analog input Channel 6.
SEG22 — AN LCD analog output.
RE2/AN7/SEG23(2) RE2 ST CMOS General purpose I/O.
AN7 AN — Analog input Channel 7.
SEG23 — AN LCD analog output.
RE3/MCLR/VPP RE3 ST — Digital input only.
MCLR ST — Master Clear with internal pull-up.
VPP HV — Programming voltage.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels P = Power
HV = High Voltage XTAL = Crystal
Note 1: COM3 is available on RA3 for the PIC16F913/916 and on RD0 for the PIC16F914/917 and PIC16F946.
2: Pins available on PIC16F914/917 and PIC16F946 only.
3: Pins available on PIC16F946 only.
4: I2C Schmitt trigger inputs have special input levels.

DS41250F-page 20  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946
TABLE 1-1: PIC16F91X/946 PINOUT DESCRIPTIONS (CONTINUED)
Input Output
Name Function Description
Type Type
RE4/SEG24(3) RE4 ST CMOS General purpose I/O.
SEG24 — AN LCD analog output.
(3)
RE5/SEG25 RE5 ST CMOS General purpose I/O.
SEG25 — AN LCD analog output.
RE6/SEG26(3) RE6 ST CMOS General purpose I/O.
SEG26 — AN LCD analog output.
RE7/SEG27(3) RE7 ST CMOS General purpose I/O.
SEG27 — AN LCD analog output.
(3)
RF0/SEG32 RF0 ST CMOS General purpose I/O.
SEG32 — AN LCD analog output.
(3)
RF1/SEG33 RF1 ST CMOS General purpose I/O.
SEG33 — AN LCD analog output.
RF2/SEG34(3) RF2 ST CMOS General purpose I/O.
SEG34 — AN LCD analog output.
RF3/SEG35(3) RF3 ST CMOS General purpose I/O.
SEG35 — AN LCD analog output.
(3)
RF4/SEG28 RF4 ST CMOS General purpose I/O.
SEG28 — AN LCD analog output.
RF5/SEG29(3) RF5 ST CMOS General purpose I/O.
SEG29 — AN LCD analog output.
RF6/SEG30(3) RF6 ST CMOS General purpose I/O.
SEG30 — AN LCD analog output.
RF7/SEG31(3) RF7 ST CMOS General purpose I/O.
SEG31 — AN LCD analog output.
(3)
RG0/SEG36 RG0 ST CMOS General purpose I/O.
SEG36 — AN LCD analog output.
RG1/SEG37(3) RG1 ST CMOS General purpose I/O.
SEG37 — AN LCD analog output.
RG2/SEG38(3) RG2 ST CMOS General purpose I/O.
SEG38 — AN LCD analog output.
RG3/SEG39(3) RG3 ST CMOS General purpose I/O.
SEG39 — AN LCD analog output.
(3)
RG4/SEG40 RG4 ST CMOS General purpose I/O.
SEG10 — AN LCD analog output.
RG5/SEG41(3) RG5 ST CMOS General purpose I/O.
SEG41 — AN LCD analog output.
AVDD(3) AVDD P — Analog power supply for microcontroller.
AVSS(3) AVSS P — Analog ground reference for microcontroller.
VDD VDD P — Power supply for microcontroller.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels P = Power
HV = High Voltage XTAL = Crystal
Note 1: COM3 is available on RA3 for the PIC16F913/916 and on RD0 for the PIC16F914/917 and PIC16F946.
2: Pins available on PIC16F914/917 and PIC16F946 only.
3: Pins available on PIC16F946 only.
4: I2C Schmitt trigger inputs have special input levels.

 2007 Microchip Technology Inc. DS41250F-page 21

PIC16F913/914/916/917/946
TABLE 1-1: PIC16F91X/946 PINOUT DESCRIPTIONS (CONTINUED)
Input Output
Name Function Description
Type Type
VSS VSS P — Ground reference for microcontroller.
Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain
TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels P = Power
HV = High Voltage XTAL = Crystal
Note 1: COM3 is available on RA3 for the PIC16F913/916 and on RD0 for the PIC16F914/917 and PIC16F946.
2: Pins available on PIC16F914/917 and PIC16F946 only.
3: Pins available on PIC16F946 only.
4: I2C Schmitt trigger inputs have special input levels.

DS41250F-page 22  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946
2.0 MEMORY ORGANIZATION FIGURE 2-2: PROGRAM MEMORY MAP
AND STACK FOR THE
2.1 Program Memory Organization PIC16F916/917/PIC16F946

The PIC16F91X/946 has a 13-bit program counter pc<12:0>

capable of addressing a 4K x 14 program memory
CALL, RETURN 13
space for the PIC16F913/914 (0000h-0FFFh) and an RETFIE, RETLW
8K x 14 program memory space for the PIC16F916/
917 and PIC16F946 (0000h-1FFFh). Accessing a
Stack Level 1
location above the memory boundaries for the
Stack Level 2
PIC16F913 and PIC16F914 will cause a wrap around
within the first 4K x 14 space. The Reset vector is at
0000h and the interrupt vector is at 0004h. Stack Level 8

FIGURE 2-1: PROGRAM MEMORY MAP Reset Vector 0000h

AND STACK FOR THE
PIC16F913/914
Interrupt Vector 0004h
0005h
pc<12:0>
Page 0
CALL, RETURN 13 07FFh
RETFIE, RETLW 0800h
Page 1
Stack Level 1 On-chip
0FFFh
Program
Stack Level 2 1000h
Mem ory
Page 2
Stack Level 8 17FFh
1800h
Page 3
Reset Vector 0000h 1FFFh

Interrupt Vector 0004h

0005h
Page 0
On-chip
07FFh
Progr am
Memory 0800h
Page 1
0FFFh
1000h

1FFFh

 2007 Microchip Technology Inc. DS41250F-page 23

PIC16F913/914/916/917/946
2.2 Data Memory Organization
The data memory is partitioned into multiple banks
which contain the General Purpose Registers (GPRs)
and the Special Function Registers (SFRs). Bits RP0
and RP1 are bank select bits.
RP1 RP0
0 0  Bank 0 is selected
0 1  Bank 1 is selected
1 0  Bank 2 is selected
1 1  Bank 3 is selected
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function
Registers are the General Purpose Registers,
implemented as static RAM. All implemented banks
contain Special Function Registers. Some frequently
used Special Function Registers from one bank are
mirrored in another bank for code reduction and
quicker access.

2.2.1 GENERAL PURPOSE REGISTER

FILE
The register file is organized as 256 x 8 bits in the
PIC16F913/914, 352 x 8 bits in the PIC16F916/917 and
336 x 8 bits in the PIC16F946. Each register is accessed
either directly or indirectly through the File Select
Register (FSR) (see Section 2.5 “Indirect Addressing,
INDF and FSR Registers”).

2.2.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by
the CPU and peripheral functions for controlling the
desired operation of the device (see Tables 2-1, 2-2,
2-3 and 2-4). These registers are static RAM.
The Special Function Registers can be classified into
two sets: core and peripheral. The Special Function
Registers associated with the “core” are described in
this section. Those related to the operation of the
peripheral features are described in the section of that
peripheral feature.

DS41250F-page 24  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946
FIGURE 2-3: PIC16F913/916 SPECIAL FUNCTION REGISTERS
File File File File
Address Address Address Address
(1)
Indirect addr. (1) 00h Indirect addr. 80h Indirect addr. (1) 100h Indirect addr. (1) 180h

TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h

PCL 02h PCL 82h PCL 102h PCL 182h
STATUS 03h STATUS 83h STATUS 103h STATUS 183h
FSR 04h FSR 84h FSR 104h FSR 184h
PORTA 05h TRISA 85h WDTCON 105h 185h
PORTB 06h TRISB 86h PORTB 106h TRISB 186h
PORTC 07h TRISC 87h LCDCON 107h 187h
08h 88h LCDPS 108h 188h
PORTE 09h TRISE 89h LVDCON 109h 189h
PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah
INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh
PIR1 0Ch PIE1 8Ch EEDATL 10Ch EECON1 18Ch
PIR2 0Dh PIE2 8Dh EEADRL 10Dh EECON2(1) 18Dh
TMR1L 0Eh PCON 8Eh EEDATH 10Eh Reserved 18Eh
TMR1H 0Fh OSCCON 8Fh EEADRH 10Fh Reserved 18Fh
T1CON 10h OSCTUNE 90h LCDDATA0 110h 190h
TMR2 11h ANSEL 91h LCDDATA1 111h
T2CON 12h PR2 92h 112h
SSPBUF 13h SSPADD 93h LCDDATA3 113h
SSPCON 14h SSPSTAT 94h LCDDATA4 114h
CCPR1L 15h WPUB 95h 115h
CCPR1H 16h IOCB 96h LCDDATA6 116h
CCP1CON 17h CMCON1 97h LCDDATA7 117h
RCSTA 18h TXSTA 98h 118h
TXREG 19h SPBRG 99h LCDDATA9 119h General
RCREG 1Ah 9Ah LCDDATA10 11Ah Purpose
1Bh 9Bh 11Bh Register(2)
1Ch CMCON0 9Ch LCDSE0 11Ch
1Dh VRCON 9Dh LCDSE1 11Dh 96 Bytes
ADRESH 1Eh ADRESL 9Eh 11Eh
ADCON0 1Fh ADCON1 9Fh 11Fh
20h A0h 120h
General General
General Purpose Purpose
Purpose Register Register
Register
80 Bytes 80 Bytes
96 Bytes EFh 16Fh 1EFh
accesses F0h accesses 170h accesses 1F0h
7Fh 70h-7Fh FFh 70h-7Fh 17Fh 70h-7Fh 1FFh
Bank 0 Bank 1 Bank 2 Bank 3

Unimplemented data memory locations, read as ‘0’.

Note 1: Not a physical register.
2: On the PIC16F913, unimplemented data memory locations, read as ‘0’.

 2007 Microchip Technology Inc. DS41250F-page 25

PIC16F913/914/916/917/946
FIGURE 2-4: PIC16F914/917 SPECIAL FUNCTION REGISTERS
File File File File
Address Address Address Address
(1)
Indirect addr. (1) 00h Indirect addr. 80h Indirect addr. (1) 100h Indirect addr. (1) 180h

TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h

PCL 02h PCL 82h PCL 102h PCL 182h
STATUS 03h STATUS 83h STATUS 103h STATUS 183h
FSR 04h FSR 84h FSR 104h FSR 184h
PORTA 05h TRISA 85h WDTCON 105h 185h
PORTB 06h TRISB 86h PORTB 106h TRISB 186h
PORTC 07h TRISC 87h LCDCON 107h 187h
PORTD 08h TRISD 88h LCDPS 108h 188h
PORTE 09h TRISE 89h LVDCON 109h 189h
PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah
INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh
PIR1 0Ch PIE1 8Ch EEDATL 10Ch EECON1 18Ch
PIR2 0Dh PIE2 8Dh EEADRL 10Dh EECON2(1) 18Dh
TMR1L 0Eh PCON 8Eh EEDATH 10Eh Reserved 18Eh
TMR1H 0Fh OSCCON 8Fh EEADRH 10Fh Reserved 18Fh
T1CON 10h OSCTUNE 90h LCDDATA0 110h 190h
TMR2 11h ANSEL 91h LCDDATA1 111h
T2CON 12h PR2 92h LCDDATA2 112h
SSPBUF 13h SSPADD 93h LCDDATA3 113h
SSPCON 14h SSPSTAT 94h LCDDATA4 114h
CCPR1L 15h WPUB 95h LCDDATA5 115h
CCPR1H 16h IOCB 96h LCDDATA6 116h
CCP1CON 17h CMCON1 97h LCDDATA7 117h
RCSTA 18h TXSTA 98h LCDDATA8 118h
TXREG 19h SPBRG 99h LCDDATA9 119h General
RCREG 1Ah 9Ah LCDDATA10 11Ah Purpose
CCPR2L 1Bh 9Bh LCDDATA11 11Bh Register(2)
CCPR2H 1Ch CMCON0 9Ch LCDSE0 11Ch
CCP2CON 1Dh VRCON 9Dh LCDSE1 11Dh 96 Bytes
ADRESH 1Eh ADRESL 9Eh LCDSE2 11Eh
ADCON0 1Fh ADCON1 9Fh 11Fh
20h A0h 120h
General General
General Purpose Purpose
Purpose Register Register
Register
80 Bytes 80 Bytes
96 Bytes EFh 16Fh 1EFh
accesses F0h accesses 170h accesses 1F0h
7Fh 70h-7Fh FFh 70h-7Fh 17Fh 70h-7Fh 1FFh
Bank 0 Bank 1 Bank 2 Bank 3

Unimplemented data memory locations, read as ‘0’.

Note 1: Not a physical register.
2: On the PIC16F914, unimplemented data memory locations, read as ‘0’.

DS41250F-page 26  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946
FIGURE 2-5: PIC16F946 SPECIAL FUNCTION REGISTERS
File File File File
Address Address Address Address
Indirect addr. (1) 00h Indirect addr. (1) 80h Indirect addr. (1) 100h Indirect addr. (1) 180h
TMR0 01h OPTION_REG 81h TMR0 101h OPTION_REG 181h
PCL 02h PCL 82h PCL 102h PCL 182h
STATUS 03h STATUS 83h STATUS 103h STATUS 183h
FSR 04h FSR 84h FSR 104h FSR 184h
PORTA 05h TRISA 85h WDTCON 105h TRISF 185h
PORTB 06h TRISB 86h PORTB 106h TRISB 186h
PORTC 07h TRISC 87h LCDCON 107h TRISG 187h
PORTD 08h TRISD 88h LCDPS 108h PORTF 188h
PORTE 09h TRISE 89h LVDCON 109h PORTG 189h
PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah
INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh
PIR1 0Ch PIE1 8Ch EEDATL 10Ch EECON1 18Ch
PIR2 PIE2 EEADRL (1)
0Dh 8Dh 10Dh EECON2 18Dh
TMR1L 0Eh PCON 8Eh EEDATH 10Eh Reserved 18Eh
TMR1H 0Fh OSCCON 8Fh EEADRH 10Fh Reserved 18Fh
T1CON 10h OSCTUNE 90h LCDDATA0 110h LCDDATA12 190h
TMR2 11h ANSEL 91h LCDDATA1 111h LCDDATA13 191h
T2CON 12h PR2 92h LCDDATA2 112h LCDDATA14 192h
SSPBUF 13h SSPADD 93h LCDDATA3 113h LCDDATA15 193h
SSPCON 14h SSPSTAT 94h LCDDATA4 114h LCDDATA16 194h
CCPR1L 15h WPUB 95h LCDDATA5 115h LCDDATA17 195h
CCPR1H 16h IOCB 96h LCDDATA6 116h LCDDATA18 196h
CCP1CON 17h CMCON1 97h LCDDATA7 117h LCDDATA19 197h
RCSTA 18h TXSTA 98h LCDDATA8 118h LCDDATA20 198h
TXREG 19h SPBRG 99h LCDDATA9 119h LCDDATA21 199h
RCREG 1Ah 9Ah LCDDATA10 11Ah LCDDATA22 19Ah
CCPR2L 1Bh 9Bh LCDDATA11 11Bh LCDDATA23 19Bh
CCPR2H 1Ch CMCON0 9Ch LCDSE0 11Ch LCDSE3 19Ch
CCP2CON 1Dh VRCON 9Dh LCDSE1 11Dh LCDSE4 19Dh
ADRESH 1Eh ADRESL 9Eh LCDSE2 11Eh LCDSE5 19Eh
ADCON0 1Fh ADCON1 9Fh 11Fh 19Fh
20h A0h 120h 1A0h
General General General
General Purpose Purpose Purpose
Purpose Register Register Register
Register
80 Bytes 80 Bytes 80 Bytes
96 Bytes
EFh 16Fh 1EFh
accesses F0h accesses 170h accesses 1F0h
7Fh 70h-7Fh FFh 70h-7Fh 17Fh 70h-7Fh 1FFh
Bank 0 Bank 1 Bank 2 Bank 3

Unimplemented data memory locations, read as ‘0’.

Note 1: Not a physical register.

 2007 Microchip Technology Inc. DS41250F-page 27

PIC16F913/914/916/917/946
TABLE 2-1: PIC16F91X/946 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0
Value on
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
POR, BOR
Bank 0
00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 41,226
01h TMR0 Timer0 Module Register xxxx xxxx 99,226
02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 40,226
03h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 32,226
04h FSR Indirect Data Memory Address Pointer xxxx xxxx 41,226
05h PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx xxxx 44,226
06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 54,226
07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 62,226
08h PORTD(2) RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx 71,226
09h PORTE RE7(3) RE6(3) RE5(3) RE4(3) RE3 RE2(2) RE1(2) RE0(2) xxxx xxxx 76,226
0Ah PCLATH — — — Write Buffer for upper 5 bits of Program Counter ---0 0000 40,226
0Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 34,226
0Ch PIR1 EEIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 37,226
0Dh PIR2 OSFIF C2IF C1IF LCDIF — LVDIF — CCP2IF(2) 0000 -0-0 38,226
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 xxxx xxxx 102,226
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 xxxx xxxx 102,226
10h T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 105,226
11h TMR2 Timer2 Module Register 0000 0000 107,226
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 108,226
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx 196,226
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 195,226
15h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx 213,226
16h CCPR1H Capture/Compare/PWM Register 1 (MSB) xxxx xxxx 213,226
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 212,226
18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 131,226
19h TXREG USART Transmit Data Register 0000 0000 130,226
1Ah RCREG USART Receive Data Register 0000 0000 128,227
1Bh(2) CCPR2L Capture/Compare/PWM Register 2 (LSB) xxxx xxxx 213,227
1Ch(2) CCPR2H Capture/Compare/PWM Register 2 (MSB) xxxx xxxx 213,227
1Dh(2) CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 212,227
1Eh ADRESH A/D Result Register High Byte xxxx xxxx 182,227
1Fh ADCON0 ADFM VCFG1 VCFG0 CHS2 CHS1 CHS0 GO/DONE ADON 0000 0000 180,227
Legend: - = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
2: PIC16F914/917 and PIC16F946 only, forced ‘0’ on PIC16F913/916.
3: PIC16F946 only, forced to ‘0’ on PIC16F91X.

DS41250F-page 28  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946
TABLE 2-2: PIC16F91X/946 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Value on
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
POR, BOR
Bank 1
80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 41,226
81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 33,227
82h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 40,226
83h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 32,226
84h FSR Indirect Data Memory Address Pointer xxxx xxxx 41,226
85h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 44,227
86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 54,227
87h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 62,227
88h TRISD(3) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 71,227
89h TRISE TRISE7(2) TRISE6(2) TRISE5(2) TRISE4(2) TRISE3(5) TRISE2(3) TRISE1(3) TRISE0(3) 1111 1111 76,227
8Ah PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 40,226
8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 34,226
8Ch PIE1 EEIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 35,227
8Dh PIE2 OSFIE C2IE C1IE LCDIE — LVDIE — CCP2IE(3) 0000 -0-0 36,227
8Eh PCON — — — SBOREN — — POR BOR ---1 --qq 39,227
8Fh OSCCON — IRCF2 IRCF1 IRCF0 OSTS(4) HTS LTS SCS -110 q000 88,227
90h OSCTUNE — — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 92,227
91h ANSEL ANS7(3) ANS6(3) ANS5(3) ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 43,227
92h PR2 Timer2 Period Register 1111 1111 107,227
93h SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 202,227
94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 194,227
95h WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 55,227
96h IOCB IOCB7 IOCB6 IOCB5 IOCB4 — — — — 0000 ---- 54,227
97h CMCON1 — — — — — — T1GSS C2SYNC - ----- 10 117,227
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 130,227
99h SPBRG SPBRG7 SPBRG6 SPBRG5 SPBRG4 SPBRG3 SPBRG2 SPBRG1 SPBRG0 0000 0000 132,227
9Ah — Unimplemented — —
9Bh — Unimplemented — —
9Ch CMCON0 C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 116,227
9Dh VRCON VREN — VRR — VR3 VR2 VR1 VR0 0-0- 0000 118,227
9Eh ADRESL A/D Result Register Low Byte xxxx xxxx 182,227
9Fh ADCON1 — ADCS2 ADCS1 ADCS0 — — — — -000 ---- 181,227
Legend: - = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
2: PIC16F946 only, forced ‘0’ on PIC16F91X.
3: PIC16F914/917 and PIC16F946 only, forced ‘0’ on PIC16F913/916.
4: The value of the OSTS bit is dependent on the value of the Configuration Word (CONFIG) of the device. See Section 4.2 “Oscillator
Control”.
5: Bit is read-only; TRISE3 = 1 always.

 2007 Microchip Technology Inc. DS41250F-page 29

PIC16F913/914/916/917/946
TABLE 2-3: PIC16F91X/946 SPECIAL FUNCTION REGISTERS SUMMARY BANK 2
Value on
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
POR, BOR
Bank 2
100h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 41,226
101h TMR0 Timer0 Module Register xxxx xxxx 99,226
102h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 40,226
103h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 32,226
104h FSR Indirect Data Memory Address Pointer xxxx xxxx 41,226
105h WDTCON — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000 235,227
106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 54,226
107h LCDCON LCDEN SLPEN WERR VLCDEN CS1 CS0 LMUX1 LMUX0 0001 0011 145,227
108h LCDPS WFT BIASMD LCDA WA LP3 LP2 LP1 LP0 0000 0000 146,227
109h LVDCON — — IRVST LVDEN — LVDL2 LVDL1 LVDL0 --00 -100 145,228
10Ah PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 40,226
10Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 34,226
10Ch EEDATL EEDATL7 EEDATL6 EEDATL5 EEDATL4 EEDATL3 EEDATL2 EEDATL1 EEDATL0 0000 0000 188,228
10Dh EEADRL EEADRL7 EEADRL6 EEADRL5 EEADRL4 EEADRL3 EEADRL2 EEADRL1 EEADRL0 0000 0000 188,228
10Eh EEDATH — — EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATH0 --00 0000 188,228
10Fh EEADRH — — — EEADRH4 EEADRH3 EEADRH2 EEADRH1 EEADRH0 ---0 0000 188,228
110h LCDDATA0 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 xxxx xxxx 147,228
COM0 COM0 COM0 COM0 COM0 COM0 COM0 COM0
111h LCDDATA1 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 xxxx xxxx 147,228
COM0 COM0 COM0 COM0 COM0 COM0 COM0 COM0
112h LCDDATA2(2) SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 xxxx xxxx 147,228
COM0 COM0 COM0 COM0 COM0 COM0 COM0 COM0
113h LCDDATA3 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 xxxx xxxx 147,228
COM1 COM1 COM1 COM1 COM1 COM1 COM1 COM1
114h LCDDATA4 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 xxxx xxxx 147,228
COM1 COM1 COM1 COM1 COM1 COM1 COM1 COM1
115h LCDDATA5(2) SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 xxxx xxxx 147,228
COM1 COM1 COM1 COM1 COM1 COM1 COM1 COM1
116h LCDDATA6 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 xxxx xxxx 147,228
COM2 COM2 COM2 COM2 COM2 COM2 COM2 COM2
117h LCDDATA7 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 xxxx xxxx 147,228
COM2 COM2 COM2 COM2 COM2 COM2 COM2 COM2
118h LCDDATA8(2) SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 xxxx xxxx 147,228
COM2 COM2 COM2 COM2 COM2 COM2 COM2 COM2
119h LCDDATA9 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 xxxx xxxx 147,228
COM3 COM3 COM3 COM3 COM3 COM3 COM3 COM3
11Ah LCDDATA10 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 xxxx xxxx 147,228
COM3 COM3 COM3 COM3 COM3 COM3 COM3 COM3
(2)
11Bh LCDDATA11 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 xxxx xxxx 147,228
COM3 COM3 COM3 COM3 COM3 COM3 COM3 COM3
11Ch LCDSE0(3) SE7 SE6 SE5 SE4 SE3 SE2 SE1 SE0 0000 0000 147,228
11Dh LCDSE1(3) SE15 SE14 SE13 SE12 SE11 SE10 SE9 SE8 0000 0000 147,228
11Eh LCDSE2(2,3) SE23 SE22 SE21 SE20 SE19 SE18 SE17 SE16 0000 0000 147,228
11Fh — Unimplemented — —
Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
2: PIC16F914/917 and PIC16F946 only.
3: This register is only initialized by a POR or BOR reset and is unchanged by other Resets.

DS41250F-page 30  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946
TABLE 2-4: PIC16F91X/946 SPECIAL FUNCTION REGISTERS SUMMARY BANK 3
Value on
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
POR, BOR
Bank 3
180h INDF Addressing this location uses contents of FSR to address data memory (not a physical xxxx xxxx 41,226
register)
181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 33,227
182h PCL Program Counter (PC) Least Significant Byte 0000 0000 40,226
183h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 32,226
184h FSR Indirect Data Memory Address Pointer xxxx xxxx 41,226
185h TRISF(3) TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 1111 1111 81,228
186h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 54,227
187h TRISG(3) — — TRISG5 TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 --11 1111 84,228
188h PORTF(3) RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0 xxxx xxxx 81,228
189h PORTG(3) — — RG5 RG4 RG3 RG2 RG1 RG0 --xx xxxx 84,228
18Ah PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 40,226
18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 34,226
18Ch EECON1 EEPGD — — — WRERR WREN WR RD 0--- x000 189,229
18Dh EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- 187
18Eh — Reserved — —
18Fh — Reserved — —
190h LCDDATA12(3) SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 xxxx xxxx 147,228
COM0 COM0 COM0 COM0 COM0 COM0 COM0 COM0
191h LCDDATA13(3) SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SE33 SEG32 xxxx xxxx 147,228
COM0 COM0 COM0 COM0 COM0 COM0 COM0 COM0
192h LCDDATA14(3) — — — — — — SEG41 SEG40 - ------xx 147,228
COM0 COM0
193h LCDDATA15(3) SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 xxxx xxxx 147,228
COM1 COM1 COM1 COM1 COM1 COM1 COM1 COM1
194h LCDDATA16(3) SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 xxxx xxxx 147,228
COM1 COM1 COM1 COM1 COM1 COM1 COM1 COM1
195h LCDDATA17(3) — — — — — — SEG41 SEG40 - ------xx 147,228
COM1 COM1
196h LCDDATA18(3) SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 xxxx xxxx 147,228
COM2 COM2 COM2 COM2 COM2 COM2 COM2 COM2
197h LCDDATA19(3) SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 xxxx xxxx 147,228
COM2 COM2 COM2 COM2 COM2 COM2 COM2 COM2
198h LCDDATA20(3) — — — — — — SEG41 SEG40 - ------xx 147,228
COM2 COM2
199h LCDDATA21(3) SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 xxxx xxxx 147,228
COM3 COM3 COM3 COM3 COM3 COM3 COM3 COM3
19Ah LCDDATA22(3) SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 xxxx xxxx 147,228
COM3 COM3 COM3 COM3 COM3 COM3 COM3 COM3
19Bh LCDDATA23(3) — — — — — — SEG41 SEG40 - ------xx 147,228
COM3 COM3
19Ch LCDSE3(2, 3) SE31 SE30 SE29 SE28 SE27 SE26 SE25 SE24 0000 0000 147,229
(2, 3)
19Dh LCDSE4 SE39 SE38 SE37 SE36 SE35 SE34 SE33 SE32 0000 0000 147,229
19Eh LCDSE5(2, 3) — — — — — — SE41 SE40 - ------00 147,229
19Fh — Unimplemented — —
Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
2: This register is only initialized by a POR or BOR reset and is unchanged by other Resets.
3: PIC16F946 only.

 2007 Microchip Technology Inc. DS41250F-page 31

PIC16F913/914/916/917/946
2.2.2.1 STATUS Register For example, CLRF STATUS will clear the upper three
The STATUS register, shown in Register 2-1, contains: bits and set the Z bit. This leaves the STATUS register
as ‘000u u1uu’ (where u = unchanged).
• the arithmetic status of the ALU
It is recommended, therefore, that only BCF, BSF,
• the Reset status
SWAPF and MOVWF instructions are used to alter the
• the bank select bits for data memory (SRAM) STATUS register, because these instructions do not
The STATUS register can be the destination for any affect any Status bits. For other instructions not
instruction, like any other register. If the STATUS affecting any Status bits (see Section 17.0
register is the destination for an instruction that affects “Instruction Set Summary”).
the Z, DC or C bits, then the write to these three bits is Note 1: The C and DC bits operate as Borrow and
disabled. These bits are set or cleared according to the Digit Borrow out bits, respectively, in
device logic. Furthermore, the TO and PD bits are not subtraction.
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
REGISTER 2-1: STATUS: STATUS REGISTER
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO PD Z DC(1) C(1)
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h-1FFh)
0 = Bank 0, 1 (00h-FFh)
bit 6-5 RP<1:0>: Register Bank Select bits (used for direct addressing)
00 = Bank 0 (00h-7Fh)
01 = Bank 1 (80h-FFh)
10 = Bank 2 (100h-17Fh)
11 = Bank 3 (180h-1FFh)
bit 4 TO: Time-out bit
1 = After power-up, CLRWDT instruction or SLEEP instruction
0 = A WDT time-out occurred
bit 3 PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit Carry/Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(1)
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
bit 0 C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred

Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order
bit of the source register.

DS41250F-page 32  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946
2.2.2.2 OPTION register
Note: To achieve a 1:1 prescaler assignment for
The OPTION register, shown in Register 2-2, is a
Timer0, assign the prescaler to the WDT by
readable and writable register, which contains various
setting PSA bit of the OPTION register to
control bits to configure:
‘1’. See Section 6.3 “Timer1 Prescaler”.
• Timer0/WDT prescaler
• External RB0/INT interrupt
• Timer0
• Weak pull-ups on PORTB

REGISTER 2-2: OPTION_REG: OPTION REGISTER

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 RBPU: PORTB Pull-up Enable bit

1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual bits in the WPUB register
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5 T0CS: Timer0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (FOSC/4)
bit 4 T0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS<2:0>: Prescaler Rate Select bits
Bit Value Timer0 Rate WDT Rate
000 1:2 1:1
001 1:4 1:2
010 1:8 1:4
011 1 : 16 1:8
100 1 : 32 1 : 16
101 1 : 64 1 : 32
110 1 : 128 1 : 64
111 1 : 256 1 : 128

 2007 Microchip Technology Inc. DS41250F-page 33

PIC16F913/914/916/917/946
2.2.2.3 INTCON Register
Note: Interrupt flag bits are set when an interrupt
The INTCON register is a readable and writable
condition occurs, regardless of the state of
register, which contains the various enable and flag bits
its corresponding enable bit or the global
for TMR0 register overflow, PORTB change and
enable bit, GIE of the INTCON register.
external RB0/INT/SEG0 pin interrupts.
User software should ensure the appropri-
ate interrupt flag bits are clear prior to
enabling an interrupt.

REGISTER 2-3: INTCON: INTERRUPT CONTROL REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
(1) (2)
GIE PEIE T0IE INTE RBIE T0IF INTF RBIF
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 GIE: Global Interrupt Enable bit

1 = Enables all unmasked interrupts
0 = Disables all interrupts
bit 6 PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5 T0IE: Timer0 Overflow Interrupt Enable bit
1 = Enables the Timer0 interrupt
0 = Disables the Timer0 interrupt
bit 4 INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3 RBIE: PORTB Change Interrupt Enable bit(1)
1 = Enables the PORTB change interrupt
0 = Disables the PORTB change interrupt
bit 2 T0IF: Timer0 Overflow Interrupt Flag bit(2)
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1 INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0 RBIF: PORTB Change Interrupt Flag bit
1 = When at least one of the PORTB general purpose I/O pins changed state (must be cleared in soft-
ware)
0 = None of the PORTB general purpose I/O pins have changed state

Note 1: The appropriate bits in the IOCB register must also be set.
2: T0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should be initialized before
clearing T0IF bit.

DS41250F-page 34  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946
2.2.2.4 PIE1 Register
The PIE1 register contains the interrupt enable bits, as Note: Bit PEIE of the INTCON register must be
shown in Register 2-4. set to enable any peripheral interrupt.

REGISTER 2-4: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
EEIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 EEIE: EE Write Complete Interrupt Enable bit

1 = Enables the EE write complete interrupt
0 = Disables the EE write complete interrupt
bit 6 ADIE: A/D Converter (ADC) Interrupt Enable bit
1 = Enables the ADC interrupt
0 = Disables the ADC interrupt
bit 5 RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt
bit 4 TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
bit 3 SSPIE: Synchronous Serial Port (SSP) Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
bit 2 CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the Timer2 to PR2 match interrupt
0 = Disables the Timer2 to PR2 match interrupt
bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit
1 = Enables the Timer1 overflow interrupt
0 = Disables the Timer1 overflow interrupt

 2007 Microchip Technology Inc. DS41250F-page 35

PIC16F913/914/916/917/946
2.2.2.5 PIE2 Register
The PIE2 register contains the interrupt enable bits, as Note: Bit PEIE of the INTCON register must be
shown in Register 2-5. set to enable any peripheral interrupt.

REGISTER 2-5: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2

R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0
OSFIE C2IE C1IE LCDIE — LVDIE — CCP2IE(1)
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 OSFIE: Oscillator Fail Interrupt Enable bit

1 = Enables oscillator fail interrupt
0 = Disables oscillator fail interrupt
bit 6 C2IE: Comparator C2 Interrupt Enable bit
1 = Enables Comparator C2 interrupt
0 = Disables Comparator C2 interrupt
bit 5 C1IE: Comparator C1 Interrupt Enable bit
1 = Enables Comparator C1 interrupt
0 = Disables Comparator C1 interrupt
bit 4 LCDIE: LCD Module Interrupt Enable bit
1 = Enables LCD interrupt
0 = Disables LCD interrupt
bit 3 Unimplemented: Read as ‘0’
bit 2 LVDIE: Low Voltage Detect Interrupt Enable bit
1 = Enables LVD Interrupt
0 = Disables LVD Interrupt
bit 1 Unimplemented: Read as ‘0’
bit 0 CCP2IE: CCP2 Interrupt Enable bit(1)
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt

Note 1: PIC16F914/PIC16F917/PIC16F946 only.

DS41250F-page 36  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946
2.2.2.6 PIR1 Register
The PIR1 register contains the interrupt flag bits, as Note: Interrupt flag bits are set when an interrupt
shown in Register 2-6. condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.

REGISTER 2-6: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1

R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
EEIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 EEIF: EE Write Operation Interrupt Flag bit

1 = The write operation completed (must be cleared in software)
0 = The write operation has not completed or has not started
bit 6 ADIF: A/D Converter Interrupt Flag bit
1 = A/D conversion complete (must be cleared in software)
0 = A/D conversion has not completed or has not been started
bit 5 RCIF: USART Receive Interrupt Flag bit
1 = The USART receive buffer is full (cleared by reading RCREG)
0 = The USART receive buffer is not full
bit 4 TXIF: USART Transmit Interrupt Flag bit
1 = The USART transmit buffer is empty (cleared by writing to TXREG)
0 = The USART transmit buffer is full
bit 3 SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit
1 = The Transmission/Reception is complete (must be cleared in software)
0 = Waiting to Transmit/Receive
bit 2 CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode
Unused in this mode
bit 1 TMR2IF: Timer2 to PR2 Interrupt Flag bit
1 = A Timer2 to PR2 match occurred (must be cleared in software)
0 = No Timer2 to PR2 match occurred
bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit
1 = The TMR1 register overflowed (must be cleared in software)
0 = The TMR1 register did not overflow

 2007 Microchip Technology Inc. DS41250F-page 37

PIC16F913/914/916/917/946
2.2.2.7 PIR2 Register
The PIR2 register contains the interrupt flag bits, as Note: Interrupt flag bits are set when an interrupt
shown in Register 2-7. condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.

REGISTER 2-7: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2

R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0
OSFIF C2IF C1IF LCDIF — LVDIF — CCP2IF(1)
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 OSFIF: Oscillator Fail Interrupt Flag bit

1 = System oscillator failed, clock input has changed to INTOSC (must be cleared in software)
0 = System clock operating
bit 6 C2IF: Comparator C2 Interrupt Flag bit
1 = Comparator output (C2OUT bit) has changed (must be cleared in software)
0 = Comparator output (C2OUT bit) has not changed
bit 5 C1IF: Comparator C1 Interrupt Flag bit
1 = Comparator output (C1OUT bit) has changed (must be cleared in software)
0 = Comparator output (C1OUT bit) has not changed
bit 4 LCDIF: LCD Module Interrupt bit
1 = LCD has generated an interrupt
0 = LCD has not generated an interrupt
bit 3 Unimplemented: Read as ‘0’
bit 2 LVDIF: Low Voltage Detect Interrupt Flag bit
1 = LVD has generated an interrupt
0 = LVD has not generated an interrupt
bit 1 Unimplemented: Read as ‘0’
bit 0 CCP2IF: CCP2 Interrupt Flag bit(1)
Capture Mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode

Note 1: PIC16F914/PIC16F917/PIC16F946 only.

DS41250F-page 38  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946
2.2.2.8 PCON Register
The Power Control (PCON) register contains flag bits
(see Table 16-2) to differentiate between a:
• Power-on Reset (POR)
• Brown-out Reset (BOR)
• Watchdog Timer Reset (WDT)
• External MCLR Reset
The PCON register also controls the software enable of
the BOR.
The PCON register bits are shown in Register 2-8.

REGISTER 2-8: PCON: POWER CONTROL REGISTER

U-0 U-0 U-0 R/W-1 U-0 U-0 R/W-0 R/W-x
— — — SBOREN — — POR BOR
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4 SBOREN: Software BOR Enable bit(1)
1 = BOR enabled
0 = BOR disabled
bit 3-2 Unimplemented: Read as ‘0’
bit 1 POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset
occurs)

Note 1: Set BOREN<1:0> = 01 in the Configuration Word register for this bit to control the BOR.

 2007 Microchip Technology Inc. DS41250F-page 39

PIC16F913/914/916/917/946
2.3 PCL and PCLATH
The Program Counter (PC) is 13 bits wide. The low Note 1: There are no Status bits to indicate stack
byte comes from the PCL register, which is a readable overflow or stack underflow conditions.
and writable register. The high byte (PC<12:8>) is not 2: There are no instructions/mnemonics
directly readable or writable and comes from called PUSH or POP. These are actions
PCLATH. On any Reset, the PC is cleared. Figure 2-6 that occur from the execution of the CALL,
shows the two situations for the loading of the PC. The RETURN, RETLW and RETFIE instruc-
upper example in Figure 2-6 shows how the PC is tions or the vectoring to an interrupt
loaded on a write to PCL (PCLATH<4:0>  PCH). address.
The lower example in Figure 2-6 shows how the PC is
loaded during a CALL or GOTO instruction 2.4 Program Memory Paging
(PCLATH<4:3>  PCH).
All PIC16F91X/946 devices are capable of addressing
FIGURE 2-6: LOADING OF PC IN a continuous 8K word block of program memory. The
DIFFERENT SITUATIONS CALL and GOTO instructions provide only 11 bits of
address to allow branching within any 2K program
PCH PCL memory page. When doing a CALL or GOTO instruction,
Instruction with
12 8 7 0 PCL as the upper 2 bits of the address are provided by
PC Destination PCLATH<4:3>. When doing a CALL or GOTO instruc-
PCLATH<4:0> 8 tion, the user must ensure that the page select bits are
5 ALU Result programmed so that the desired program memory
page is addressed. If a return from a CALL instruction
PCLATH (or interrupt) is executed, the entire 13-bit PC is POPed
off the stack. Therefore, manipulation of the
PCH PCL PCLATH<4:3> bits is not required for the RETURN
12 11 10 8 7 0 instructions (which POPs the address from the stack).
PC GOTO, CALL
Note: The contents of the PCLATH register are
2
PCLATH<4:3> 11 unchanged after a RETURN or RETFIE
OPCODE<10:0>
instruction is executed. The user must
rewrite the contents of the PCLATH regis-
PCLATH
ter for any subsequent subroutine calls or
GOTO instructions.
2.3.1 COMPUTED GOTO
Example 2-1 shows the calling of a subroutine in
A computed GOTO is accomplished by adding an offset page 1 of the program memory. This example assumes
to the program counter (ADDWF PCL). When perform- that PCLATH is saved and restored by the Interrupt
ing a table read using a computed GOTO method, care Service Routine (if interrupts are used).
should be exercised if the table location crosses a PCL
memory boundary (each 256-byte block). Refer to the EXAMPLE 2-1: CALL OF A SUBROUTINE
Application Note AN556, “Implementing a Table Read” IN PAGE 1 FROM PAGE 0
(DS00556).
ORG 500h
BCF PCLATH,4
2.3.2 STACK
BSF PCLATH,3 ;Select page 1
The PIC16F91X/946 family has an 8-level x 13-bit wide ;(800h-FFFh)
hardware stack (see Figures 2-1 and 2-2). The stack CALL SUB1_P1 ;Call subroutine in
space is not part of either program or data space and : ;page 1 (800h-FFFh)
the Stack Pointer is not readable or writable. The PC is :
PUSHed onto the stack when a CALL instruction is ORG 900h ;page 1 (800h-FFFh)
SUB1_P1
executed or an interrupt causes a branch. The stack is
: ;called subroutine
POPed in the event of a RETURN, RETLW or a RETFIE
;page 1 (800h-FFFh)
instruction execution. PCLATH is not affected by a :
PUSH or POP operation. RETURN ;return to
The stack operates as a circular buffer. This means that ;Call subroutine
after the stack has been PUSHed eight times, the ninth ;in page 0
;(000h-7FFh)
PUSH overwrites the value that was stored from the
first PUSH. The tenth PUSH overwrites the second
PUSH (and so on).

DS41250F-page 40  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946
2.5 Indirect Addressing, INDF and EXAMPLE 2-2: INDIRECT ADDRESSING
FSR Registers MOVLW 020h ;initialize pointer
MOVWF FSR ;to RAM
The INDF register is not a physical register. Addressing BANKISEL 020h
the INDF register will cause indirect addressing. NEXT CLRF INDF ;clear INDF register
Indirect addressing is possible by using the INDF INCF FSR ;inc pointer
BTFSS FSR,4 ;all done?
register. Any instruction using the INDF register
GOTO NEXT ;no clear next
actually accesses data pointed to by the File Select
CONTINUE ;yes continue
Register (FSR). Reading INDF itself indirectly will
produce 00h. Writing to the INDF register indirectly
results in a no operation (although Status bits may be
affected). An effective 9-bit address is obtained by
concatenating the 8-bit FSR register and the IRP bit of
the STATUS register, as shown in Figure 2-7.
A simple program to clear RAM location 020h-02Fh
using indirect addressing is shown in Example 2-2.

FIGURE 2-7: DIRECT/INDIRECT ADDRESSING PIC16F91X/946

Direct Addressing Indirect Addressing

RP1 RP0 6 From Opcode 0 IRP 7 File Select Register 0

Bank Select Location Select Bank Select Location Select

00 01 10 11
00h 180h

Data
Memory

7Fh 1FFh
Bank 0 Bank 1 Bank 2 Bank 3
Note: For memory map detail, see Figures 2-3 and 2-4.

 2007 Microchip Technology Inc. DS41250F-page 41

PIC16F913/914/916/917/946
NOTES:

DS41250F-page 42  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946
3.0 I/O PORTS 3.1 ANSEL Register
The PIC16F913/914/916/917/946 family of devices The ANSEL register (Register 3-1) is used to configure
includes several 8-bit PORT registers along with their the Input mode of an I/O pin to analog. Setting the
corresponding TRIS registers and one four bit port: appropriate ANSEL bit high will cause all digital reads
on the pin to be read as ‘0’ and allow analog functions
• PORTA and TRISA
on the pin to operate correctly.
• PORTB and TRISB
The state of the ANSEL bits has no affect on digital out-
• PORTC and TRISC
put functions. A pin with TRIS clear and ANSEL set will
• PORTD and TRISD(1) still operate as a digital output, but the Input mode will
• PORTE and TRISE be analog. This can cause unexpected behavior when
• PORTF and TRISF(2) executing read-modify-write instructions on the
affected port.
• PORTG and TRISG(2)

Note 1: PIC16F914/917 and PIC16F946 only.

2: PIC16F946 only
PORTA, PORTB, PORTC and RE3/MCLR/VPP are
implemented on all devices. PORTD and RE<2:0>
(PORTE) are implemented only on the PIC16F914/917
and PIC16F946. RE<7:4> (PORTE), PORTF and
PORTG are implemented only on the PIC16F946.
REGISTER 3-1: ANSEL: ANALOG SELECT REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
ANS7(2) ANS6(2) ANS5(2) ANS4 ANS3 ANS2 ANS1 ANS0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 ANS<7:0>: Analog Select bits

Analog select between analog or digital function on pins AN<7:0>, respectively.
1 = Analog input. Pin is assigned as analog input(1).
0 = Digital I/O. Pin is assigned to port or special function.

Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and
interrupt-on-change if available. The corresponding TRIS bit must be set to Input mode in order to allow
external control of the voltage on the pin.
2: PIC16F914/PIC16F917/PIC16F946 only.

 2007 Microchip Technology Inc. DS41250F-page 43

PIC16F913/914/916/917/946
3.2 PORTA and TRISA Registers The TRISA register controls the direction of the PORTA
pins, even when they are being used as analog inputs.
PORTA is a 8-bit wide, bidirectional port. The The user must ensure the bits in the TRISA register are
corresponding data direction register is TRISA maintained set when using them as analog inputs. I/O
(Register 3-3). Setting a TRISA bit (= 1) will make the pins configured as analog inputs always read ‘0’.
corresponding PORTA pin an input (i.e., put the
corresponding output driver in a High-Impedance mode).
Clearing a TRISA bit (= 0) will make the corresponding Note 1: The CMCON0 and ANSEL registers must
PORTA pin an output (i.e., put the contents of the output be initialized to configure an analog
latch on the selected pin). Example 3-1 shows how to channel as a digital input. Pins configured
initialize PORTA. as analog inputs will read ‘0’.
Five of the pins of PORTA can be configured as analog
inputs. These pins, RA5 and RA<3:0>, are configured EXAMPLE 3-1: INITIALIZING PORTA
as analog inputs on device power-up and must be
BANKSEL PORTA ;
reconfigured by the user to be used as I/O’s. This is CLRF PORTA ;Init PORTA
done by writing the appropriate values to the CMCON0 BANKSEL TRISA ;
and ANSEL registers (see Example 3-1). MOVLW 07h ;Set RA<2:0> to
MOVWF CMCON0 ;digital I/O
Reading the PORTA register (Register 3-2) reads the
CLRF ANSEL ;Make all PORTA digital I/O
status of the pins, whereas writing to it will write to the
MOVLW 0F0h ;Set RA<7:4> as inputs
PORT latch. All write operations are read-modify-write MOVWF TRISA ;and set RA<3:0> as outputs
operations. Therefore, a write to a port means that the
port pins are read, this value is modified and then written
to the PORT data latch.

REGISTER 3-2: PORTA: PORTA REGISTER

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 RA<7:0>: PORTA I/O Pin bits

1 = Port pin is >V IH min.
0 = Port pin is <VIL max.

REGISTER 3-3: TRISA: PORTA TRI-STATE REGISTER

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 TRISA<7:0>: PORTA Tri-State Control bits

1 = PORTA pin configured as an input (tri-stated)
0 = PORTA pin configured as an output

Note 1: TRISA<7:6> always reads ‘1’ in XT, HS and LP Oscillator modes.

DS41250F-page 44  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946
3.2.1 PIN DESCRIPTIONS AND
DIAGRAMS
Each PORTA pin is multiplexed with other functions. The
pins and their combined functions are briefly described
here. For specific information about individual functions,
refer to the appropriate section in this data sheet.

3.2.1.1 RA0/AN0/C1-/SEG12
Figure 3-1 shows the diagram for this pin. The RA0 pin
is configurable to function as one of the following:
• a general purpose I/O
• an analog input for the ADC
• an analog input for Comparator C1
• an analog output for the LCD

FIGURE 3-1: BLOCK DIAGRAM OF RA0

Data Bus
D Q

WR PORTA
CK Q VDD
Data Latch

D Q
I/O Pin
WR TRISA VSS
CK Q
TRIS Latch
Analog Input or
SE12 and LCDEN
TTL
RD TRISA SE12 and LCDEN Input Buffer

RD PORTA

SE12 and LCDEN

SEG12

To A/D Converter and Comparator

 2007 Microchip Technology Inc. DS41250F-page 45

PIC16F913/914/916/917/946
3.2.1.2 RA1/AN1/C2-/SEG7
Figure 3-2 shows the diagram for this pin. The RA1 pin
is configurable to function as one of the following:
• a general purpose I/O
• an analog input for the ADC
• an analog input for Comparator C2
• an analog output for the LCD

FIGURE 3-2: BLOCK DIAGRAM OF RA1

Data Bus
D Q

WR PORTA
CK Q VDD
Data Latch

D Q
I/O Pin
WR TRISA VSS
CK Q
TRIS Latch
Analog Input or
SE7 and LCDEN
TTL
RD TRISA SE7 and LCDEN Input Buffer

RD PORTA
SE7 and LCDEN
SEG7

To A/D Converter and Comparator

DS41250F-page 46  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946
3.2.1.3 RA2/AN2/C2+/VREF-/COM2
Figure 3-3 shows the diagram for this pin. The RA2 pin
is configurable to function as one of the following:
• a general purpose I/O
• an analog input for the ADC
• an analog input for Comparator C2
• a voltage reference input for the ADC
• an analog output for the LCD

FIGURE 3-3: BLOCK DIAGRAM OF RA2

Data Bus
D Q

WR PORTA VDD
CK Q
Data Latch

D Q I/O Pin

WR TRISA VSS
CK Q
TRIS Latch Analog Input or
LCDEN and
LMUX<1:0> = 1X

RD TRISA LCDEN and TTL

LMUX<1:0> = 1X Input Buffer

RD PORTA

LCDEN and
LMUX<1:0> = 1X
COM2

To A/D Converter and Comparator

To A/D Module VREF- Input

 2007 Microchip Technology Inc. DS41250F-page 47

PIC16F913/914/916/917/946
3.2.1.4 RA3/AN3/C1+/VREF+/COM3/SEG15
Figure 3-4 shows the diagram for this pin. The RA3 pin
is configurable to function as one of the following:
• a general purpose input
• an analog input for the ADC
• an analog input from Comparator C1
• a voltage reference input for the ADC
• analog outputs for the LCD

FIGURE 3-4: BLOCK DIAGRAM OF RA3

Data Bus
D Q

WR PORTA VDD
CK Q
Data Latch

D Q I/O Pin

WR TRISA VSS
CK Q
TRIS Latch
Analog Input or
LCDMODE_EN(2)

RD TRISA TTL
LCDMODE_EN(2) Input Buf fer

RD PORTA

LCDMODE_EN (2)
COM3(1) or SEG15

To A/D Converter and Comparator

To A/D Module VREF+ Input

Note 1: PIC16F913/916 only.

2: For the PIC16F913/916, the LCDMODE_EN = LCDEN and (SE15 or LMUX<1:0> = 11).
For the PIC16F914/917 and PIC16F946, the LCDMODE_EN = LCDEN and SE15.

DS41250F-page 48  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946
3.2.1.5 RA4/C1OUT/T0CKI/SEG4
Figure 3-5 shows the diagram for this pin. The RA4 pin
is configurable to function as one of the following:
• a general purpose I/O
• a digital output from Comparator C1
• a clock input for Timer0
• an analog output for the LCD

FIGURE 3-5: BLOCK DIAGRAM OF RA4

CM<2:0> = 110 or 101

C1OUT
1
Data Bus 0
D Q
VDD
WR PORTA
CK Q
Data Latch
D Q I/O Pin
VSS
WR TRISA
CK Q
TRIS Latch
SE4 and LCDEN

TTL
RD TRISA SE4 and LCDEN Input Buf fer

RD PORTA
Schmitt Trigger
T0CKI SE4 and LCDEN

SE4 and LCDEN

SEG4

 2007 Microchip Technology Inc. DS41250F-page 49

PIC16F913/914/916/917/946
3.2.1.6 RA5/AN4/C2OUT/SS/SEG5
Figure 3-6 shows the diagram for this pin. The RA5 pin
is configurable to function as one of the following:
• a general purpose I/O
• a digital output from Comparator C2
• a slave select input
• an analog output for the LCD
• an analog input for the ADC

FIGURE 3-6: BLOCK DIAGRAM OF RA5

CM<2:0> = 110 or 101

C2OUT
1
Data Bus
D Q 0
VDD
WR PORTA
CK Q
Data Latch
D Q I/O Pin
VSS
WR TRISA
CK Q
TRIS Latch
Analog Input or
SE5 and LCDEN
TTL
RD TRISA SE5 and LCDEN Input Buffer

RD PORTA

To SS Input
SE5 and LCDEN
SEG5

To A/D Converter

DS41250F-page 50  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946
3.2.1.7 RA6/OSC2/CLKOUT/T1OSO
Figure 3-7 shows the diagram for this pin. The RA6 pin
is configurable to function as one of the following:
• a general purpose I/O
• a crystal/resonator connection
• a clock output
• a Timer1 oscillator connection

FIGURE 3-7: BLOCK DIAGRAM OF RA6

FOSC = 1x1
From OSC1 Oscillator
CLKOUT (FOSC/4) Circuit
1
Data Bus D Q 0
VDD
WR PORTA
CK Q
Data Latch
D Q I/O Pin
VSS
WR TRISA
CK Q
FOSC = 00x, 010
TRIS Latch
FOSC = 00x, 010 or T1OSCEN
or T1OSCEN
TTL
Input Buffer
RD TRISA

RD PORTA

 2007 Microchip Technology Inc. DS41250F-page 51

PIC16F913/914/916/917/946
3.2.1.8 RA7/OSC1/CLKIN/T1OSI
Figure 3-8 shows the diagram for this pin. The RA7 pin
is configurable to function as one of the following:
• a general purpose I/O
• a crystal/resonator connection
• a clock input
• a Timer1 oscillator connection

FIGURE 3-8: BLOCK DIAGRAM OF RA7

To OSC2 Oscillator
Circuit
FOSC = 011
Data Bus
D Q

WR PORTA
CK Q
VDD
Data Latch

D Q
I/O Pin
WR TRISA VSS
CK Q
FOSC = 10x
FOSC = 10x TRIS Latch
TTL
Input Buffer

RD TRISA

RD PORTA

TABLE 3-1: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Value on Value on all
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR other Resets

ADCON0 ADFM VCFG1 VCFG0 CHS2 CHS1 CHS0 GO/DONE ADON 0000 0000 0000 0000
ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111
CMCON0 C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 0000 0000
CONFIG(1) CPD CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 — —
OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
LCDCON LCDEN SLPEN WERR VLCDEN CS1 CS0 LMUX1 LMUX0 0001 0011 0001 0011
LCDSE0 SE7 SE6 SE5 SE4 SE3 SE2 SE1 SE0 0000 0000 uuuu uuuu
LCDSE1 SE15 SE14 SE13 SE12 SE11 SE10 SE9 SE8 0000 0000 uuuu uuuu
PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx xxxx uuuu uuuu
SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu
TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.
Note 1: See Configuration Word register (CONFIG) for operation of all register bits.

DS41250F-page 52  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946
3.3 PORTB and TRISB Registers 3.4 Additional PORTB Pin Functions
PORTB is an 8-bit bidirectional I/O port. All PORTB pins RB<7:6> are used as data and clock signals, respectively,
can have a weak pull-up feature, and PORTB<7:4> for both serial programming and the in-circuit debugger
implements an interrupt-on-input change function. features on the device. Also, RB0 can be configured as an
PORTB is also used for the Serial Flash programming external interrupt input.
interface and ICD interface.
3.4.1 WEAK PULL-UPS
EXAMPLE 3-2: INITIALIZING PORTB Each of the PORTB pins has an individually configurable
internal weak pull-up. Control bits WPUB<7:0> enable or
BANKSEL PORTB ;
disable each pull-up. Refer to Register 3-7. Each weak
CLRF PORTB ;Init PORTB
pull-up is automatically turned off when the port pin is
BANKSEL TRISB ;
MOVLW 0FFh ;Set RB<7:0> as inputs configured as an output. The pull-ups are disabled on a
MOVWF TRISB ; Power-on Reset by the RBPU bit of the OPTION
register.

3.4.2 INTERRUPT-ON-CHANGE
Four of the PORTB pins are individually configurable
as an interrupt-on-change pin. Control bits IOCB<7:4>
enable or disable the interrupt function for each pin.
Refer to Register 3-6. The interrupt-on-change feature
is disabled on a Power-on Reset.
For enabled interrupt-on-change pins, the values are
compared with the old value latched on the last read of
PORTB. The ‘mismatch’ outputs of the last read are
OR’d together to set the PORTB Change Interrupt flag
bit (RBIF) in the INTCON register (Register 2-3).
This interrupt can wake the device from Sleep. The user,
in the Interrupt Service Routine, clears the interrupt by:
a) Any read or write of PORTB. This will end the
mismatch condition.
b) Clear the flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading or writing PORTB will end the mismatch con-
dition and allow flag bit RBIF to be cleared. The latch
holding the last read value is not affected by a MCLR
nor Brown-out Reset. After these Resets, the RBIF flag
will continue to be set if a mismatch is present.
Note: If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RBIF
interrupt flag may not get set. Furthermore,
since a read or write on a port affects all bits
of that port, care must be taken when using
multiple pins in Interrupt-on-change mode.
Changes on one pin may not be seen while
servicing changes on another pin.

 2007 Microchip Technology Inc. DS41250F-page 53

PIC16F913/914/916/917/946

REGISTER 3-4: PORTB: PORTB REGISTER

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 RB<7:0>: PORTB I/O Pin bits

1 = Port pin is >VIH min.
0 = Port pin is <VIL max.

REGISTER 3-5: TRISB: PORTB TRI-STATE REGISTER

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 TRISB<7:0>: PORTB Tri-State Control bits

1 = PORTB pin configured as an input (tri-stated)
0 = PORTB pin configured as an output

REGISTER 3-6: IOCB: PORTB INTERRUPT-ON-CHANGE REGISTER

R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0
IOCB7 IOCB6 IOCB5 IOCB4 — — — —
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-4 IOCB<7:4>: Interrupt-on-Change bits

1 = Interrupt-on-change enabled
0 = Interrupt-on-change disabled
bit 3-0 Unimplemented: Read as ‘0’

DS41250F-page 54  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946

REGISTER 3-7: WPUB: WEAK PULL-UP REGISTER

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 WPUB<7:0>: Weak Pull-up Register bits

1 = Pull-up enabled
0 = Pull-up disabled
Note 1: Global RBPU must be enabled for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is in Output mode (TRISx<7:0> = 0).

 2007 Microchip Technology Inc. DS41250F-page 55

PIC16F913/914/916/917/946
3.4.3 PIN DESCRIPTIONS AND 3.4.3.2 RB1/SEG1
DIAGRAMS Figure 3-9 shows the diagram for this pin. The RB1 pin
Each PORTB pin is multiplexed with other functions. The is configurable to function as one of the following:
pins and their combined functions are briefly described • a general purpose I/O
here. For specific information about individual functions
• an analog output for the LCD
such as the LCD or interrupts, refer to the appropriate
section in this data sheet. 3.4.3.3 RB2/SEG2
3.4.3.1 RB0/INT/SEG0 Figure 3-9 shows the diagram for this pin. The RB2 pin
is configurable to function as one of the following:
Figure 3-9 shows the diagram for this pin. The RB0 pin
is configurable to function as one of the following: • a general purpose I/O
• a general purpose I/O • an analog output for the LCD
• an external edge triggered interrupt 3.4.3.4 RB3/SEG3
• an analog output for the LCD
Figure 3-9 shows the diagram for this pin. The RB3 pin
is configurable to function as one of the following:
• a general purpose I/O
• an analog output for the LCD

FIGURE 3-9: BLOCK DIAGRAM OF RB<3:0>

WPUB<3:0> SE<3:0> VDD

VDD
RBPU P Weak
Pull-up
Data Bus
D Q
I/O Pin
WR PORTB
CK
VSS
Data Latch
D Q

WR TRISB
CK
TRIS Latch
SE<3:0> and LCDEN

TTL
Input Buffer
RD TRISB

RD PORTB
SE<3:0> and LCDEN
SEG<3:0>

Schmitt Trigger
INT(1) SE0 and LCDEN

Note 1: RB0 only.

DS41250F-page 56  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946
3.4.3.5 RB4/COM0
Figure 3-10 shows the diagram for this pin. The RB4
pin is configurable to function as one of the following:
• a general purpose I/O
• an analog output for the LCD

FIGURE 3-10: BLOCK DIAGRAM OF RB4

WPUB<4> LCDEN VDD

VDD
RBPU P Weak
Pull-up
Data Bus
D Q
I/O Pin
WR PORTB
CK
VSS
Data Latch
D Q

WR TRISB
CK
TRIS Latch
LCDEN

RD TRISB TTL
Input Buffer

RD PORTB

D Q

WR IOC
CK Q
Q D

RD IOC
EN Q1
Set RBIF
Interrupt-on- LCDEN
Change Q S
From other Q D
R RB<7:4> pins
EN RD PORTB
Write ‘0’ to RBIF

LCDEN
COM0

 2007 Microchip Technology Inc. DS41250F-page 57

PIC16F913/914/916/917/946
3.4.3.6 RB5/COM1
Figure 3-11 shows the diagram for this pin. The RB5
pin is configurable to function as one of the following:
• a general purpose I/O
• an analog output for the LCD

FIGURE 3-11: BLOCK DIAGRAM OF RB5

WPUB<5> LCDEN and LMUX<1:0>  00 VDD

VDD
RBPU P Weak
Pull-up
Data Bus
D Q
I/O Pin
WR PORTB
CK
VSS
Data Latch
D Q

WR TRISB
CK
TRIS Latch
LCDEN and LMUX<1:0>  00

RD TRISB TTL
Input Buffer

RD PORTB

D Q

WR IOC
CK Q
Q D

RD IOC LCDEN and

LMUX<1:0>  00 EN Q1
Set RBIF
Interrupt-on-
Change Q S
From other Q D
R RB<7:4> pins
EN RD PORTB
Write ‘0’ to RBIF

LCDEN and LMUX<1:0>  00

COM1

DS41250F-page 58  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946
3.4.3.7 RB6/ICSPCLK/ICDCK/SEG14
Figure 3-12 shows the diagram for this pin. The RB6
pin is configurable to function as one of the following:
• a general purpose I/O
• an In-Circuit Serial Programming™ clock
• an ICD clock input
• an analog output for the LCD

FIGURE 3-12: BLOCK DIAGRAM OF RB6

Program Mode/ICD Mode
WPUB<6> VDD
RBPU Weak
P Pull-up
SE14 and LCDEN VDD

Data Bus
D Q
I/O Pin
WR PORTB
CK
VSS
Data Latch
D Q

WR TRISB
CK SE14 and LCDEN
TRIS Latch TTL
Input Buffer

RD TRISB

RD PORTB

D Q

WR IOC
CK Q
Q D

RD IOC Q1
EN

Set RBIF
Interrupt-on- Q S Program Mode/ICD
Change
From other Q D
R RB<7:4> pins
EN RD PORTB
Write ‘0’ to RBIF

Schmitt Trigger
ICSPCLK Program Mode or ICD Mode or (SE14 and LCDEN)

SE14 and LCDEN

SEG14

 2007 Microchip Technology Inc. DS41250F-page 59

PIC16F913/914/916/917/946
3.4.3.8 RB7/ICSPDAT/ICDDAT/SEG13
Figure 3-13 shows the diagram for this pin. The RB7
pin is configurable to function as one of the following:
• a general purpose I/O
• an In-Circuit Serial Programming™ I/O
• an ICD data I/O
• an analog output for the LCD

FIGURE 3-13: BLOCK DIAGRAM OF RB7

PORT/Program Mode/ICD
ICSPDAT VDD
RBPU
SE13 and LCDEN
P Weak
Pull-up VDD

Data Bus 1
D Q
0 I/O Pin
WR PORTB CK
VSS
Data Latch
D Q

WR TRISB
CK
TRIS Latch 0
PGD DRVEN
1 TTL
Input Buffer
SE13 and LCDEN
RD TRISB

RD PORTB

D Q
Q D
WR IOC
CK Q EN Q1

RD IOC

Program
Mode/ICD
Set RBIF
Interrupt-on- Q S
Change
From other Q D
R RB<7:4> pins
EN RD PORTB
Write ‘0’ to RBIF

Schmitt Trigger
ICSPDAT/ICDDAT Program Mode or ICD Mode or (SE13 and LCDEN)

SE13 and LCDEN

SEG13

DS41250F-page 60  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946
TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Value on Value on all
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR other Resets

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x
IOCB IOCB7 IOCB6 IOCB5 IOCB4 — — — — 0000 ---- 0000 ----
LCDCON LCDEN SLPEN WERR VLCDEN CS1 CS0 LMUX1 LMUX0 0001 0011 0001 0011
LCDSE0 SE7 SE6 SE5 SE4 SE3 SE2 SE1 SE0 0000 0000 uuuu uuuu
LCDSE1 SE15 SE14 SE13 SE12 SE11 SE10 SE9 SE8 0000 0000 uuuu uuuu
OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111
WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTB.
Note 1: This register is only initialized by a POR or BOR reset and is unchanged by other Resets.
2: Configuration Word register bit DEBUG <12> is also associated with PORTB. See Register 16-1 for more details.

 2007 Microchip Technology Inc. DS41250F-page 61

PIC16F913/914/916/917/946
3.5 PORTC and TRISC Registers EXAMPLE 3-3: INITIALIZING PORTC
PORTC is an 8-bit bidirectional port. PORTC is BANKSEL PORTC ;
CLRF PORTC ;Init PORTC
multiplexed with several peripheral functions. PORTC
BANKSEL TRISC ;
pins have Schmitt Trigger input buffers.
MOVLW 0FFh ;Set RC<7:0> as inputs
All PORTC pins have latch bits (PORTC register). MOVWF TRISC ;
They will modify the contents of the PORTC latch BANKSEL LCDCON ;
(when written); thus, modifying the value driven out on CLRF LCDCON ;Disable VLCD<3:1>
a pin if the corresponding TRISC bit is configured for ;inputs on RC<2:0>
output.

REGISTER 3-8: PORTC: PORTC REGISTER

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 RC<7:0>: PORTC I/O Pin bits

1 = Port pin is >VIH min.
0 = Port pin is <VIL max.

REGISTER 3-9: TRISC: PORTC TRI-STATE REGISTER

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 TRISC<7:0>: PORTC Tri-State Control bits

1 = PORTC pin configured as an input (tri-stated)
0 = PORTC pin configured as an output

DS41250F-page 62  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946
3.5.1 PIN DESCRIPTIONS AND 3.5.1.3 RC2/VLCD3
DIAGRAMS Figure 3-16 shows the diagram for this pin. The RC2
Each PORTC pin is multiplexed with other functions. The pin is configurable to function as one of the following:
pins and their combined functions are briefly described • a general purpose I/O
here. For specific information about individual functions
• an analog input for the LCD bias voltage
such as the LCD or SSP, refer to the appropriate section
in this data sheet.

3.5.1.1 RC0/VLCD1
Figure 3-14 shows the diagram for this pin. The RC0
pin is configurable to function as one of the following:
• a general purpose I/O
• an analog input for the LCD bias voltage

3.5.1.2 RC1/VLCD2
Figure 3-15 shows the diagram for this pin. The RC1
pin is configurable to function as one of the following:
• a general purpose I/O
• an analog input for the LCD bias voltage

FIGURE 3-14: BLOCK DIAGRAM OF RC0

Data Bus VDD

D Q

WR PORTC
CK Q
Data Latch I/O Pin
D Q VSS

WR TRISC
CK Q
TRIS Latch

(VLCDEN and LMUX<1:0>  00)

RD TRISC
Schmitt
Trigger

RD PORTC

(LCDEN and LMUX<1:0>  00)

VLCD1

 2007 Microchip Technology Inc. DS41250F-page 63

PIC16F913/914/916/917/946
FIGURE 3-15: BLOCK DIAGRAM OF RC1

Data Bus VDD

D Q

WR PORTC
CK Q
Data Latch I/O Pin
D Q VSS

WR TRISC Q
CK
TRIS Latch

(VLCDEN and LMUX<1:0>  00)

RD TRISC
Schmitt
Trigger

RD PORTC

(LCDEN and LMUX<1:0>  00)

VLCD2

FIGURE 3-16: BLOCK DIAGRAM OF RC2

Data Bus VDD

D Q

WR PORTC
CK Q
Data Latch I/O Pin
D Q VSS

WR TRISC
CK Q
TRIS Latch

VLCDEN
RD TRISC
Schmitt
Trigger

RD PORTC

LCDEN
VLCD3

DS41250F-page 64  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946
3.5.1.4 RC3/SEG6
Figure 3-17 shows the diagram for this pin. The RC3
pin is configurable to function as one of the following:
• a general purpose I/O
• an analog output for the LCD

FIGURE 3-17: BLOCK DIAGRAM OF RC3

Data Bus VDD

D Q

WR PORTC
CK Q
Data Latch I/O Pin
D Q VSS

WR TRISC
CK Q
TRIS Latch

SE6 and LCDEN

RD TRISC
Schmitt
Trigger

RD PORTC

SE6 and LCDEN

SEG6 and LCDEN

 2007 Microchip Technology Inc. DS41250F-page 65

PIC16F913/914/916/917/946
3.5.1.5 RC4/T1G/SDO/SEG11
Figure 3-18 shows the diagram for this pin. The RC4pin
is configurable to function as one of the following:
• a general purpose I/O
• a Timer1 gate input
• a serial data output
• an analog output for the LCD

FIGURE 3-18: BLOCK DIAGRAM OF RC4

PO RT/SDO Select

SDO
0
Data Bus D Q 1
VDD
WR PORTC
CK Q
Data Latch

D Q I/O Pin
VSS
WR TRISC
CK Q
TRIS Latch

RD TRISC

SE11 and LCDEN

Schmitt
Trigger

RD PORTC

Timer1 Gate
SE11 and LCDEN
SEG11

DS41250F-page 66  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946
3.5.1.6 RC5/T1CKI/CCP1/SEG10
Figure 3-19 shows the diagram for this pin. The RC5
pin is configurable to function as one of the following:
• a general purpose I/O
• a Timer1 clock input
• a Capture input, Compare output or PWM output
• an analog output for the LCD

FIGURE 3-19: BLOCK DIAGRAM OF RC5

(PORT/CCP1 Sele ct) and CCPMX

CCP1 Data Out

0
Data Bus D Q 1
VDD
WR PORTC
CK Q
Data Latch
D Q I/O Pin
VSS
WR TRISC
CK Q
TRIS Latch

RD TRISC

SE10 and LCDEN

Schmitt
Trigger

RD PORTC

Timer1 Clock Input

SE10 and LCDEN

SEG10

 2007 Microchip Technology Inc. DS41250F-page 67

PIC16F913/914/916/917/946
3.5.1.7 RC6/TX/CK/SCK/SCL/SEG9
Figure 3-20 shows the diagram for this pin. The RC6
pin is configurable to function as one of the following:
• a general purpose I/O
• an asynchronous serial output
• a synchronous clock I/O
• a SPI clock I/O
• an I2C data I/O
• an analog output for the LCD

FIGURE 3-20: BLOCK DIAGRAM OF RC6

PORT/USART/SSP Mode Select(1)

I2C™ Data Out

TX/CK Data Out

SCK Data Out

Data Bus D Q
VDD
WR PORTC
CK Q
Data Latch
D Q I/O Pin
VSS
WR TRISC
CK Q
TRIS Latch

RD TRISC
USART or I2C™ Drive

SE9 and LCDEN

Schmitt
Trigger

RD PORTC

CK/SCL/SCK Input
SE9 and LCDEN
SEG9

Note 1: If all three data output sources are enabled, the following priority order will be used:
• USART data (highest)
• SSP data
• PORT data (lowest)

DS41250F-page 68  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946
3.5.1.8 RC7/RX/DT/SDI/SDA/SEG8
Figure 3-21 shows the diagram for this pin. The RC7
pin is configurable to function as one of the following:
• a general purpose I/O
• an asynchronous serial input
• a synchronous serial data I/O
• a SPI data input
• an I2C data I/O
• an analog output for the LCD

FIGURE 3-21: BLOCK DIAGRAM OF RC7

USART/I2C™ Mode Select(1)

DT Data Out

I2C™ Data Out

PORT/(USART or I2C™) Select

VDD
0

1
I/O Pin
Data Bus
D Q VSS
WR PORTC
CK Q
Data Latch
D Q
WR TRISC
CK Q
TRIS Latch
SE8 and LCDEN
Schmitt
RD TRISC
I2C™ Drive Trigger
or SCEN Drive

RD PORTC

RX/SDI Input
SE8 and LCDEN
SEG8

Note 1: If all three data output sources are enabled, the following priority order will be used:
• USART data (highest)
• SSP data
• PORT data (lowest)

 2007 Microchip Technology Inc. DS41250F-page 69

PIC16F913/914/916/917/946
TABLE 3-3: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Value on Value on all
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR other Resets

CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
LCDCON LCDEN SLPEN WERR VLCDEN CS1 CS0 LMUX1 LMUX0 0001 0011 0001 0011
LCDSE0 SE7 SE6 SE5 SE4 SE3 SE2 SE1 SE0 0000 0000 uuuu uuuu
LCDSE1 SE15 SE14 SE13 SE12 SE11 SE10 SE9 SE8 0000 0000 uuuu uuuu
PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC.

DS41250F-page 70  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946
3.6 PORTD and TRISD Registers EXAMPLE 3-4: INITIALIZING PORTD
PORTD is an 8-bit port with Schmitt Trigger input buffers. BANKSEL PORTD ;
CLRF PORTD ;Init PORTD
Each pin is individually configured as an input or output.
BANKSEL TRISD ;
PORTD is only available on the PIC16F914/917 and
MOVLW 0FF ;Set RD<7:0> as inputs
PIC16F946. ;
MOVWF TRISD

REGISTER 3-10: PORTD: PORTD REGISTER

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 RD<7:0>: PORTD I/O Pin bits

1 = Port pin is >VIH min.
0 = Port pin is <VIL max.

REGISTER 3-11: TRISD: PORTD TRI-STATE REGISTER

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 TRISD<7:0>: PORTD Tri-State Control bits

1 = PORTD pin configured as an input (tri-stated)
0 = PORTD pin configured as an output

 2007 Microchip Technology Inc. DS41250F-page 71

PIC16F913/914/916/917/946
3.6.1 PIN DESCRIPTIONS AND 3.6.1.7 RD6/SEG19
DIAGRAMS Figure 3-25 shows the diagram for this pin. The RD6
Each PORTD pin is multiplexed with other functions. The pin is configurable to function as one of the following:
pins and their combined functions are briefly described • a general purpose I/O
here. For specific information about individual functions
• an analog output for the LCD
such as the Comparator or the ADC, refer to the
appropriate section in this data sheet. 3.6.1.8 RD7/SEG20
3.6.1.1 RD0/COM3 Figure 3-25 shows the diagram for this pin. The RD7
pin is configurable to function as one of the following:
Figure 3-22 shows the diagram for this pin. The RD0
pin is configurable to function as one of the following: • a general purpose I/O
• a general purpose I/O • an analog output for the LCD
• an analog output for the LCD

3.6.1.2 RD1
Figure 3-23 shows the diagram for this pin. The RD1
pin is configurable to function as one of the following:
• a general purpose I/O

3.6.1.3 RD2/CCP2
Figure 3-24 shows the diagram for this pin. The RD2
pin is configurable to function as one of the following:
• a general purpose I/O
• a Capture input, Compare output or PWM output

3.6.1.4 RD3/SEG16
Figure 3-25 shows the diagram for this pin. The RD3
pin is configurable to function as one of the following:
• a general purpose I/O
• an analog output for the LCD

3.6.1.5 RD4/SEG17
Figure 3-25 shows the diagram for this pin. The RD4
pin is configurable to function as one of the following:
• a general purpose I/O
• an analog output for the LCD

3.6.1.6 RD5/SEG18
Figure 3-25 shows the diagram for this pin. The RD5
pin is configurable to function as one of the following:
• a general purpose I/O
• an analog output for the LCD

DS41250F-page 72  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946
FIGURE 3-22: BLOCK DIAGRAM OF RD0

VDD

Data Bus
D Q
WR PORTD
CK Q I/O Pin
VSS
Data Latch

D Q
WR TRISD
CK Q
TRIS Latch

RD TRISD LCDEN and LMUX<1:0> = 11

Schmitt
Trigger

RD PORTD

LCDEN and
COM3 LMUX<1:0> = 11

FIGURE 3-23: BLOCK DIAGRAM OF RD1

VDD

Data Bus
D Q
WR PORTD
CK Q RD1 Pin
Data Latch VSS

D Q
WR TRISD
CK Q
TRIS Latch

Schmitt
RD TRISD Trigger

RD PORTD

 2007 Microchip Technology Inc. DS41250F-page 73

PIC16F913/914/916/917/946
FIGURE 3-24: BLOCK DIAGRAM OF RD2

(PORT/CCP2 Select) and CCPMX

VDD
CCP2 Data Out
0

Data Bus 1
D Q I/O Pin
WR PORTD
CK Q VSS
Data Latch
D Q
WR TRISD
CK Q
TRIS Latch
Schmitt
Trigger
RD TRISD

RD PORTD
CCP2 Input

FIGURE 3-25: BLOCK DIAGRAM OF RD<7:3>

VDD

Data Bus
D Q
WR PORTD
CK Q I/O Pin
Data Latch VSS

D Q
WR TRISD
CK Q
TRIS Latch

SE<20:16> and LCDEN

Schmitt
RD TRISD Trigger

RD PORTD

SE<20:16> and LCDEN

SEG<20:16>

DS41250F-page 74  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946
TABLE 3-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD(1)
Value on Value on all
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR other Resets
CCP2CON(1) — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
LCDCON LCDEN SLPEN WERR VLCDEN CS1 CS0 LMUX1 LMUX0 0001 0011 0001 0011
LCDSE2(1) SE23 SE22 SE21 SE20 SE19 SE18 SE17 SE16 0000 0000 uuuu uuuu
(1)
PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu
TRISD(1) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTD.
Note 1: PIC16F914/917 and PIC16F946 only.

 2007 Microchip Technology Inc. DS41250F-page 75

PIC16F913/914/916/917/946
3.7 PORTE and TRISE Registers EXAMPLE 3-5: INITIALIZING PORTE
BANKSEL PORTE ;
PORTE is a 1-bit, 4-bit or 8-bit port with Schmitt Trigger
CLRF PORTE ;Init PORTE
input buffers. RE<7:4, 2:0> are individually configured as
BANKSEL TRISE ;
inputs or outputs and RE3 is only available as an input if MOVLW 0Fh ;Set RE<3:0> as inputs
MCLRE is ‘0’ in Configuration Word (Register 16-1). MOVWF TRISE ;
RE<2:0> are only available on the PIC16F914/917 and CLRF ANSEL ;Make RE<2:0> as I/O’s
PIC16F946. RE<7:4> are only available on the
PIC16F946.

REGISTER 3-12: PORTE: PORTE REGISTER

R/W-x R/W-x R/W-x R/W-x R-x R/W-x R/W-x R/W-x
RE7(1,3) RE6(1,3) RE5(1,3) RE4(1,3) RE3 RE2(2,4) RE1(2,4) RE0(2,4)
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 RE<7:0>: PORTE I/O Pin bits

1 = Port pin is >VIH min.
0 = Port pin is <VIL max.

Note 1: PIC16F946 only.

2: PIC16F914/917 and PIC16F946 only.
3: PIC16F91X, Read as ‘0’.
4: PIC16F913/916, Read as ‘0’.

REGISTER 3-13: TRISE: PORTE TRI-STATE REGISTER

R/W-1 R/W-1 R/W-1 R/W-1 R-1 R/W-1 R/W-1 R/W-1
(1,3) (1,3) (1,3) (1,3) (2,4) (2,4)
TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0(2,4)
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 TRISE<7:0>: PORTE Tri-State Control bits

1 = PORTE pin configured as an input (tri-stated)
0 = PORTE pin configured as an output

Note 1: PIC16F946 only.

2: PIC16F914/917 and PIC16F946 only.
3: PIC16F91X, Read as ‘0’.
4: PIC16F913/916, Read as ‘0’.

DS41250F-page 76  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946
3.7.1 PIN DESCRIPTIONS AND 3.7.1.7 RE6/SEG26(2)
DIAGRAMS
Figure 3-28 shows the diagram for this pin. The
Each PORTE pin is multiplexed with other functions. The RE6/SEG26 pin is configurable to function as one of
pins and their combined functions are briefly described the following:
here. For specific information about individual functions
• a general purpose I/O
such as the Comparator or the ADC, refer to the
appropriate section in this data sheet. • an analog output for the LCD

3.7.1.1 3.7.1.8 RE7/SEG27(2)

RE0/AN5/SEG21(1)
Figure 3-26 shows the diagram for this pin. The RE0 Figure 3-28 shows the diagram for this pin. The
pin is configurable to function as one of the following: RE7/SEG27 pin is configurable to function as one of
the following:
• a general purpose I/O
• a general purpose I/O
• an analog input for the ADC
• an analog output for the LCD
• an analog output for the LCD

3.7.1.2 RE1/AN6/SEG22(1) Note 1: Pin is available on the PIC16F914/917 and

Figure 3-26 shows the diagram for this pin. The RE1 PIC16F946 only.
pin is configurable to function as one of the following: 2: Pin is available on the PIC16F946 only.
• a general purpose I/O
• an analog input for the ADC
• an analog output for the LCD

3.7.1.3 RE2/AN7/SEG23(1)
Figure 3-26 shows the diagram for this pin. The RE2
pin is configurable to function as one of the following:
• a general purpose I/O
• an analog input for the ADC
• an analog output for the LCD

3.7.1.4 RE3/MCLR/VPP
Figure 3-27 shows the diagram for this pin. The RE3
pin is configurable to function as one of the following:
• a digital input only
• as Master Clear Reset with weak pull-up
• a programming voltage reference input

3.7.1.5 RE4/SEG24(2)
Figure 3-28 shows the diagram for this pin. The
RE4/SEG24 pin is configurable to function as one of
the following:
• a general purpose I/O
• an analog output for the LCD

3.7.1.6 RE5/SEG25(2)
Figure 3-28 shows the diagram for this pin. The
RE5/SEG25 pin is configurable to function as one of
the following:
• a general purpose I/O
• an analog output for the LCD

 2007 Microchip Technology Inc. DS41250F-page 77

PIC16F913/914/916/917/946
FIGURE 3-26: BLOCK DIAGRAM OF RE<2:0> (PIC16F914/917 AND PIC16F946 ONLY)
VDD

Data Bus
D Q
WR PORTE
CK Q I/O Pin
Data Latch VSS

D Q
WR TRISE
CK Q
TRIS Latch
Analog Mode or
SEG<23:21> and LCDEN
RD TRISE and LCDEN Schmitt
Trigger

RD PORTE

SEG<23:21> and LCDEN

SEG<23:21>

AN<7:5>

FIGURE 3-27: BLOCK DIAGRAM OF RE3

HV
Schmitt Trigger
MCLR circuit Buffer
MCLR Filter

Programming mode
HV Detect
Input Pin
MCLRE

VSS
Data Bus HV
Schmitt Trigger
Buffer
RD TRISE VSS

RD PORTE

DS41250F-page 78  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946
FIGURE 3-28: BLOCK DIAGRAM OF RE<7:4> (PIC16F946 ONLY)
VDD

Data Bus
D Q
WR PORTE
CK Q I/O Pin
Data Latch VSS

D Q
WR TRISE
CK Q
TRIS Latch
Analog Mode or
SEG<27:24> and LCDEN
RD TRISE Schmitt
Trigger

RD PORTE

SEG<27:24> and LCDEN

SEG<27:24>

AN<7:5>

 2007 Microchip Technology Inc. DS41250F-page 79

PIC16F913/914/916/917/946
TABLE 3-5: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Value on Value on all
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR other Resets

ADCON0 ADFM VCFG1 VCFG0 CHS2 CHS1 CHS0 GO/DONE ADON 0000 0000 0000 0000
ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111
LCDCON LCDEN SLPEN WERR VLCDEN CS1 CS0 LMUX1 LMUX0 0001 0011 0001 0011
LCDSE2(1,2) SE23 SE22 SE21 SE20 SE19 SE18 SE17 SE16 0000 0000 uuuu uuuu
LCDSE3(1, 3) SE31 SE30 SE29 SE28 SE27 SE26 SE25 SE24 0000 0000 uuuu uuuu
PORTE RE7(3) RE6(3) RE5(3) RE4(3) RE3 RE2(2) RE1(2) RE0(2) xxxx xxxx uuuu uuuu
TRISE TRISE7(3) TRISE6(3) TRISE5(3) TRISE4(3) TRISE3(4) TRISE2(2) TRISE1(2) TRISE0(2) 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC.
Note 1: This register is only initialized by a POR or BOR reset and is unchanged by other Resets.
2: PIC16F914/917 and PIC16F946 only.
3: PIC16F946 only.
4: Bit is read-only; TRISE = 1 always.

DS41250F-page 80  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946
3.8 PORTF and TRISF Registers EXAMPLE 3-6: INITIALIZING PORTF
PORTF is an 8-bit port with Schmitt Trigger input buff- BANKSEL PORTF ;
CLRF PORTF ;Init PORTF
ers. RF<7:0> are individually configured as inputs or
BANKSEL TRISF ;
outputs, depending on the state of the port direction. ;Set RF<7:0> as inputs
MOVLW 0FFh
The port bits are also multiplexed with LCD segment MOVWF TRISF ;
functions. PORTF is available on the PIC16F946 only.

REGISTER 3-14: PORTF: PORTF REGISTER(1)

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 RF<7:0>: PORTF I/O Pin bits

1 = Port pin is >VIH min.
0 = Port pin is <VIL max.

Note 1: PIC16F946 only.

REGISTER 3-15: TRISF: PORTF TRI-STATE REGISTER(1)

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 TRISF<7:0>: PORTF Tri-State Control bits

1 = PORTF pin configured as an input (tri-stated)
0 = PORTF pin configured as an output

Note 1: PIC16F946 only.

 2007 Microchip Technology Inc. DS41250F-page 81

PIC16F913/914/916/917/946
3.8.1 PIN DESCRIPTIONS AND 3.8.1.7 RF6/SEG30
DIAGRAMS Figure 3-29 shows the diagram for this pin. The RF6
Each PORTF pin is multiplexed with other functions. The pin is configurable to function as one of the following:
pins and their combined functions are briefly described • a general purpose I/O
here. For specific information about individual functions,
• an analog output for the LCD
refer to the appropriate section in this data sheet.
3.8.1.8 RF7/SEG31
3.8.1.1 RF0/SEG32
Figure 3-29 shows the diagram for this pin. The RF7
Figure 3-29 shows the diagram for this pin. The RF0
pin is configurable to function as one of the following:
pin is configurable to function as one of the following:
• a general purpose I/O
• a general purpose I/O
• an analog output for the LCD
• an analog output for the LCD

3.8.1.2 RF1/SEG33
Figure 3-29 shows the diagram for this pin. The RF1
pin is configurable to function as one of the following:
• a general purpose I/O
• an analog output for the LCD

3.8.1.3 RF2/SEG34
Figure 3-29 shows the diagram for this pin. The RF2
pin is configurable to function as one of the following:
• a general purpose I/O
• an analog output for the LCD

3.8.1.4 RF3/SEG35
Figure 3-29 shows the diagram for this pin. The RF3
pin is configurable to function as one of the following:
• a general purpose I/O
• an analog output for the LCD

3.8.1.5 RF4/SEG28
Figure 3-29 shows the diagram for this pin. The RF4
pin is configurable to function as one of the following:
• a general purpose I/O
• an analog output for the LCD

3.8.1.6 RF5/SEG29
Figure 3-29 shows the diagram for this pin. The RF5
pin is configurable to function as one of the following:
• a general purpose I/O
• an analog output for the LCD

DS41250F-page 82  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946
FIGURE 3-29: BLOCK DIAGRAM OF RF<7:0>

VDD

Data Bus
D Q
WR PORTF
CK Q I/O Pin
Data Latch VSS

D Q
WR TRISF
CK Q
TRIS Latch

RD TRISF SE<35:28> and LCDEN

Schmitt
Trigger

RD PORTF

SE<35:28> and LCDEN

SEG<35:28>

TABLE 3-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTF(1)

Value on all
Value on
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other
POR, BOR
Resets

LCDCON LCDEN SLPEN WERR VLCDEN CS1 CS0 LMUX1 LMUX0 0001 0011 0001 0011
(1)
LCDSE3 SE31 SE30 SE29 SE28 SE27 SE26 SE25 SE24 0000 0000 uuuu uuuu
LCDSE4(1) SE39 SE38 SE37 SE36 SE35 SE34 SE33 SE32 0000 0000 uuuu uuuu
(1)
PORTF RF7 RF6 RF5 RF4 RF3 RF2 RF1 RF0 xxxx xxxx uuuu uuuu
TRISF(1) TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTF.
Note 1: PIC16F946 only.

 2007 Microchip Technology Inc. DS41250F-page 83

PIC16F913/914/916/917/946
3.9 PORTG and TRISG Registers EXAMPLE 3-7: INITIALIZING PORTG
BANKSEL PORTG ;
PORTG is an 8-bit port with Schmitt Trigger input
CLRF PORTG ;Init PORTG
buffers. RG<5:0> are individually configured as inputs ;
BANKSEL TRISG
or outputs, depending on the state of the port direction. MOVLW 3Fh ;Set RG<5:0> as inputs
The port bits are also multiplexed with LCD segment MOVWF TRISG ;
functions. PORTG is available on the PIC16F946 only.

REGISTER 3-16: PORTG: PORTG REGISTER(1)

U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
— — RG5 RG4 RG3 RG2 RG1 RG0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 RG<5:0>: PORTG I/O Pin bits
1 = Port pin is >VIH min.
0 = Port pin is <VIL max.

Note 1: PIC16F946 only.

REGISTER 3-17: TRISG: PORTG TRI-STATE REGISTER(1)

U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
— — TRISG5 TRISG4 TRISG3 TRISG2 TRISG1 TRISG0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5-0 TRISF<5:0>: PORTG Tri-State Control bits
1 = PORTG pin configured as an input (tri-stated)
0 = PORTG pin configured as an output

Note 1: PIC16F946 only.

DS41250F-page 84  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946
3.9.1 PIN DESCRIPTIONS AND 3.9.1.4 RG3/SEG39
DIAGRAMS Figure 3-30 shows the diagram for this pin. The RG3
Each PORTG pin is multiplexed with other functions. The pin is configurable to function as one of the following:
pins and their combined functions are briefly described • a general purpose I/O
here. For specific information about individual functions,
• an analog output for the LCD
refer to the appropriate section in this data sheet.
3.9.1.5 RG4/SEG40
3.9.1.1 RG0/SEG36
Figure 3-30 shows the diagram for this pin. The RG4
Figure 3-30 shows the diagram for this pin. The RG0
pin is configurable to function as one of the following:
pin is configurable to function as one of the following:
• a general purpose I/O
• a general purpose I/O
• an analog output for the LCD
• an analog output for the LCD
3.9.1.6 RG5/SEG41
3.9.1.2 RG1/SEG37
Figure 3-30 shows the diagram for this pin. The RG5
Figure 3-30 shows the diagram for this pin. The RG1
pin is configurable to function as one of the following:
pin is configurable to function as one of the following:
• a general purpose I/O
• a general purpose I/O
• an analog output for the LCD
• an analog output for the LCD

3.9.1.3 RG2/SEG38
Figure 3-30 shows the diagram for this pin. The RG2
pin is configurable to function as one of the following:
• a general purpose I/O
• an analog output for the LCD

FIGURE 3-30: BLOCK DIAGRAM OF RG<5:0>

VDD

Data Bus
D Q
WR PORTG
CK Q I/O Pin
Data Latch VSS

D Q
WR TRISG
CK Q
TRIS Latch

RD TRISG SE<41:36> and LCDEN

Schmitt
Trigger

RD PORTG

SE<41:36> and LCDEN

SEG<41:36>

 2007 Microchip Technology Inc. DS41250F-page 85

PIC16F913/914/916/917/946
TABLE 3-7: SUMMARY OF REGISTERS ASSOCIATED WITH PORTG(1)
Value on all
Value on
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other
POR, BOR
Resets

LCDCON LCDEN SLPEN WERR VLCDEN CS1 CS0 LMUX1 LMUX0 0001 0011 0001 0011
LCDSE4(1) SE39 SE38 SE37 SE36 SE35 SE34 SE33 SE32 0000 0000 uuuu uuuu
LCDSE5(1) — — — — — — SE41 SE40 - ----- 00 - ----- uu
PORTG(1) — — RG5 RG4 RG3 RG2 RG1 RG0 --xx xxxx --uu uuuu
TRISG (1)
— — TRISG5 TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 --11 1111 --11 1111
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTG.
Note 1: PIC16F946 only.

DS41250F-page 86  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946
4.0 OSCILLATOR MODULE (WITH The Oscillator module can be configured in one of eight
clock modes.
FAIL-SAFE CLOCK MONITOR)
1. EC – External clock with I/O on OSC2/CLKOUT.
4.1 Overview 2. LP – 32 kHz Low-Power Crystal mode.
3. XT – Medium Gain Crystal or Ceramic
The Oscillator module has a wide variety of clock Resonator Oscillator mode.
sources and selection features that allow it to be used
4. HS – High Gain Crystal or Ceramic Resonator
in a wide range of applications while maximizing perfor-
mode.
mance and minimizing power consumption. Figure 4-1
illustrates a block diagram of the Oscillator module. 5. RC – External Resistor-Capacitor (RC) with
FOSC/4 output on OSC2/CLKOUT.
Clock sources can be configured from external
6. RCIO – External Resistor-Capacitor (RC) with
oscillators, quartz crystal resonators, ceramic resonators
I/O on OSC2/CLKOUT.
and Resistor-Capacitor (RC) circuits. In addition, the
system clock source can be configured from one of two 7. INTOSC – Internal oscillator with FOSC/4 output
internal oscillators, with a choice of speeds selectable via on OSC2 and I/O on OSC1/CLKIN.
software. Additional clock features include: 8. INTOSCIO – Internal oscillator with I/O on
OSC1/CLKIN and OSC2/CLKOUT.
• Selectable system clock source between external
or internal via software. Clock Source modes are configured by the FOSC<2:0>
• Two-Speed Start-up mode, which minimizes bits in the Configuration Word register (CONFIG). The
latency between external oscillator start-up and internal clock can be generated from two internal
code execution. oscillators. The HFINTOSC is a calibrated
high-frequency oscillator. The LFINTOSC is an
• Fail-Safe Clock Monitor (FSCM) designed to
uncalibrated low-frequency oscillator.
detect a failure of the external clock source (LP,
XT, HS, EC or RC modes) and switch
automatically to the internal oscillator.

FIGURE 4-1: SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM

FOSC<2:0>
(Configuration Word Register)
External Oscillator SCS<0>
(OSCCON Register)
OSC2

Sleep
LP, XT, HS, RC, RCIO, EC
OSC1
MUX

IRCF<2:0>
(OSCCON Register) System Clock
(CPU and Peripherals)
8 MHz
111 INTOSC
Internal Oscillator 4 MHz
110
2 MHz
101
Postscaler

1 MHz
100
MUX

HFINTOSC
500 kHz
8 MHz 011
250 kHz
010
125 kHz
001
LFINTOSC 31 kHz
000
31 kHz

Power-up Timer (PWRT)

Watchdog Timer (WDT)
Fail-Safe Clock Monitor (FSCM)

 2007 Microchip Technology Inc. DS41250F-page 87

PIC16F913/914/916/917/946
4.2 Oscillator Control
The Oscillator Control (OSCCON) register (Figure 4-1)
controls the system clock and frequency selection
options. The OSCCON register contains the following
bits:
• Frequency selection bits (IRCF)
• Frequency Status bits (HTS, LTS)
• System clock control bits (OSTS, SCS)

REGISTER 4-1: OSCCON: OSCILLATOR CONTROL REGISTER

U-0 R/W-1 R/W-1 R/W-0 R-1 R-0 R-0 R/W-0
— IRCF2 IRCF1 IRCF0 OSTS(1) HTS LTS SCS
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6-4 IRCF<2:0>: Internal Oscillator Frequency Select bits
111 = 8 MHz
110 = 4 MHz (default)
101 = 2 MHz
100 = 1 MHz
011 = 500 kHz
010 = 250 kHz
001 = 125 kHz
000 = 31 kHz (LFINTOSC)
bit 3 OSTS: Oscillator Start-up Time-out Status bit(1)
1 = Device is running from the clock defined by FOSC<2:0> of the Configuration Word
0 = Device is running from the internal oscillator (HFINTOSC or LFINTOSC)
bit 2 HTS: HFINTOSC Status bit (High Frequency – 8 MHz to 125 kHz)
1 = HFINTOSC is stable
0 = HFINTOSC is not stable
bit 1 LTS: LFINTOSC Stable bit (Low Frequency – 31 kHz)
1 = LFINTOSC is stable
0 = LFINTOSC is not stable
bit 0 SCS: System Clock Select bit
1 = Internal oscillator is used for system clock
0 = Clock source defined by FOSC<2:0> of the Configuration Word

Note 1: Bit resets to ‘0’ with Two-Speed Start-up and LP, XT or HS selected as the Oscillator mode or Fail-Safe
mode is enabled.

DS41250F-page 88  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946
4.3 Clock Source Modes 4.4 External Clock Modes
Clock Source modes can be classified as external or 4.4.1 OSCILLATOR START-UP TIMER (OST)
internal.
If the Oscillator module is configured for LP, XT or HS
• External Clock modes rely on external circuitry for modes, the Oscillator Start-up Timer (OST) counts
the clock source. Examples are: Oscillator mod- 1024 oscillations from OSC1. This occurs following a
ules (EC mode), quartz crystal resonators or Power-on Reset (POR) and when the Power-up Timer
ceramic resonators (LP, XT and HS modes) and (PWRT) has expired (if configured), or a wake-up from
Resistor-Capacitor (RC) mode circuits. Sleep. During this time, the program counter does not
• Internal clock sources are contained internally increment and program execution is suspended. The
within the Oscillator module. The Oscillator OST ensures that the oscillator circuit, using a quartz
module has two internal oscillators: the 8 MHz crystal resonator or ceramic resonator, has started and
High-Frequency Internal Oscillator (HFINTOSC) is providing a stable system clock to the Oscillator
and the 31 kHz Low-Frequency Internal Oscillator module. When switching between clock sources, a
(LFINTOSC). delay is required to allow the new clock to stabilize.
The system clock can be selected between external or These oscillator delays are shown in Table 4-1.
internal clock sources via the System Clock Select In order to minimize latency between external oscillator
(SCS) bit of the OSCCON register. See Section 4.6 start-up and code execution, the Two-Speed Clock
“Clock Switching” for additional information. Start-up mode can be selected (see Section 4.7
“Two-Speed Clock Start-up Mode”).

TABLE 4-1: OSCILLATOR DELAY EXAMPLES

Switch From Switch To Frequency Oscillator Delay
LFINTOSC 31 kHz
Sleep/POR Oscillator Warm-Up Delay (TWARM)
HFINTOSC 125 kHz to 8 MHz
Sleep/POR EC, RC DC – 20 MHz 2 instruction cycles
LFINTOSC (31 kHz) EC, RC DC – 20 MHz 1 cycle of each
Sleep/POR LP, XT, HS 32 kHz to 20 MHz 1024 Clock Cycles (OST)
LFINTOSC (31 kHz) HFINTOSC 125 kHz to 8 MHz 1 s (approx.)

4.4.2 EC MODE FIGURE 4-2: EXTERNAL CLOCK (EC)

The External Clock (EC) mode allows an externally MODE OPERATION
generated logic level as the system clock source. When
operating in this mode, an external clock source is Clock from OSC1/CLKIN
connected to the OSC1 input and the OSC2 is available Ext. System
for general purpose I/O. Figure 4-2 shows the pin PIC® MCU
connections for EC mode.
I/O
The Oscillator Start-up Timer (OST) is disabled when
EC mode is selected. Therefore, there is no delay in
operation after a Power-on Reset (POR) or wake-up Note 1: Alternate pin functions are listed in
from Sleep. Because the PIC® MCU design is fully Section 1.0 “Device Overview”.
static, stopping the external clock input will have the
effect of halting the device while leaving all data intact.
Upon restarting the external clock, the device will
resume operation as if no time had elapsed.

 2007 Microchip Technology Inc. DS41250F-page 89

PIC16F913/914/916/917/946
4.4.3 LP, XT, HS MODES Note 1: Quartz crystal characteristics vary according
The LP, XT and HS modes support the use of quartz to type, package and manufacturer. The
crystal resonators or ceramic resonators connected to user should consult the manufacturer data
OSC1 and OSC2 (Figure 4-3). The mode selects a low, sheets for specifications and recommended
medium or high gain setting of the internal application.
inverter-amplifier to support various resonator types
2: Always verify oscillator performance over
and speed.
the VDD and temperature range that is
LP Oscillator mode selects the lowest gain setting of the expected for the application.
internal inverter-amplifier. LP mode current consumption
3: For oscillator design assistance, reference
is the least of the three modes. This mode is designed to
the following Microchip Applications Notes:
drive only 32.768 kHz tuning-fork type crystals (watch
crystals). • AN826, “Crystal Oscillator Basics and
Crystal Selection for rfPIC® and PIC®
XT Oscillator mode selects the intermediate gain
Devices” (DS00826)
setting of the internal inverter-amplifier. XT mode
current consumption is the medium of the three modes. • AN849, “Basic PIC® Oscillator Design”
This mode is best suited to drive resonators with a (DS00849)
medium drive level specification. • AN943, “Practical PIC® Oscillator
Analysis and Design” (DS00943)
HS Oscillator mode selects the highest gain setting of the
internal inverter-amplifier. HS mode current consumption • AN949, “Making Your Oscillator Work”
is the highest of the three modes. This mode is best (DS00949)
suited for resonators that require a high drive setting.
FIGURE 4-4: CERAMIC RESONATOR
Figure 4-3 and Figure 4-4 show typical circuits for OPERATION
quartz crystal and ceramic resonators, respectively.
(XT OR HS MODE)
FIGURE 4-3: QUARTZ CRYSTAL
PIC® MCU
OPERATION (LP, XT OR
HS MODE) OSC1/CLKIN

PIC® MCU C1 To Internal

Logic

OSC1/CLKIN RP(3) RF(2) Sleep

C1 To Internal
Logic
Quartz C2 Ceramic OSC2/CLKOUT
RF(2) Sleep RS(1)
Crystal
Resonator

Note 1: A series resistor (RS) may be required for

C2 RS(1) OSC2/CLKOUT
ceramic resonators with low drive level.
2: The value of R F varies with the Oscillator mode
Note 1: A series resistor (RS) may be required for selected (typically between 2 M to 10 M.
quartz crystals with low drive level. 3: An additional parallel feedback resistor (R P)
2: The value of R F varies with the Oscillator mode may be required for proper ceramic resonator
selected (typically between 2 M to 10 M. operation.

DS41250F-page 90  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946
4.4.4 EXTERNAL RC MODES 4.5 Internal Clock Modes
The external Resistor-Capacitor (RC) modes support The Oscillator module has two independent, internal
the use of an external RC circuit. This allows the oscillators that can be configured or selected as the
designer maximum flexibility in frequency choice while system clock source.
keeping costs to a minimum when clock accuracy is not
required. There are two modes: RC and RCIO. 1. The HFINTOSC (High-Frequency Internal
Oscillator) is factory calibrated and operates at
In RC mode, the RC circuit connects to OSC1. 8 MHz. The frequency of the HFINTOSC can be
OSC2/CLKOUT outputs the RC oscillator frequency user-adjusted via software using the OSCTUNE
divided by 4. This signal may be used to provide a clock register (Register 4-2).
for external circuitry, synchronization, calibration, test
2. The LFINTOSC (Low-Frequency Internal
or other application requirements. Figure 4-5 shows
Oscillator) is uncalibrated and operates at 31 kHz.
the external RC mode connections.
The system clock speed can be selected via software
FIGURE 4-5: EXTERNAL RC MODES using the Internal Oscillator Frequency Select bits
IRCF<2:0> of the OSCCON register.
VDD The system clock can be selected between external or
PIC® MCU
internal clock sources via the System Clock Selection
REXT (SCS) bit of the OSCCON register. See Section 4.6
OSC1/CLKIN Internal “Clock Switching” for more information.
Clock
CEXT 4.5.1 INTOSC AND INTOSCIO MODES
The INTOSC and INTOSCIO modes configure the
VSS
internal oscillators as the system clock source when
the device is programmed using the oscillator selection
FOSC/4 or OSC2/CLKOUT(1)
I/O(2) or the FOSC<2:0> bits in the Configuration Word
register (CONFIG). See Section 16.0 “Special
Features of the CPU” for more information.
Recommended values: 10 k  REXT  100 k, <3V
3 k  REXT  100 k, 3-5V In INTOSC mode, OSC1/CLKIN is available for general
CEXT > 20 pF, 2-5V purpose I/O. OSC2/CLKOUT outputs the selected
internal oscillator frequency divided by 4. The CLKOUT
Note 1: Alternate pin functions are listed in
Section 1.0 “Device Overview”.
signal may be used to provide a clock for external
2: Output depends upon RC or RCIO clock mode.
circuitry, synchronization, calibration, test or other
application requirements.
In RCIO mode, the RC circuit is connected to OSC1. In INTOSCIO mode, OSC1/CLKIN and OSC2/CLKOUT
OSC2 becomes an additional general purpose I/O pin. are available for general purpose I/O.
The RC oscillator frequency is a function of the supply
voltage, the resistor (REXT) and capacitor (CEXT) values 4.5.2 HFINTOSC
and the operating temperature. Other factors affecting The High-Frequency Internal Oscillator (HFINTOSC) is
the oscillator frequency are: a factory calibrated 8 MHz internal clock source. The
• threshold voltage variation frequency of the HFINTOSC can be altered via
• component tolerances software using the OSCTUNE register (Register 4-2).
• packaging variations in capacitance The output of the HFINTOSC connects to a postscaler
The user also needs to take into account variation due and multiplexer (see Figure 4-1). One of seven
to tolerance of external RC components used. frequencies can be selected via software using the
IRCF<2:0> bits of the OSCCON register. See
Section 4.5.4 “Frequency Select Bits (IRCF)” for
more information.
The HFINTOSC is enabled by selecting any frequency
between 8 MHz and 125 kHz by setting the IRCF<2:0>
bits of the OSCCON register  000. Then, set the
System Clock Source (SCS) bit of the OSCCON
register to ‘1’ or enable Two-Speed Start-up by setting
the IESO bit in the Configuration Word register
(CONFIG) to ‘1’.
The HF Internal Oscillator (HTS) bit of the OSCCON
register indicates whether the HFINTOSC is stable or not.

 2007 Microchip Technology Inc. DS41250F-page 91

PIC16F913/914/916/917/946
4.5.2.1 OSCTUNE Register When the OSCTUNE register is modified, the
HFINTOSC frequency will begin shifting to the new
The HFINTOSC is factory calibrated but can be
frequency. Code execution continues during this shift.
adjusted in software by writing to the OSCTUNE
There is no indication that the shift has occurred.
register (Register 4-2).
OSCTUNE does not affect the LFINTOSC frequency.
The default value of the OSCTUNE register is ‘0’. The
Operation of features that depend on the LFINTOSC
value is a 5-bit two’s complement number.
clock source frequency, such as the Power-up Timer
(PWRT), Watchdog Timer (WDT), Fail-Safe Clock
Monitor (FSCM) and peripherals, are not affected by the
change in frequency.

REGISTER 4-2: OSCTUNE: OSCILLATOR TUNING REGISTER

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — TUN4 TUN3 TUN2 TUN1 TUN0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-5 Unimplemented: Read as ‘0’

bit 4-0 TUN<4:0>: Frequency Tuning bits
01111 = Maximum frequency
01110 =
•
•
•
00001 =
00000 = Oscillator module is running at the factory-calibrated frequency.
11111 =
•
•
•
10000 = Minimum frequency

DS41250F-page 92  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946
4.5.3 LFINTOSC 4.5.5 HF AND LF INTOSC CLOCK
The Low-Frequency Internal Oscillator (LFINTOSC) is SWITCH TIMING
an uncalibrated 31 kHz internal clock source. When switching between the LFINTOSC and the
The output of the LFINTOSC connects to a postscaler HFINTOSC, the new oscillator may already be shut
and multiplexer (see Figure 4-1). Select 31 kHz, via down to save power (see Figure 4-6). If this is the case,
software, using the IRCF<2:0> bits of the OSCCON there is a delay after the IRCF<2:0> bits of the
register. See Section 4.5.4 “Frequency Select Bits OSCCON register are modified before the frequency
(IRCF)” for more information. The LFINTOSC is also the selection takes place. The LTS and HTS bits of the
frequency for the Power-up Timer (PWRT), Watchdog OSCCON register will reflect the current active status
Timer (WDT) and Fail-Safe Clock Monitor (FSCM). of the LFINTOSC and HFINTOSC oscillators. The
timing of a frequency selection is as follows:
The LFINTOSC is enabled by selecting 31 kHz
(IRCF<2:0> bits of the OSCCON register = 000) as the 1. IRCF<2:0> bits of the OSCCON register are
system clock source (SCS bit of the OSCCON modified.
register = 1), or when any of the following are enabled: 2. If the new clock is shut down, a clock start-up
delay is started.
• Two-Speed Start-up IESO bit of the Configuration
Word register = 1 and IRCF<2:0> bits of the 3. Clock switch circuitry waits for a falling edge of
OSCCON register = 000 the current clock.
• Power-up Timer (PWRT) 4. CLKOUT is held low and the clock switch
circuitry waits for a rising edge in the new clock.
• Watchdog Timer (WDT)
5. CLKOUT is now connected with the new clock.
• Fail-Safe Clock Monitor (FSCM)
LTS and HTS bits of the OSCCON register are
The LF Internal Oscillator (LTS) bit of the OSCCON updated as required.
register indicates whether the LFINTOSC is stable or 6. Clock switch is complete.
not.
See Figure 4-1 for more details.
4.5.4 FREQUENCY SELECT BITS (IRCF) If the internal oscillator speed selected is between
The output of the 8 MHz HFINTOSC and 31 kHz 8 MHz and 125 kHz, there is no start-up delay before
LFINTOSC connects to a postscaler and multiplexer the new frequency is selected. This is because the old
(see Figure 4-1). The Internal Oscillator Frequency and new frequencies are derived from the HFINTOSC
Select bits IRCF<2:0> of the OSCCON register select via the postscaler and multiplexer.
the frequency output of the internal oscillators. One of Start-up delay specifications are located under the
eight frequencies can be selected via software: oscillator parameters of Section 19.0 “Electrical
• 8 MHz Specifications”.
• 4 MHz (Default after Reset)
• 2 MHz
• 1 MHz
• 500 kHz
• 250 kHz
• 125 kHz
• 31 kHz (LFINTOSC)
Note: Following any Reset, the IRCF<2:0> bits of
the OSCCON register are set to ‘110’ and
the frequency selection is set to 4 MHz.
The user can modify the IRCF bits to
select a different frequency.

 2007 Microchip Technology Inc. DS41250F-page 93

PIC16F913/914/916/917/946
FIGURE 4-6: INTERNAL OSCILLATOR SWITCH TIMING

HFINTOSC LFINTOSC (FSCM and WDT disabled)

HFINTOSC
Start-up Time 2-cycle Sync Running

LFINTOSC

IRCF <2:0> 0 0

System Clock

HFINTOSC LFINTOSC (Either FSCM or WDT enabled)

HFINTOSC
2-cycle Sync Running

LFINTOSC

IRCF <2:0> 0 0

System Clock

LFINTOSC HFINTOSC
LFINTOSC turns off unless WDT or FSCM is enabled
LFINTOSC
Start-up Time 2-cycle Sync Running

HFINTOSC

IRCF <2:0> 0 0

System Clock

DS41250F-page 94  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946
4.6 Clock Switching When the Oscillator module is configured for LP, XT or
HS modes, the Oscillator Start-up Timer (OST) is
The system clock source can be switched between enabled (see Section 4.4.1 “Oscillator Start-up Timer
external and internal clock sources via software using (OST)”). The OST will suspend program execution until
the System Clock Select (SCS) bit of the OSCCON 1024 oscillations are counted. Two-Speed Start-up
register. mode minimizes the delay in code execution by
operating from the internal oscillator as the OST is
4.6.1 SYSTEM CLOCK SELECT (SCS) BIT counting. When the OST count reaches 1024 and the
The System Clock Select (SCS) bit of the OSCCON OSTS bit of the OSCCON register is set, program
register selects the system clock source that is used for execution switches to the external oscillator.
the CPU and peripherals.
• When the SCS bit of the OSCCON register = 0,
4.7.1 TWO-SPEED START-UP MODE
the system clock source is determined by CONFIGURATION
configuration of the FOSC<2:0> bits in the Two-Speed Start-up mode is configured by the
Configuration Word register (CONFIG). following settings:
• When the SCS bit of the OSCCON register = 1, • IESO (of the Configuration Word register) = 1;
the system clock source is chosen by the internal Internal/External Switchover bit (Two-Speed
oscillator frequency selected by the IRCF<2:0> Start-up mode enabled).
bits of the OSCCON register. After a Reset, the
• SCS (of the OSCCON register) = 0.
SCS bit of the OSCCON register is always
cleared. • FOSC<2:0> bits in the Configuration Word
register (CONFIG) configured for LP, XT or HS
Note: Any automatic clock switch, which may mode.
occur from Two-Speed Start-up or Fail-Safe
Clock Monitor, does not update the SCS bit Two-Speed Start-up mode is entered after:
of the OSCCON register. The user can • Power-on Reset (POR) and, if enabled, after
monitor the OSTS bit of the OSCCON Power-up Timer (PWRT) has expired, or
register to determine the current system • Wake-up from Sleep.
clock source.
If the external clock oscillator is configured to be
4.6.2 OSCILLATOR START-UP TIME-OUT anything other than LP, XT or HS mode, then
STATUS (OSTS) BIT Two-Speed Start-up is disabled. This is because the
external clock oscillator does not require any
The Oscillator Start-up Time-out Status (OSTS) bit of stabilization time after POR or an exit from Sleep.
the OSCCON register indicates whether the system
clock is running from the external clock source, as 4.7.2 TWO-SPEED START-UP
defined by the FOSC<2:0> bits in the Configuration SEQUENCE
Word register (CONFIG), or from the internal clock
source. In particular, OSTS indicates that the Oscillator 1. Wake-up from Power-on Reset or Sleep.
Start-up Timer (OST) has timed out for LP, XT or HS 2. Instructions begin execution by the internal
modes. oscillator at the frequency set in the IRCF<2:0>
bits of the OSCCON register.
4.7 Two-Speed Clock Start-up Mode 3. OST enabled to count 1024 clock cycles.
4. OST timed out, wait for falling edge of the
Two-Speed Start-up mode provides additional power internal oscillator.
savings by minimizing the latency between external
5. OSTS is set.
oscillator start-up and code execution. In applications
that make heavy use of the Sleep mode, Two-Speed 6. System clock held low until the next falling edge
Start-up will remove the external oscillator start-up of new clock (LP, XT or HS mode).
time from the time spent awake and can reduce the 7. System clock is switched to external clock
overall power consumption of the device. source.
This mode allows the application to wake-up from
Sleep, perform a few instructions using the INTOSC
as the clock source and go back to Sleep without
waiting for the primary oscillator to become stable.
Note: Executing a SLEEP instruction will abort
the oscillator start-up time and will cause
the OSTS bit of the OSCCON register to
remain clear.

 2007 Microchip Technology Inc. DS41250F-page 95

PIC16F913/914/916/917/946
4.7.3 CHECKING TWO-SPEED CLOCK
STATUS
Checking the state of the OSTS bit of the OSCCON
register will confirm if the microcontroller is running
from the external clock source, as defined by the
FOSC<2:0> bits in the Configuration Word register
(CONFIG), or the internal oscillator.

FIGURE 4-7: TWO-SPEED START-UP

HFINTOSC

TOST

OSC1 0 1 1022 1023

OSC2

Program Counter PC - N PC PC + 1

System Clock

DS41250F-page 96  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946
4.8 Fail-Safe Clock Monitor 4.8.3 FAIL-SAFE CONDITION CLEARING
The Fail-Safe Clock Monitor (FSCM) allows the device The Fail-Safe condition is cleared after a Reset,
to continue operating should the external oscillator fail. executing a SLEEP instruction or toggling the SCS bit
The FSCM can detect oscillator failure any time after of the OSCCON register. When the SCS bit is toggled,
the Oscillator Start-up Timer (OST) has expired. The the OST is restarted. While the OST is running, the
FSCM is enabled by setting the FCMEN bit in the device continues to operate from the INTOSC selected
Configuration Word register (CONFIG). The FSCM is in OSCCON. When the OST times out, the Fail-Safe
applicable to all external oscillator modes (LP, XT, HS, condition is cleared and the device will be operating
EC, RC and RCIO). from the external clock source. The Fail-Safe condition
must be cleared before the OSFIF flag can be cleared.
FIGURE 4-8: FSCM BLOCK DIAGRAM
4.8.4 RESET OR WAKE-UP FROM SLEEP
Clock Monitor The FSCM is designed to detect an oscillator failure
Latch after the Oscillator Start-up Timer (OST) has expired.
External
S Q The OST is used after waking up from Sleep and after
Clock
any type of Reset. The OST is not used with the EC or
RC Clock modes so that the FSCM will be active as
LFINTOSC soon as the Reset or wake-up has completed. When
÷ 64 R Q the FSCM is enabled, the Two-Speed Start-up is also
Oscillator
enabled. Therefore, the device will always be executing
31 kHz 488 Hz code while the OST is operating.
(~32 s) (~2 ms)
Note: Due to the wide range of oscillator start-up
Sample Clock Clock times, the Fail-Safe circuit is not active
Failure during oscillator start-up (i.e., after exiting
Detected Reset or Sleep). After an appropriate
amount of time, the user should check the
OSTS bit of the OSCCON register to verify
4.8.1 FAIL-SAFE DETECTION
the oscillator start-up and that the system
The FSCM module detects a failed oscillator by clock switchover has successfully
comparing the external oscillator to the FSCM sample completed.
clock. The sample clock is generated by dividing the
LFINTOSC by 64. See Figure 4-8. Inside the fail
detector block is a latch. The external clock sets the
latch on each falling edge of the external clock. The
sample clock clears the latch on each rising edge of the
sample clock. A failure is detected when an entire
half-cycle of the sample clock elapses before the
primary clock goes low.

4.8.2 FAIL-SAFE OPERATION

When the external clock fails, the FSCM switches the
device clock to an internal clock source and sets the bit
flag OSFIF of the PIR2 register. Setting this flag will
generate an interrupt if the OSFIE bit of the PIE2
register is also set. The device firmware can then take
steps to mitigate the problems that may arise from a
failed clock. The system clock will continue to be
sourced from the internal clock source until the device
firmware successfully restarts the external oscillator
and switches back to external operation.
The internal clock source chosen by the FSCM is
determined by the IRCF<2:0> bits of the OSCCON
register. This allows the internal oscillator to be
configured before a failure occurs.

 2007 Microchip Technology Inc. DS41250F-page 97

PIC16F913/914/916/917/946
FIGURE 4-9: FSCM TIMING DIAGRAM

Sample Clock

System Oscillator
Clock Failure
Output

Clock Monitor Output

(Q)
Failure
Detected
OSCFIF

Test Test Test

Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.

TABLE 4-2: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

Value on
Value on all other
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR, BOR
Resets(1)

CONFIG(2) CPD CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0 — —

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x
OSCCON — IRCF2 IRCF1 IRCF0 OSTS HTS LTS SCS -110 x000 -110 x000
OSCTUNE — — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 ---u uuuu
PIE2 OSFIE C2IE C1IE LCDIE — LVDIE — CCP2IE 0000 -0-0 0000 -0-0
PIR2 OSFIF C2IF C1IF LCDIF — LVDIF — CCP2IF 0000 -0-0 0000 -0-0

T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by oscillators.
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
2: See Configuration Word register (CONFIG) for operation of all register bits.

DS41250F-page 98  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946
5.0 TIMER0 MODULE 5.1 Timer0 Operation
The Timer0 module is an 8-bit timer/counter with the When used as a timer, the Timer0 module can be used
following features: as either an 8-bit timer or an 8-bit counter.
• 8-bit timer/counter register (TMR0)
5.1.1 8-BIT TIMER MODE
• 8-bit prescaler (shared with Watchdog Timer)
When used as a timer, the Timer0 module will
• Programmable internal or external clock source
increment every instruction cycle (without prescaler).
• Programmable external clock edge selection Timer mode is selected by clearing the T0CS bit of the
• Interrupt on overflow OPTION register to ‘0’.
Figure 5-1 is a block diagram of the Timer0 module. When TMR0 is written, the increment is inhibited for
two instruction cycles immediately following the write.
Note: The value written to the TMR0 register can
be adjusted, in order to account for the two
instruction cycle delay when TMR0 is
written.

5.1.2 8-BIT COUNTER MODE

When used as a counter, the Timer0 module will
increment on every rising or falling edge of the T0CKI
pin. The incrementing edge is determined by the T0SE
bit of the Option register. Counter mode is selected by
setting the T0CS bit of the Option register to ‘1’.

FIGURE 5-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

FOSC/4
Data Bus
0
8
1
Sync
1 2 Tcy TMR0
T0CKI 0
pin 0
T0CS Set Flag bit T0IF
T0SE 8-bit
on Overflow
Prescaler PSA
1

8
WDTE PSA
SWDTEN
PS<2:0> 1
WDT
16-bit Time-out
Prescaler 0
16
31 kHz Watchdog
INTOSC Timer PSA
WDTPS<3:0>

Note 1: T0SE, T0CS, PSA, PS<2:0> are bits in the Option register.
2: SWDTEN and WDTPS<3:0> are bits in the WDTCON register.
3: WDTE bit is in the Configuration Word register.

 2007 Microchip Technology Inc. DS41250F-page 99

PIC16F913/914/916/917/946
5.1.3 SOFTWARE PROGRAMMABLE When changing the prescaler assignment from the
PRESCALER WDT to the Timer0 module, the following instruction
sequence must be executed (see Example 5-2).
A single software programmable prescaler is available
for use with either Timer0 or the Watchdog Timer
(WDT), but not both simultaneously. The prescaler EXAMPLE 5-2: CHANGING PRESCALER
assignment is controlled by the PSA bit of the Option (WDT  TIMER0)
register. To assign the prescaler to Timer0, the PSA bit CLRWDT ;Clear WDT and
must be cleared to a ‘0’. ;prescaler
BANKSEL OPTION_REG ;
There are 8 prescaler options for the Timer0 module
MOVLW b’11110000’ ;Mask TMR0 select and
ranging from 1:2 to 1:256. The prescale values are
ANDWF OPTION_REG,W ;prescaler bits
selectable via the PS<2:0> bits of the OPTION register. IORLW b’00000011’ ;Set prescale to 1:16
In order to have a 1:1 prescaler value for the Timer0 MOVWF OPTION_REG ;
module, the prescaler must be assigned to the WDT
module.
5.1.4 TIMER0 INTERRUPT
The prescaler is not readable or writable. When
assigned to the Timer0 module, all instructions writing to Timer0 will generate an interrupt when the TMR0
the TMR0 register will clear the prescaler. register overflows from FFh to 00h. The T0IF interrupt
flag bit of the INTCON register is set every time the
When the prescaler is assigned to WDT, a CLRWDT TMR0 register overflows, regardless of whether or not
instruction will clear the prescaler along with the WDT. the Timer0 interrupt is enabled. The T0IF bit must be
cleared in software. The Timer0 interrupt enable is the
5.1.3.1 Switching Prescaler Between T0IE bit of the INTCON register.
Timer0 and WDT Modules
Note: The Timer0 interrupt cannot wake the
As a result of having the prescaler assigned to either
processor from Sleep since the timer is
Timer0 or the WDT, it is possible to generate an
frozen during Sleep.
unintended device Reset when switching prescaler
values. When changing the prescaler assignment from 5.1.5 USING TIMER0 WITH AN
Timer0 to the WDT module, the instruction sequence
shown in Example 5-1, must be executed.
EXTERNAL CLOCK
When Timer0 is in Counter mode, the synchronization
EXAMPLE 5-1: CHANGING PRESCALER of the T0CKI input and the Timer0 register is accom-
(TIMER0  WDT) plished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, the
BANKSEL TMR0 ; high and low periods of the external clock source must
CLRWDT ;Clear WDT meet the timing requirements as shown in
CLRF TMR0 ;Clear TMR0 and Section 19.0 “Electrical Specifications”
;prescaler
BANKSEL OPTION_REG ;
BSF OPTION_REG,PSA ;Select WDT
CLRWDT ;
;
MOVLW b’11111000’ ;Mask prescaler
ANDWF OPTION_REG,W ;bits
IORLW b’00000101’ ;Set WDT prescaler
MOVWF OPTION_REG ;to 1:32

DS41250F-page  2007 Microchip Technology Inc.

100
 PIC16F913/914/916/917/946

REGISTER 5-1: OPTION_REG: OPTION REGISTER

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 RBPU: PORTB Pull-up Enable bit

1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual PORT latch values
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of INT pin
0 = Interrupt on falling edge of INT pin
bit 5 T0CS: TMR0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (FOSC/4)
bit 4 T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS<2:0>: Prescaler Rate Select bits
BIT VALUE TMR0 RATE WDT RATE

000 1:2 1:1

001 1:4 1:2
010 1:8 1:4
011 1 : 16 1:8
100 1 : 32 1 : 16
101 1 : 64 1 : 32
110 1 : 128 1 : 64
111 1 : 256 1 : 128

Note 1: A dedicated 16-bit WDT postscaler is available. See Section 16.4 “Watchdog Timer (WDT)” for more
information.

TABLE 5-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0

Value on
Value on
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other
POR, BOR
Resets
TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x
OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111
Legend: - = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the
Timer0 module.

 2007 Microchip Technology Inc. DS41250F-page 101

 PIC16F913/914/916/917/946
7.0 TIMER2 MODULE The TMR2 and PR2 registers are both fully readable
and writable. On any Reset, the TMR2 register is set to
The Timer2 module is an 8-bit timer with the following 00h and the PR2 register is set to FFh.
features:
Timer2 is turned on by setting the TMR2ON bit in the
• 8-bit timer register (TMR2) T2CON register to a ‘1’. Timer2 is turned off by clearing
• 8-bit period register (PR2) the TMR2ON bit to a ‘0’.
• Interrupt on TMR2 match with PR2 The Timer2 prescaler is controlled by the T2CKPS bits
• Software programmable prescaler (1:1, 1:4, 1:16) in the T2CON register. The Timer2 postscaler is
• Software programmable postscaler (1:1 to 1:16) controlled by the TOUTPS bits in the T2CON register.
The prescaler and postscaler counters are cleared
See Figure 7-1 for a block diagram of Timer2. when:

7.1 Timer2 Operation • A write to TMR2 occurs.

• A write to T2CON occurs.
The clock input to the Timer2 module is the system
• Any device Reset occurs (Power-on Reset, MCLR
instruction clock (FOSC/4). The clock is fed into the Reset, Watchdog Timer Reset, or Brown-out
Timer2 prescaler, which has prescale options of 1:1,
Reset).
1:4 or 1:16. The output of the prescaler is then used to
increment the TMR2 register. Note: TMR2 is not cleared when T2CON is
written.
The values of TMR2 and PR2 are constantly compared
to determine when they match. TMR2 will increment
from 00h until it matches the value in PR2. When a
match occurs, two things happen:
• TMR2 is reset to 00h on the next increment cycle.
• The Timer2 postscaler is incremented.
The match output of the Timer2/PR2 comparator is
then fed into the Timer2 postscaler. The postscaler has
postscale options of 1:1 to 1:16 inclusive. The output of
the Timer2 postscaler is used to set the TMR2IF
interrupt flag bit in the PIR1 register.

FIGURE 7-1: TIMER2 BLOCK DIAGRAM

Sets Flag
TMR2
bit TMR2IF
Output

Prescaler Reset
FOSC/4 TMR2
1:1, 1:4, 1:16

2 Postscaler
Comparator
EQ 1:1 to 1:16
T2CKPS<1:0>
PR2 4

TOUTPS<3:0>

 2007 Microchip Technology Inc. DS41250F-page 107

PIC16F913/914/916/917/946

REGISTER 7-1: T2CON: TIMER 2 CONTROL REGISTER

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6-3 TOUTPS<3:0>: Timer2 Output Postscaler Select bits
0000 = 1:1 Postscaler
0001 = 1:2 Postscaler
0010 = 1:3 Postscaler
0011 = 1:4 Postscaler
0100 = 1:5 Postscaler
0101 = 1:6 Postscaler
0110 = 1:7 Postscaler
0111 = 1:8 Postscaler
1000 = 1:9 Postscaler
1001 = 1:10 Postscaler
1010 = 1:11 Postscaler
1011 = 1:12 Postscaler
1100 = 1:13 Postscaler
1101 = 1:14 Postscaler
1110 = 1:15 Postscaler
1111 = 1:16 Postscaler
bit 2 TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16

TABLE 7-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2

Value on
Value on
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other
POR, BOR
Resets

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x
PIE1 EEIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
PIR1 EEIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PR2 Timer2 Module Period Register 1111 1111 1111 1111
TMR2 Holding Register for the 8-bit TMR2 Register 0000 0000 0000 0000
T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’. Shaded cells are not used for Timer2 module.

DS41250F-page  2007 Microchip Technology Inc.

108
 PIC16F913/914/916/917/946
12.0 ANALOG-TO-DIGITAL The ADC voltage reference is software selectable to be
either internally generated or externally supplied.
CONVERTER (ADC) MODULE
The ADC can generate an interrupt upon completion of
The Analog-to-Digital Converter (ADC) allows a conversion. This interrupt can be used to wake-up the
conversion of an analog input signal to a 10-bit binary device from Sleep.
representation of that signal. This device uses analog
inputs, which are multiplexed into a single sample and Figure 12-1 shows the block diagram of the ADC.
hold circuit. The output of the sample and hold is
connected to the input of the converter. The converter
generates a 10-bit binary result via successive
approximation and stores the conversion result into the
ADC result registers (ADRESL and ADRESH).

FIGURE 12-1: ADC BLOCK DIAGRAM

VDD

VCFG0 = 0
VREF+ VCFG0 = 1

RA0/AN0 000
RA1/AN1 001
ADC
RA2/AN2 010
GO/DONE 10
RA3/AN3 011
RA5/AN4 100
0 = Left Justify
(1) 101 ADFM
RE0/AN5 1 = Right Justify
RE1/AN6(1) 110 ADON 10
RE2/AN7(1) 111
VSS ADRESH ADRESL

CHS VCFG1 = 0
VREF- VCFG1 = 1

Note 1: These channels are only available on PIC16F914/917 and PIC16F946 devices.

 2007 Microchip Technology Inc. DS41250F-page 175

PIC16F913/914/916/917/946
12.1 ADC Configuration 12.1.3 ADC VOLTAGE REFERENCE
When configuring and using the ADC the following The VCFG bits of the ADCON0 register provide
functions must be considered: independent control of the positive and negative
voltage references. The positive voltage reference can
• Port configuration be either VDD or an external voltage source. Likewise,
• Channel selection the negative voltage reference can be either VSS or an
• ADC voltage reference selection external voltage source.
• ADC conversion clock source
12.1.4 CONVERSION CLOCK
• Interrupt control
• Results formatting The source of the conversion clock is software select-
able via the ADCS bits of the ADCON1 register. There
12.1.1 PORT CONFIGURATION are seven possible clock options:
The ADC can be used to convert both analog and digital • FOSC/2
signals. When converting analog signals, the I/O pin • FOSC/4
should be configured for analog by setting the associated • FOSC/8
TRIS and ANSEL bits. See the corresponding Port • FOSC/16
section for more information.
• FOSC/32
Note: Analog voltages on any pin that is defined • FOSC/64
as a digital input may cause the input • FRC (dedicated internal oscillator)
buffer to conduct excess current.
The time to complete one bit conversion is defined as
12.1.2 CHANNEL SELECTION TAD. One full 10-bit conversion requires 11 TAD periods
as shown in Figure 12-3.
The CHS bits of the ADCON0 register determine which
channel is connected to the sample and hold circuit. For correct conversion, the appropriate TAD specification
must be met. See A/D conversion requirements in
When changing channels, a delay is required before Section 19.0 “Electrical Specifications” for more
starting the next conversion. Refer to Section 12.2 information. Table 12-1 gives examples of appropriate
“ADC Operation” for more information. ADC clock selections.
Note: Unless using the FRC, any changes in the
system clock frequency will change the
ADC clock frequency, which may
adversely affect the ADC result.

DS41250F-page 176  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946
TABLE 12-1: ADC CLOCK PERIOD (T AD) VS. DEVICE OPERATING FREQUENCIES (VDD > 3.0V)
ADC Clock Period (TAD) Device Frequency (FOSC)
ADC Clock Source ADCS<2:0> 20 MHz 8 MHz 4 MHz 1 MHz
FOSC/2 000 100 ns (2)
250 ns (2)
500 ns (2)
2.0 s
FOSC/4 100 200 ns(2) 500 ns(2) 1.0 s(2) 4.0 s
FOSC/8 001 400 ns (2)
1.0 s (2)
2.0 s 8.0 s(3)
FOSC/16 101 800 ns (2)
2.0 s 4.0 s 16.0 s(3)
FOSC/32 010 1.6 s 4.0 s 8.0 s(3) 32.0 s(3)
FOSC/64 110 3.2 s 8.0 s (3)
16.0 s (3)
64.0 s(3)
FRC x11 2-6 s(1,4) 2-6 s(1,4) 2-6 s(1,4) 2-6 s(1,4)
Legend: Shaded cells are outside of recommended range.
Note 1: The FRC source has a typical TAD time of 4 s for VDD > 3.0V.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: When the device frequency is greater than 1 MHz, the FRC clock source is only recommended if the
conversion will be performed during Sleep.

FIGURE 12-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES

TCY to TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Conversion Starts
Holding Capacitor is Disconnected from Analog Input (typically 100 ns)

Set GO/DONE bit

ADRESH and ADRESL registers are loaded,
GO bit is cleared,
ADIF bit is set,
Holding capacitor is connected to analog input

12.1.5 INTERRUPTS
The ADC module allows for the ability to generate an
interrupt upon completion of an Analog-to-Digital
conversion. The ADC interrupt flag is the ADIF bit in the
PIR1 register. The ADC interrupt enable is the ADIE bit
in the PIE1 register. The ADIF bit must be cleared in
software.
Note: The ADIF bit is set at the completion of
every conversion, regardless of whether
or not the ADC interrupt is enabled.
This interrupt can be generated while the device is
operating or while in Sleep. If the device is in Sleep, the
interrupt will wake-up the device. Upon waking from
Sleep, the next instruction following the SLEEP
instruction is always executed. If the user is attempting
to wake-up from Sleep and resume in-line code
execution, the global interrupt must be disabled. If the
global interrupt is enabled, execution will switch to the
Interrupt Service Routine.
Please see Section 12.1.5 “Interrupts” for more
information.

 2007 Microchip Technology Inc. DS41250F-page 177

PIC16F913/914/916/917/946
12.1.6 RESULT FORMATTING
The 10-bit A/D conversion result can be supplied in two
formats, left justified or right justified. The ADFM bit of
the ADCON0 register controls the output format.
Figure 12-4 shows the two output formats.

FIGURE 12-3: 10-BIT A/D CONVERSION RESULT FORMAT

ADRESH ADRESL
(ADFM = 0) MSB LSB
bit 7 bit 0 bit 7 bit 0

10-bit A/D Result Unimplemented: Read as ‘0’

(ADFM = 1) MSB LSB

bit 7 bit 0 bit 7 bit 0

Unimplemented: Read as ‘0’ 10-bit A/D Result

12.2 ADC Operation 12.2.4 ADC OPERATION DURING SLEEP

The ADC module can operate during Sleep. This
12.2.1 STARTING A CONVERSION requires the ADC clock source to be set to the FRC
To enable the ADC module, the ADON bit of the option. When the FRC clock source is selected, the
ADCON0 register must be set to a ‘1’. Setting the ADC waits one additional instruction before starting the
GO/DONE bit of the ADCON0 register to a ‘1’ will start conversion. This allows the SLEEP instruction to be
the Analog-to-Digital conversion. executed, which can reduce system noise during the
conversion. If the ADC interrupt is enabled, the device
Note: The GO/DONE bit should not be set in the
will wake-up from Sleep when the conversion
same instruction that turns on the ADC.
completes. If the ADC interrupt is disabled, the ADC
Refer to Section 12.2.6 “A/D Conver-
module is turned off after the conversion completes,
sion Procedure”.
although the ADON bit remains set.
12.2.2 COMPLETION OF A CONVERSION When the ADC clock source is something other than
FRC, a SLEEP instruction causes the present conver-
When the conversion is complete, the ADC module will:
sion to be aborted and the ADC module is turned off,
• Clear the GO/DONE bit although the ADON bit remains set.
• Set the ADIF flag bit
• Update the ADRESH:ADRESL registers with new 12.2.5 SPECIAL EVENT TRIGGER
conversion result The CCP Special Event Trigger allows periodic ADC
measurements without software intervention. When
12.2.3 TERMINATING A CONVERSION this trigger occurs, the GO/DONE bit is set by hardware
If a conversion must be terminated before completion, and the Timer1 counter resets to zero.
the GO/DONE bit can be cleared in software. The Using the Special Event Trigger does not assure proper
ADRESH:ADRESL registers will not be updated with the ADC timing. It is the user’s responsibility to ensure that
partially complete Analog-to-Digital conversion sample. the ADC timing requirements are met.
Instead, the ADRESH:ADRESL register pair will retain
See Section 15.0 “Capture/Compare/PWM (CCP)
the value of the previous conversion. Additionally, a
Module” for more information.
2 TAD delay is required before another acquisition can be
initiated. Following this delay, an input acquisition is
automatically started on the selected channel.
Note: A device Reset forces all registers to their
Reset state. Thus, the ADC module is
turned off and any pending conversion is
terminated.

DS41250F-page 178  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946
12.2.6 A/D CONVERSION PROCEDURE EXAMPLE 12-1: A/D CONVERSION
This is an example procedure for using the ADC to ;This code block configures the ADC
perform an Analog-to-Digital conversion: ;for polling, Vdd reference, Frc clock
;and AN0 input.
1. Configure Port:
;
• Disable pin output driver (See TRIS register) ;Conversion start & polling for completion
• Configure pin as analog ; are included.
2. Configure the ADC module: ;
BANKSEL ADCON1 ;
• Select ADC conversion clock MOVLW B’01110000’ ;ADC Frc clock
• Configure voltage reference MOVWF ADCON1 ;
• Select ADC input channel BANKSEL TRISA ;
BSF TRISA,0 ;Set RA0 to input
• Select result format BANKSEL ANSEL ;
• Turn on ADC module BSF ANSEL,0 ;Set RA0 to analog
3. Configure ADC interrupt (optional): BANKSEL ADCON0 ;
MOVLW B’10000001’ ;Right justify,
• Clear ADC interrupt flag
MOVWF ADCON0 ;Vdd Vref, AN0, On
• Enable ADC interrupt CALL SampleTime ;Acquisiton delay
• Enable peripheral interrupt BSF ADCON0,GO ;Start conversion
• Enable global interrupt(1) BTFSC ADCON0,GO ;Is conversion done?
GOTO $-1 ;No, test again
4. Wait the required acquisition time(2). BANKSEL ADRESH ;
5. Start conversion by setting the GO/DONE bit. MOVF ADRESH,W ;Read upper 2 bits
MOVWF RESULTHI ;store in GPR space
6. Wait for ADC conversion to complete by one of
BANKSEL ADRESL ;
the following: MOVF ADRESL,W ;Read lower 8 bits
• Polling the GO/DONE bit MOVWF RESULTLO ;Store in GPR space
• Waiting for the ADC interrupt (interrupts
enabled)
12.2.7 ADC REGISTER DEFINITIONS
7. Read ADC Result
8. Clear the ADC interrupt flag (required if interrupt The following registers are used to control the opera-
is enabled). tion of the ADC.

Note 1: The global interrupt can be disabled if the

user is attempting to wake-up from Sleep
and resume in-line code execution.
2: See Section 12.3 “A/D Acquisition
Requirements”.

 2007 Microchip Technology Inc. DS41250F-page 179

PIC16F913/914/916/917/946

REGISTER 12-1: ADCON0: A/D CONTROL REGISTER 0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADFM VCFG1 VCFG0 CHS2 CHS1 CHS0 GO/DONE ADON
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 ADFM: A/D Conversion Result Format Select bit

1 = Right justified
0 = Left justified
bit 6 VCFG1: Voltage Reference bit
1 = VREF- pin
0 = VSS
bit 5 VCFG0: Voltage Reference bit
1 = VREF+ pin
0 = VSS
bit 4-2 CHS<2:0>: Analog Channel Select bits
000 = AN0
001 = AN1
010 = AN2
011 = AN3
100 = AN4
101 = AN5(1)
110 = AN6(1)
111 = AN7(1)
bit 1 GO/DONE: A/D Conversion Status bit
1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.
This bit is automatically cleared by hardware when the A/D conversion has completed.
0 = A/D conversion completed/not in progress
bit 0 ADON: ADC Enable bit
1 = ADC is enabled
0 = ADC is disabled and consumes no operating current

Note 1: Not available on 28-pin devices.

DS41250F-page 180  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946

REGISTER 12-2: ADCON1: A/D CONTROL REGISTER 1

U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0
— ADCS2 ADCS1 ADCS0 — — — —
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7 Unimplemented: Read as ‘0’

bit 6-4 ADCS<2:0>: A/D Conversion Clock Select bits
000 = FOSC/2
001 = FOSC/8
010 = FOSC/32
x11 = FRC (clock derived from a dedicated internal oscillator = 500 kHz max.)
100 = FOSC/4
101 = FOSC/16
110 = FOSC/64
bit 3-0 Unimplemented: Read as ‘0’

 2007 Microchip Technology Inc. DS41250F-page 181

PIC16F913/914/916/917/946

REGISTER 12-3: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
ADRES9 ADRES8 ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 ADRES<9:2>: ADC Result Register bits

Upper 8 bits of 10-bit conversion result

REGISTER 12-4: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
ADRES1 ADRES0 — — — — — —
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 ADRES<1:0>: ADC Result Register bits

Lower 2 bits of 10-bit conversion result
bit 5-0 Reserved: Do not use.

REGISTER 12-5: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
— — — — — — ADRES9 ADRES8
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-2 Reserved: Do not use.

bit 1-0 ADRES<9:8>: ADC Result Register bits
Upper 2 bits of 10-bit conversion result

REGISTER 12-6: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1

R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 ADRES1 ADRES0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-0 ADRES<7:0>: ADC Result Register bits

Lower 8 bits of 10-bit conversion result

DS41250F-page 182  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946
12.3 A/D Acquisition Requirements an A/D acquisition must be done before the conversion
can be started. To calculate the minimum acquisition
For the ADC to meet its specified accuracy, the charge time, Equation 12-1 may be used. This equation
holding capacitor (CHOLD) must be allowed to fully assumes that 1/2 LSb error is used (1024 steps for the
charge to the input channel voltage level. The Analog ADC). The 1/2 LSb error is the maximum error allowed
Input model is shown in Figure 12-4. The source for the ADC to meet its specified resolution.
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge the
capacitor CHOLD. The sampling switch (RSS) impedance
varies over the device voltage (VDD), see Figure 12-4.
The maximum recommended impedance for analog
sources is 10 k. As the source impedance is
decreased, the acquisition time may be decreased.
After the analog input channel is selected (or changed),

EQUATION 12-1: ACQUISITION TIME EXAMPLE

Assumptions: Temperature = 50°C and external impedance of 10k 5.0V V DD

TACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= T AMP + TC + TCOFF
= 2μs + TC + Temperature - 25°C0.05μs/°C

The value for TC can be approximated with the following equations:

VAPPLIED1 – ----------- ----

----------- = VCHOLD
1
;[1] VCHOLD charged to within 1/2 lsb
 
–TC
 --------- 
RC
V APPLIED 1 – e  = VCHOLD ;[2] VCHOLD charge response to VAPPLIED
 
–Tc
 ---------
V APPLIED 1 – e RC  = VAPPLIED 1 –-------------------------
1  ;combining [1] and [2]
   

Note: Where n = number of bits of the ADC.

Solving for TC:

TC = – C HOLD RIC + RSS + RS  ln(1/2047)

= –10pF1k + 7k + 10k ln(0.0004885)
= 1.37μs
Therefore:
TACQ = 2μS + 1.37μS + 50°C- 25°C0.05μS/°C
= 4.67μS

Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.

 2007 Microchip Technology Inc. DS41250F-page 183

PIC16F913/914/916/917/946
FIGURE 12-4: ANALOG INPUT MODEL
VDD
Sampling
Switch
VT = 0.6V
Rs ANx RIC  1k SS Rss

VA CPIN
VT = 0.6V CHOLD = 10 pF
5 pF
VSS/VREF-

6V
5V RSS
Legend: CPIN = Input Capacitance VDD 4V
VT = Threshold Voltage 3V
I LEAKAGE = Leakage current at the pin due to 2V
various junctions
RIC = Interconnect Resistance 5 6 7 8 9 10 11
SS = Sampling Switch Sampling Switch
CHOLD = Sample/Hold Capacitance (k)

Note 1: See Section 19.0 “Electrical Specifications”.

FIGURE 12-5: ADC TRANSFER FUNCTION

Full-Scale Range

3FFh
3FEh
3FDh
3FCh
ADC Output Code

1 LSB ideal
3FBh

Full-Scale
004h Transition

003h
002h
001h
000h Analog Input Voltage
1 LSB ideal

VSS/VREF- Zero-Scale VDD/VREF+

Transition

DS41250F-page 184  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946
TABLE 12-2: SUMMARY OF ASSOCIATED ADC REGISTERS
Value on
Value on
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other
POR, BOR
Resets

ADCON0 ADFM VCFG1 VCFG0 CHS2 CHS1 CHS0 GO/DONE ADON 0000 0000 0000 0000
ADCON1 — ADCS2 ADCS1 ADCS0 — — — — -000 ---- -000 ----
ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 1111 1111 1111 1111
ADRESH A/D Result Register High Byte xxxx xxxx uuuu uuuu
ADRESL A/D Result Register Low Byte xxxx xxxx uuuu uuuu
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x
LCDCON LCDEN SLPEN WERR VLCDEN CS1 CS0 LMUX1 LMUX0 0001 0011 0001 0011
LCDSE0 SE7 SE6 SE5 SE4 SE3 SE2 SE1 SE0 0000 0000 0000 0000
LCDSE1 SE15 SE14 SE13 SE12 SE11 SE10 SE9 SE8 0000 0000 0000 0000
LCDSE2(1) SE23 SE22 SE21 SE20 SE19 SE18 SE17 SE16 0000 0000 0000 0000
PIE1 EEIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
PIR1 EEIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx xxxx uuuu uuuu
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu
PORTE RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 xxxx xxxx uuuu uuuu
TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 ---- 1111 ----
TRISE TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, — = unimplemented read as ‘0’. Shaded cells are not used for ADC module.

 2007 Microchip Technology Inc. DS41250F-page 185

PIC16F913/914/916/917/946
NOTES:

DS41250F-page 186  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946
15.0 CAPTURE/COMPARE/PWM TABLE 15-1: CCP MODE – TIMER
(CCP) MODULE RESOURCES REQUIRED
CCP Mode Timer Resource
The Capture/Compare/PWM module is a peripheral
which allows the user to time and control different Capture Timer1
events. In Capture mode, the peripheral allows the Compare Timer1
timing of the duration of an event. The Compare mode
PWM Timer2
allows the user to trigger an external event when a
predetermined amount of time has expired. The PWM
mode can generate a Pulse-Width Modulated signal of
varying frequency and duty cycle.
The timer resources used by the module are shown in
Table 15-1.
Additional information on CCP modules is available in
the Application Note AN594, “Using the CCP Modules”
(DS00594).

TABLE 15-2: INTERACTION OF TWO CCP MODULES

CCPx Mode CCPy Mode Interaction
Capture Capture Same TMR1 time base
Capture Compare Same TMR1 time base
Compare Compare Same TMR1 time base
PWM PWM The PWMs will have the same frequency and update rate (TMR2 interrupt).
The rising edges will be aligned.
PWM Capture None
PWM Compare None

Note: CCPRx and CCPx throughout this

document refer to CCPR1 or CCPR2 and
CCP1 or CCP2, respectively.

 2007 Microchip Technology Inc. DS41250F-page 211

PIC16F913/914/916/917/946

REGISTER 15-1: CCPxCON: CCPx CONTROL REGISTER

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — CCPxX CCPxY CCP1M3 CCP1M2 CCP1M1 CCP1M0
bit 7 bit 0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 7-6 Unimplemented: Read as ‘0’

bit 5-4 CCPxX:CCPxY: PWM Least Significant bits
Capture mode:
Unused
Compare mode:
Unused
PWM mode:
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
bit 3-0 CCPxM<3:0>: CCP Mode Select bits
0000 = Capture/Compare/PWM off (resets CCP module)
0001 = Unused (reserved)
0010 = Unused (reserved)
0011 = Unused (reserved)
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, set output on match (CCPxIF bit is set)
1001 = Compare mode, clear output on match (CCPxIF bit is set)
1010 = Compare mode, generate software interrupt on match (CCPxIF bit is set, CCPx pin
is unaffected)
1011 = Compare mode, trigger special event (CCPxIF bit is set, TMR1 is reset and A/D
conversion is started if the ADC module is enabled. CCPx pin is unaffected.)
11xx = PWM mode.

DS41250F-page 212  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946
15.1 Capture Mode 15.1.2 TIMER1 MODE SELECTION
In Capture mode, CCPRxH:CCPRxL captures the Timer1 must be running in Timer mode or Synchronized
16-bit value of the TMR1 register when an event occurs Counter mode for the CCP module to use the capture
on pin CCPx. An event is defined as one of the feature. In Asynchronous Counter mode, the capture
following and is configured by the CCPxM<3:0> bits of operation may not work.
the CCPxCON register:
15.1.3 SOFTWARE INTERRUPT
• Every falling edge
When the Capture mode is changed, a false capture
• Every rising edge
interrupt may be generated. The user should keep the
• Every 4th rising edge CCPxIE interrupt enable bit of the PIEx register clear to
• Every 16th rising edge avoid false interrupts. Additionally, the user should
When a capture is made, the Interrupt Request Flag bit clear the CCPxIF interrupt flag bit of the PIRx register
CCPxIF of the PIRx register is set. The interrupt flag following any change in operating mode.
must be cleared in software. If another capture occurs
before the value in the CCPRxH, CCPRxL register pair 15.1.4 CCP PRESCALER
is read, the old captured value is overwritten by the new There are four prescaler settings specified by the
captured value (see Figure 15-1). CCPxM<3:0> bits of the CCPxCON register. Whenever
the CCP module is turned off, or the CCP module is not
15.1.1 CCPx PIN CONFIGURATION in Capture mode, the prescaler counter is cleared. Any
In Capture mode, the CCPx pin should be configured Reset will clear the prescaler counter.
as an input by setting the associated TRIS control bit. Switching from one capture prescaler to another does not
clear the prescaler and may generate a false interrupt. To
Note: If the CCPx pin is configured as an output,
avoid this unexpected operation, turn the module off by
a write to the port can cause a capture
clearing the CCPxCON register before changing the
condition.
prescaler (see Example 15-1).
FIGURE 15-1: CAPTURE MODE
EXAMPLE 15-1: CHANGING BETWEEN
OPERATION BLOCK
CAPTURE PRESCALERS
DIAGRAM
Set Flag bit CCPxIF
BANKSEL CCP1CON ;Set Bank bits to point
(PIRx register) ;to CCP1CON
Prescaler CCP1CON ;Turn CCP module off
CLRF
 1, 4, 16
MOVLW NEW_CAPT_PS ;Load the W reg with
CCPx CCPRxH CCPRxL ; the new prescaler
pin
; move value and CCP ON
and Capture MOVWF CCP1CON ;Load CCP1CON with this
Edge Detect Enable ; value
TMR1H TMR1L
CCPxCON<3:0>
System Clock (FOSC)

 2007 Microchip Technology Inc. DS41250F-page 213

PIC16F913/914/916/917/946
15.2 Compare Mode 15.2.2 TIMER1 MODE SELECTION
In Compare mode, the 16-bit CCPRx register value is In Compare mode, Timer1 must be running in either
constantly compared against the TMR1 register pair Timer mode or Synchronized Counter mode. The
value. When a match occurs, the CCPx module may: compare operation may not work in Asynchronous
Counter mode.
• Toggle the CCPx output.
• Set the CCPx output. 15.2.3 SOFTWARE INTERRUPT MODE
• Clear the CCPx output. When Generate Software Interrupt mode is chosen
• Generate a Special Event Trigger. (CCPxM<3:0> = 1010), the CCPx module does not
• Generate a Software Interrupt. assert control of the CCPx pin (see the CCPxCON
register).
The action on the pin is based on the value of the
CCPxM<3:0> control bits of the CCPxCON register. 15.2.4 SPECIAL EVENT TRIGGER
All Compare modes can generate an interrupt.
When Special Event Trigger mode is chosen
(CCPxM<3:0> = 1011), the CCPx module does the
FIGURE 15-2: COMPARE MODE following:
OPERATION BLOCK
• Resets Timer1
DIAGRAM
• Starts an ADC conversion if ADC is enabled
CCPxCON<3:0>
Mode Select The CCPx module does not assert control of the CCPx
pin in this mode (see the CCPxCON register).
Set CCPxIF Interrupt Flag
(PIRx) The Special Event Trigger output of the CCP occurs
CCPx 4 immediately upon a match between the TMR1H,
Pin CCPRxH CCPRxL
TMR1L register pair and the CCPRxH, CCPRxL
Q S Output register pair. The TMR1H, TMR1L register pair is not
Comparator
R Logic Match reset until the next rising edge of the Timer1 clock. This
TMR1H TMR1L allows the CCPRxH, CCPRxL register pair to
TRIS effectively provide a 16-bit programmable period
Output Enable
register for Timer1.
Special Event Trigger
Note 1: The Special Event Trigger from the CCP
Special Event Trigger will: module does not set interrupt flag bit
Clear TMR1H and TMR1L registers. TMRxIF of the PIR1 register.
NOT set interrupt flag bit TMR1IF of the PIR1 register.
Set the GO/DONE bit to start the ADC conversion. 2: Removing the match condition by
changing the contents of the CCPRxH
and CCPRxL register pair, between the
15.2.1 CCPx PIN CONFIGURATION clock edge that generates the Special
The user must configure the CCPx pin as an output by Event Trigger and the clock edge that
clearing the associated TRIS bit. generates the Timer1 Reset, will preclude
the Reset from occurring.
Note: Clearing the CCPxCON register will force
the CCPx compare output latch to the
default low level. This is not the PORT I/O
data latch.

DS41250F-page 214  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946
15.3 PWM Mode The PWM output (Figure 15-2) has a time base
(period) and a time that the output stays high (duty
The PWM mode generates a Pulse-Width Modulated cycle).
signal on the CCPx pin. The duty cycle, period and
resolution are determined by the following registers: FIGURE 15-4: CCP PWM OUTPUT
• PR2
Period
• T2CON
• CCPRxL Pulse Width
• CCPxCON TMR2 = PR2

In Pulse-Width Modulation (PWM) mode, the CCP TMR2 = CCPRxL:CCPxCON<5:4>

module produces up to a 10-bit resolution PWM output
TMR2 = 0
on the CCPx pin. Since the CCPx pin is multiplexed
with the PORT data latch, the TRIS for that pin must be
cleared to enable the CCPx pin output driver.
Note: Clearing the CCPxCON register will
relinquish CCPx control of the CCPx pin.
Figure 15-3 shows a simplified block diagram of PWM
operation.
Figure 15-4 shows a typical waveform of the PWM
signal.
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 15.3.7
“Setup for PWM Operation”.

FIGURE 15-3: SIMPLIFIED PWM BLOCK

DIAGRAM
CCPxCON<5:4>
Duty Cycle Registers

CCPRxL

CCPRxH(2) (Slave)
CCPx

Comparator R Q

(1) S
TMR2
TRIS

Comparator
Clear Timer2,
toggle CCPx pin and
latch duty cycle
PR2

Note 1: The 8-bit timer TMR2 register is concatenated

with the 2-bit internal system clock (F OSC), or
2 bits of the prescaler, to create the 10-bit time
base.
2: In PWM mode, CCPRxH is a read-only register.

 2007 Microchip Technology Inc. DS41250F-page 215

PIC16F913/914/916/917/946
15.3.1 PWM PERIOD EQUATION 15-2: PULSE WIDTH
The PWM period is specified by the PR2 register of
Timer2. The PWM period can be calculated using the Pulse Width = CCPRxL:CCPxCON<5:4> 
formula of Equation 15-1. TOSC  (TMR2 Prescale Value)

EQUATION 15-1: PWM PERIOD

EQUATION 15-3: DUTY CYCLE RATIO
PWM Period = PR2 + 1  4  TOSC 
(TMR2 Prescale Value) CCPRxL:CCPxCON<5:4>
Duty Cycle Ratio =
4PR2 + 1
Note: TOSC = 1/FOSC

When TMR2 is equal to PR2, the following three events The CCPRxH register and a 2-bit internal latch are
occur on the next increment cycle: used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
• TMR2 is cleared
The 8-bit timer TMR2 register is concatenated with
• The CCPx pin is set. (Exception: If the PWM duty
either the 2-bit internal system clock (FOSC), or 2 bits of
cycle = 0%, the pin will not be set.)
the prescaler, to create the 10-bit time base. The system
• The PWM duty cycle is latched from CCPRxL into clock is used if the Timer2 prescaler is set to 1:1.
CCPRxH.
When the 10-bit time base matches the CCPRxH and
2-bit latch, then the CCPx pin is cleared (see
Note: The Timer2 postscaler (see Section 7.1
Figure 15-3).
“Timer2 Operation”) is not used in the
determination of the PWM frequency.

15.3.2 PWM DUTY CYCLE

The PWM duty cycle is specified by writing a 10-bit value
to multiple registers: CCPRxL register and CCPx<1:0>
bits of the CCPxCON register. The CCPRxL contains
the eight MSbs and the CCPx<1:0> bits of the
CCPxCON register contain the two LSbs. CCPRxL and
CCPx<1:0> bits of the CCPxCON register can be written
to at any time. The duty cycle value is not latched into
CCPRxH until after the period completes (i.e., a match
between PR2 and TMR2 registers occurs). While using
the PWM, the CCPRxH register is read-only.
Equation 15-2 is used to calculate the PWM pulse
width.
Equation 15-3 is used to calculate the PWM duty cycle
ratio.

DS41250F-page 216  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946
15.3.3 PWM RESOLUTION EQUATION 15-4: PWM RESOLUTION
The resolution determines the number of available duty
cycles for a given period. For example, a 10-bit resolution log 4PR2 + 1  
Resolution = --------------------------------------- -- bits
will result in 1024 discrete duty cycles, whereas an 8-bit log 2
resolution will result in 256 discrete duty cycles.
The maximum PWM resolution is 10 bits when PR2 is
255. The resolution is a function of the PR2 register Note: If the pulse width value is greater than the
value as shown by Equation 15-4. period the assigned PWM pin(s) will
remain unchanged.

TABLE 15-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)

PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz
Timer Prescale (1, 4, 16) 16 4 1 1 1 1
PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17
Maximum Resolution (bits) 10 10 10 8 7 6.6

TABLE 15-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz)

PWM Frequency 1.22 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz
Timer Prescale (1, 4, 16) 16 4 1 1 1 1
PR2 Value 0x65 0x65 0x65 0x19 0x0C 0x09
Maximum Resolution (bits) 8 8 8 6 5 5

 2007 Microchip Technology Inc. DS41250F-page 217

PIC16F913/914/916/917/946
15.3.4 OPERATION IN SLEEP MODE 15.3.7 SETUP FOR PWM OPERATION
In Sleep mode, the TMR2 register will not increment The following steps should be taken when configuring
and the state of the module will not change. If the CCPx the CCP module for PWM operation:
pin is driving a value, it will continue to drive that value. 1. Disable the PWM pin (CCPx) output drivers by
When the device wakes up, TMR2 will continue from its setting the associated TRIS bit.
previous state.
2. Set the PWM period by loading the PR2 register.
15.3.5 CHANGES IN SYSTEM CLOCK 3. Configure the CCP module for the PWM mode
FREQUENCY by loading the CCPxCON register with the
appropriate values.
The PWM frequency is derived from the system clock
4. Set the PWM duty cycle by loading the CCPRxL
frequency. Any changes in the system clock frequency
register and CCPx bits of the CCPxCON register.
will result in changes to the PWM frequency. See
Section 4.0 “Oscillator Module (With Fail-Safe 5. Configure and start Timer2:
Clock Monitor)” for additional details. • Clear the TMR2IF interrupt flag bit of the
PIR1 register.
15.3.6 EFFECTS OF RESET • Set the Timer2 prescale value by loading the
Any Reset will force all ports to Input mode and the T2CKPS bits of the T2CON register.
CCP registers to their Reset states. • Enable Timer2 by setting the TMR2ON bit of
the T2CON register.
6. Enable PWM output after a new PWM cycle has
started:
• Wait until Timer2 overflows (TMR2IF bit of
the PIR1 register is set).
• Enable the CCPx pin output driver by
clearing the associated TRIS bit.

TABLE 15-5: SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND PWM
Value on
Value on
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other
POR, BOR
Resets
CCPxCON — — CCPxX CCPxY CCPxM3 CCPxM2 CCPxM1 CCPxM0 --00 0000 --00 0000
CCPRxL Capture/Compare/PWM Register X Low Byte xxxx xxxx uuuu uuuu
CCPRxH Capture/Compare/PWM Register X High Byte xxxx xxxx uuuu uuuu
CMCON1 — — — — — — T1GSS C2SYNC - ----- 10 ------- 10
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x
LCDCON LCDEN SLPEN WERR VLCDEN CS1 CS0 LMUX1 LMUX0 0001 0011 0001 0011
LCDSE1 SE15 SE14 SE13 SE12 SE11 SE10 SE9 SE8 0000 0000 0000 0000
PIE1 EEIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
PIE2 OSFIE C2IE C1IE LCDIE — LVDIE — CCP2IE 0000 -0-0 0000 -0-0
PIR1 EEIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
PIR2 OSFIF C2IF C1IF LCDIF — LVDIF — CCP2IF 0000 -0-0 0000 -0-0
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
T1CON T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu
T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
TMR2 Timer2 Module Register 0000 0000 0000 0000
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
TRISD(1) TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 1111 1111 1111 1111
Legend: - = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Capture, Compare
and PWM.
Note 1: PIC16F914/917 and PIC16F946 only.

DS41250F-page 218  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946
17.0 INSTRUCTION SET SUMMARY TABLE 17-1: OPCODE FIELD
DESCRIPTIONS
The PIC16F913/914/916/917/946 instruction set is
highly orthogonal and is comprised of three basic cate- Field Description
gories: f Register file address (0x00 to 0x7F)
• Byte-oriented operations W Working register (accumulator)
• Bit-oriented operations b Bit address within an 8-bit file register
• Literal and control operations k Literal field, constant data or label
Each PIC16 instruction is a 14-bit word divided into an x Don’t care location (= 0 or 1).
opcode, which specifies the instruction type and one or The assembler will generate code with x = 0.
more operands, which further specify the operation of It is the recommended form of use for
the instruction. The formats for each of the categories compatibility with all Microchip software tools.
is presented in Figure 17-1, while the various opcode
d Destination select; d = 0: store result in W ,
fields are summarized in Table 17-1.
d = 1: store result in file register f.
Table 17-2 lists the instructions recognized by the Default is d = 1.
MPASMTM assembler.
PC Program Counter
For byte-oriented instructions, ‘f’ represents a file TO Time-out bit
register designator and ‘d’ represents a destination
designator. The file register designator specifies which C Carry bit
file register is to be used by the instruction. DC Digit carry bit
The destination designator specifies where the result of Z Zero bit
the operation is to be placed. If ‘d’ is zero, the result is PD Power-down bit
placed in the W register. If ‘d’ is one, the result is placed
in the file register specified in the instruction. FIGURE 17-1: GENERAL FORMAT FOR
For bit-oriented instructions, ‘b’ represents a bit field INSTRUCTIONS
designator, which selects the bit affected by the
operation, while ‘f’ represents the address of the file in Byte-oriented file register operations
which the bit is located. 13 8 7 6 0
OPCODE d f (FILE #)
For literal and control operations, ‘k’ represents an
8-bit or 11-bit constant, or literal value. d = 0 for destination W
d = 1 for destination f
One instruction cycle consists of four oscillator periods; f = 7-bit file register address
for an oscillator frequency of 4 MHz, this gives a
nominal instruction execution time of 1 s. All Bit-oriented file register operations
instructions are executed within a single instruction 13 10 9 7 6 0
cycle, unless a conditional test is true, or the program OPCODE b (BIT #) f (FILE #)
counter is changed as a result of an instruction. When
this occurs, the execution takes two instruction cycles, b = 3-bit bit address
with the second cycle executed as a NOP. f = 7-bit file register address

All instruction examples use the format ‘0xhh’ to

Literal and control operations
represent a hexadecimal number, where ‘h’ signifies a
hexadecimal digit. General
13 8 7 0
17.1 Read-Modify-Write Operations OPCODE k (literal)

Any instruction that specifies a file register as part of k = 8-bit immediate value
the instruction performs a Read-Modify-Write (R-M-W)
operation. The register is read, the data is modified, CALL and GOTO instructions only
and the result is stored according to either the instruc- 13 11 10 0
tion, or the destination designator ‘d’. A read operation OPCODE k (literal)
is performed on a register even if the instruction writes
to that register. k = 11-bit immediate value

For example, a CLRF PORTA instruction will read

PORTA, clear all the data bits, then write the result back
to PORTA. This example would have the unintended
consequence of clearing the condition that set the RBIF
flag.

 2007 Microchip Technology Inc. DS41250F-page 241

PIC16F913/914/916/917/946
TABLE 17-2: PIC16F913/914/916/917/946 INSTRUCTION SET
Mnemonic, 14-Bit Opcode Status
Description Cycles Notes
Operands MSb LSb Affected

BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF f, d Add W and f 1 00 0111 dfff ffff C, DC, Z 1, 2
ANDWF f, d AND W with f 1 00 0101 dfff ffff Z 1, 2
CLRF f Clear f 1 00 0001 lfff ffff Z 2
CLRW – Clear W 1 00 0001 0xxx xxxx Z
COMF f, d Complement f 1 00 1001 dfff ffff Z 1, 2
DECF f, d Decrement f 1 00 0011 dfff ffff Z 1, 2
DECFSZ f, d Decrement f, Skip if 0 1(2) 00 1011 dfff ffff 1, 2, 3
INCF f, d Increment f 1 00 1010 dfff ffff Z 1, 2
INCFSZ f, d Increment f, Skip if 0 1(2) 00 1111 dfff ffff 1, 2, 3
IORWF f, d Inclusive OR W with f 1 00 0100 dfff ffff Z 1, 2
MOVF f, d Move f 1 00 1000 dfff ffff Z 1, 2
MOVWF f Move W to f 1 00 0000 lfff ffff
NOP – No Operation 1 00 0000 0xx0 0000
RLF f, d Rotate Left f through Carry 1 00 1101 dfff ffff C 1, 2
RRF f, d Rotate Right f through Carry 1 00 1100 dfff ffff C 1, 2
SUBWF f, d Subtract W from f 1 00 0010 dfff ffff C, DC, Z 1, 2
SWAPF f, d Swap nibbles in f 1 00 1110 dfff ffff 1, 2
XORWF f, d Exclusive OR W with f 1 00 0110 dfff ffff Z 1, 2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF f, b Bit Clear f 1 01 00bb bfff ffff 1, 2
BSF f, b Bit Set f 1 01 01bb bfff ffff 1, 2
BTFSC f, b Bit Test f, Skip if Clear 1 (2) 01 10bb bfff ffff 3
BTFSS f, b Bit Test f, Skip if Set 1 (2) 01 11bb bfff ffff 3
LITERAL AND CONTROL OPERATIONS
ADDLW k Add literal and W 1 11 111x kkkk kkkk C, DC, Z
ANDLW k AND literal with W 1 11 1001 kkkk kkkk Z
CALL k Call Subroutine 2 10 0kkk kkkk kkkk
CLRWDT – Clear Watchdog Timer 1 00 0000 0110 0100 TO, PD
GOTO k Go to address 2 10 1kkk kkkk kkkk
IORLW k Inclusive OR literal with W 1 11 1000 kkkk kkkk Z
MOVLW k Move literal to W 1 11 00xx kkkk kkkk
RETFIE – Return from interrupt 2 00 0000 0000 1001
RETLW k Return with literal in W 2 11 01xx kkkk kkkk
RETURN – Return from Subroutine 2 00 0000 0000 1000
SLEEP – Go into Standby mode 1 00 0000 0110 0011 TO, PD
SUBLW k Subtract W from literal 1 11 110x kkkk kkkk C, DC, Z
XORLW k Exclusive OR literal with W 1 11 1010 kkkk kkkk Z
Note 1: When an I/O register is modified as a function of itself (e.g., MOVF GPIO, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external
device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned to the Timer0 module.
3: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.

DS41250F-page 242  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946
17.2 Instruction Descriptions
ADDLW Add literal and W BCF Bit Clear f
Syntax: [ label ] ADDLW k Syntax: [ label ] BCF f,b
Operands: 0  k  255 Operands: 0  f  127
0b7
Operation: (W) + k  (W)
Status Affected: C, DC, Z Operation: 0  (f<b>)
Status Affected: None
Description: The contents of the W register
are added to the eight-bit literal ‘k’ Description: Bit ‘b’ in register ‘f’ is cleared.
and the result is placed in the
W register.

ADDWF Add W and f BSF Bit Set f

Syntax: [ label ] ADDWF f,d Syntax: [ label ] BSF f,b
Operands: 0  f  127 Operands: 0  f  127
d  0,1 0b7
Operation: (W) + (f)  (destination) Operation: 1  (f<b>)
Status Affected: C, DC, Z Status Affected: None
Description: Add the contents of the W register Description: Bit ‘b’ in register ‘f’ is set.
with register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W register. If
‘d’ is ‘1’, the result is stored back
in register ‘f’.

ANDLW AND literal with W BTFSC Bit Test f, Skip if Clear

Syntax: [ label ] ANDLW k Syntax: [ label ] BTFSC f,b
Operands: 0  k  255 Operands: 0  f  127
0b7
Operation: (W) .AND. (k)  (W)
Status Affected: Z Operation: skip if (f<b>) = 0
Status Affected: None
Description: The contents of W register are
AND’ed with the eight-bit literal Description: If bit ‘b’ in register ‘f’ is ‘1’, the next
‘k’. The result is placed in the W instruction is executed.
register. If bit ‘b’, in register ‘f’, is ‘0’, the
next instruction is discarded, and
a NOP is executed instead, making
this a 2-cycle instruction.
ANDWF AND W with f
Syntax: [ label ] ANDWF f,d
Operands: 0  f  127
d  0,1
Operation: (W) .AND. (f)  (destination)
Status Affected: Z
Description: AND the W register with register
‘f’. If ‘d’ is ‘0’, the result is stored in
the W register. If ‘d’ is ‘1’, the
result is stored back in register ‘f’.

 2007 Microchip Technology Inc. DS41250F-page 243

PIC16F913/914/916/917/946

BTFSS Bit Test f, Skip if Set CLRWDT Clear Watchdog Timer

Syntax: [ label ] BTFSS f,b Syntax: [ label ] CLRWDT
Operands: 0  f  127 Operands: None
0b<7 Operation: 00h  WDT
Operation: skip if (f<b>) = 1 0  WDT prescaler,
1  TO
Status Affected: None
1  PD
Description: If bit ‘b’ in register ‘f’ is ‘0’, the next
Status Affected: TO, PD
instruction is executed.
If bit ‘b’ is ‘1’, then the next Description: CLRWDT instruction resets the
instruction is discarded and a NOP Watchdog Timer. It also resets the
is executed instead, making this a prescaler of the WDT.
2-cycle instruction. Status bits TO and PD are set.

CALL Call Subroutine COMF Complement f

Syntax: [ label ] CALL k Syntax: [ label ] COMF f,d
Operands: 0  k  2047 Operands: 0  f  127
Operation: (PC)+ 1 TOS, d  [0,1]
k  PC<10:0>, Operation: (f)  (destination)
(PCLATH<4:3>)  PC<12:11>
Status Affected: Z
Status Affected: None
Description: The contents of register ‘f’ are
Description: Call Subroutine. First, return complemented. If ‘d’ is ‘0’, the
address (PC + 1) is pushed onto result is stored in W. If ‘d’ is ‘1’,
the stack. The eleven-bit the result is stored back in
immediate address is loaded into register ‘f’.
PC bits <10:0>. The upper bits of
the PC are loaded from PCLATH.
CALL is a two-cycle instruction.

CLRF Clear f DECF Decrement f

Syntax: [ label ] CLRF f Syntax: [ label ] DECF f,d
Operands: 0  f  127 Operands: 0  f  127
Operation: 00h  (f) d  [0,1]
1 Z Operation: (f) - 1  (destination)
Status Affected: Z Status Affected: Z
Description: The contents of register ‘f’ are Description: Decrement register ‘f’. If ‘d’ is ‘0’,
cleared and the Z bit is set. the result is stored in the W
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
CLRW Clear W
Syntax: [ label ] CLRW
Operands: None
Operation: 00h  (W)
1 Z
Status Affected: Z
Description: W register is cleared. Zero bit (Z)
is set.

DS41250F-page 244  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946

DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0

Syntax: [ label ] DECFSZ f,d Syntax: [ label ] INCFSZ f,d
Operands: 0  f  127 Operands: 0  f  127
d  [0,1] d  [0,1]
Operation: (f) - 1  (destination); Operation: (f) + 1  (destination),
skip if result = 0 skip if result = 0
Status Affected: None Status Affected: None
Description: The contents of register ‘f’ are Description: The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result incremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is is placed in the W register. If ‘d’ is
‘1’, the result is placed back in ‘1’, the result is placed back in
register ‘f’. register ‘f’.
If the result is ‘1’, the next If the result is ‘1’, the next
instruction is executed. If the instruction is executed. If the
result is ‘0’, then a NOP is result is ‘0’, a NOP is executed
executed instead, making it a instead, making it a 2-cycle
2-cycle instruction. instruction.

GOTO Unconditional Branch IORLW Inclusive OR literal with W

Syntax: [ label ] GOTO k Syntax: [ label ] IORLW k
Operands: 0  k  2047 Operands: 0  k  255
Operation: k  PC<10:0> Operation: (W) .OR. k  (W)
PCLATH<4:3>  PC<12:11> Status Affected: Z
Status Affected: None Description: The contents of the W register are
Description: GOTO is an unconditional branch. OR’ed with the eight-bit literal ‘k’.
The eleven-bit immediate value is The result is placed in the
loaded into PC bits <10:0>. The W register.
upper bits of PC are loaded from
PCLATH<4:3>. GOTO is a
two-cycle instruction.

INCF Increment f IORWF Inclusive OR W with f

Syntax: [ label ] INCF f,d Syntax: [ label ] IORWF f,d

Operands: 0  f  127 Operands: 0  f  127
d  [0,1] d  [0,1]
Operation: (f) + 1  (destination) Operation: (W) .OR. (f)  (destination)
Status Affected: Z Status Affected: Z
Description: The contents of register ‘f’ are Description: Inclusive OR the W register with
incremented. If ‘d’ is ‘0’, the result register ‘f’. If ‘d’ is ‘0’, the result is
is placed in the W register. If ‘d’ is placed in the W register. If ‘d’ is
‘1’, the result is placed back in ‘1’, the result is placed back in
register ‘f’. register ‘f’.

 2007 Microchip Technology Inc. DS41250F-page 245

PIC16F913/914/916/917/946

MOVF Move f MOVWF Move W to f

Syntax: [ label ] MOVF f,d Syntax: [ label ] MOVWF f
Operands: 0  f  127 Operands: 0  f  127
d  [0,1] Operation: (W)  (f)
Operation: (f)  (dest) Status Affected: None
Status Affected: Z Description: Move data from W register to
Description: The contents of register f is register ‘f’.
moved to a destination dependent Words: 1
upon the status of d. If d = 0,
Cycles: 1
destination is W register. If d = 1,
the destination is file register f Example: MOVW OPTION
itself. d = 1 is useful to test a file F
register since status flag Z is Before Instruction
affected. OPTION = 0xFF
Words: 1 W = 0x4F
Cycles: 1 After Instruction
OPTION = 0x4F
Example: MOVF FSR, 0 W = 0x4F
After Instruction
W = value in FSR
register
Z = 1

MOVLW Move literal to W NOP No Operation

Syntax: [ label ] MOVLW k Syntax: [ label ] NOP
Operands: 0  k  255 Operands: None
Operation: k  (W) Operation: No operation
Status Affected: None Status Affected: None
Description: The eight-bit literal ‘k’ is loaded into Description: No operation.
W register. The “don’t cares” will Words: 1
assemble as ‘0’s.
Cycles: 1
Words: 1
Example: NOP
Cycles: 1
Example: MOVLW 0x5A
After Instruction
W = 0x5A

DS41250F-page 246  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946

RETFIE Return from Interrupt RETLW Return with literal in W

Syntax: [ label ] RETFIE Syntax: [ label ] RETLW k
Operands: None Operands: 0  k  255
Operation: TOS  PC, Operation: k  (W);
1  GIE TOS  PC
Status Affected: None Status Affected: None
Description: Return from Interrupt. Stack is Description: The W register is loaded with the
POPed and Top-of-Stack (TOS) is eight bit literal ‘k’. The program
loaded in the PC. Interrupts are counter is loaded from the top of
enabled by setting Global the stack (the return address).
Interrupt Enable bit, GIE This is a two-cycle instruction.
(INTCON<7>). This is a two-cycle Words: 1
instruction.
Cycles: 2
Words: 1
Example: CALL TABLE;W contains
Cycles: 2 table
Example: RETFIE ;offset value
TABLE • ;W now has table value
After Interrupt •
PC = TOS •
GIE = 1 ADDWF PC ;W = offset
RETLW k1 ;Begin table
RETLW k2 ;
•
•
•
RETLW kn ; End of table

Before Instruction
W = 0x07
After Instruction
W = value of k8

RETURN Return from Subroutine

Syntax: [ label ] RETURN
Operands: None
Operation: TOS  PC
Status Affected: None
Description: Return from subroutine. The stack
is POPed and the top of the stack
(TOS) is loaded into the program
counter. This is a two-cycle
instruction.

 2007 Microchip Technology Inc. DS41250F-page 247

PIC16F913/914/916/917/946

RLF Rotate Left f through Carry SLEEP Enter Sleep mode

Syntax: [ label ] RLF f,d Syntax: [ label ] SLEEP
Operands: 0  f  127 Operands: None
d  [0,1] Operation: 00h  WDT,
Operation: See description below 0  WDT prescaler,
Status Affected: C 1  TO,
0  PD
Description: The contents of register ‘f’ are
rotated one bit to the left through Status Affected: TO, PD
the Carry flag. If ‘d’ is ‘0’, the Description: The power-down Status bit, PD is
result is placed in the W register. cleared. Time-out Status bit, TO
If ‘d’ is ‘1’, the result is stored is set. Watchdog Timer and its
back in register ‘f’. prescaler are cleared.
C Register f The processor is put into Sleep
mode with the oscillator stopped.
Words: 1
Cycles: 1
Example: RLF REG1,0
Before Instruction
REG1 = 1110 0110
C = 0
After Instruction
REG1 = 1110 0110
W = 1100 1100
C = 1

RRF Rotate Right f through Carry SUBLW Subtract W from literal

Syntax: [ label ] RRF f,d Syntax: [ label ] SUBLW k
Operands: 0  f  127 Operands: 0  k  255
d  [0,1] Operation: k - (W)  W)
Operation: See description below Status Affected: C, DC, Z
Status Affected: C Description: The W register is subtracted (2’s
Description: The contents of register ‘f’ are complement method) from the
rotated one bit to the right through eight-bit literal ‘k’. The result is
the Carry flag. If ‘d’ is ‘0’, the placed in the W register.
result is placed in the W register.
If ‘d’ is ‘1’, the result is placed C=0 Wk
back in register ‘f’. C=1 Wk
C Register f DC = 0 W<3:0>  k<3:0>
DC = 1 W<3:0>  k<3:0>

DS41250F-page 248  2007 Microchip Technology Inc.

 PIC16F913/914/916/917/946

SUBWF Subtract W from f XORLW Exclusive OR literal with W

Syntax: [ label ] SUBWF f,d Syntax: [ label ] XORLW k
Operands: 0  f  127 Operands: 0  k  255
d  [0,1]
Operation: (W) .XOR. k  W)
Operation: (f) - (W)  destination)
Status Affected: Z
Status Affected: C, DC, Z
Description: The contents of the W register
Description: Subtract (2’s complement method) are XOR’ed with the eight-bit
W register from register ‘f’. If ‘d’ is literal ‘k’. The result is placed in
‘0’, the result is stored in the W the W register.
register. If ‘d’ is ‘1’, the result is
stored back in register ‘f.

C=0 Wf
C=1 Wf
DC = 0 W<3:0>  f<3:0>
DC = 1 W<3:0>  f<3:0>

SWAPF Swap Nibbles in f XORWF Exclusive OR W with f

Syntax: [ label ] SWAPF f,d Syntax: [ label ] XORWF f,d
Operands: 0  f  127 Operands: 0  f  127
d  [0,1] d  [0,1]
Operation: (f<3:0>)  (destination<7:4>), Operation: (W) .XOR. (f)  destination)
(f<7:4>)  (destination<3:0>) Status Affected: Z
Status Affected: None Description: Exclusive OR the contents of the
Description: The upper and lower nibbles of W register with register ‘f’. If ‘d’ is
register ‘f’ are exchanged. If ‘d’ is ‘0’, the result is stored in the W
‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is
register. If ‘d’ is ‘1’, the result is stored back in register ‘f’.
placed in register ‘f’.

 2007 Microchip Technology Inc. DS41250F-page 249

PIC16F913/914/916/917/946
NOTES:

DS41250F-page 250  2007 Microchip Technology Inc.