STP40NF10

N-channel 100 V, 0.025 Ω, 50 A TO-220

low gate charge STripFET™ II Power MOSFET

Features
Order code VDSS RDS(on) max. ID
STP40NF10 100 V < 0.028 Ω 50 A

■ Exceptional dv/dt capability

■ Low gate charge 3
2
1
■ 100% avalanche tested
TO-220

Application
Switching applications

Description
Figure 1. Internal schematic diagram
This N-channel 100 V Power MOSFET is the
latest development of STMicroelectronics unique
"single feature size" strip-based process. The
resulting transistor shows extremely high packing
density for low on-resistance, rugged avalanche
characteristics and less critical alignment steps
allowing remarkable manufacturing
reproducibility.

Table 1. Device summary

Order code Marking Package Packaging

STP40NF10 P40NF10@ TO-220 Tube

November 2010 Doc ID 11096 Rev 5 1/12

www.st.com 12
Contents STP40NF10

Contents

1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) ............................ 6

3 Test circuit ................................................ 8

4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

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STP40NF10 Electrical ratings

1 Electrical ratings

Table 2. Absolute maximum ratings

Symbol Parameter Value Unit

VDS Drain-source voltage (VGS = 0) 100 V

VGS Gate- source voltage ±20 V
ID(1) Drain current (continuous) at TC = 25 °C 50 A
ID Drain current (continuous) at TC = 100 °C 35 A
(2)
IDM Drain current (pulsed) 200 A
PTOT Total dissipation at TC = 25 °C 150 W
Derating factor 1 W/°C
dv/dt(3) Peak diode recovery voltage slope 27 V/ns
EAS (4)
Single pulse avalanche energy 385 mJ
Tstg Storage temperature
- 55 to 175 °C
Tj Max. operating junction temperature
1. Limited by wire bonding
2. Pulse width limited by safe operating area
3. ISD ≤50 A, di/dt ≤600 A/µs, VDD ≤V(BR)DSS, Tj ≤TJMAX.
4. Starting Tj= 25 °C, ID= 50 A, VDD=25 V

Table 3. Thermal data

Symbol Parameter Value Unit

Rthj-case Thermal resistance junction-case max 1 °C/W

Rthj-a Thermal resistance junction-ambient max 62.5 °C/W
Tl Maximum lead temperature for soldering purpose 300 °C

Doc ID 11096 Rev 5 3/12

Electrical characteristics STP40NF10

2 Electrical characteristics

(TCASE = 25 °C unless otherwise specified)

Table 4. On/off states

Symbol Parameter Test conditions Min. Typ. Max. Unit

Drain-source
V(BR)DSS ID = 250 µA, VGS = 0 100 V
Breakdown voltage

Zero gate voltage VDS = Max rating 1 µA

IDSS
Drain current (VGS = 0) VDS=Max rating,TC=125°C 10 µA
Gate-body leakage
IGSS VGS = ±20 V ±100 nA
current (VDS = 0)
VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 2 3 4 V
Static drain-source on
RDS(on) VGS = 10 V, ID = 25 A 0.025 0.028 Ω
resistance

Table 5. Dynamic
Symbol Parameter Test conditions Min. Typ. Max. Unit

gfs (1) Forward transconductance VDS = 15 V, ID=28 A - 22 S

Ciss Input capacitance 2180 pF
Coss Output capacitance VDS = 25 V, f = 1 MHz, - 298 pF
VGS = 0
Reverse transfer
Crss 83.7 pF
capacitance
Qg Total gate charge VDD = 50 V, ID = 40 A, 46.5 62 nC
Qgs Gate-source charge VGS = 10V - 13.3 nC
Qgd Gate-drain charge (see Figure 15) 17.5 22.5 nC
1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5.

Table 6. Switching times

Symbol Parameter Test conditions Min. Typ. Max. Unit

td(on) Turn-on delay time 21 ns

VDD = 50V, ID = 25A - -
tr Rise time 46 ns
RG = 4.7Ω VGS = 10V
td(off) Turn-off-delay time (see Figure 14) 54 ns
- -
tf Fall time 13 ns

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STP40NF10 Electrical characteristics

Table 7. Source drain diode

Symbol Parameter Test conditions Min. Typ. Max Unit

ISD Source-drain current - 80 A

(1)
ISDM Source-drain current (pulsed) - 320 A
(2)
VSD Forward on voltage ISD = 50A, VGS = 0 - 1.5 V
ISD = 50A, VDD = 25V
trr Reverse recovery time 80 ns
di/dt = 100A/µs,
Qrr Reverse recovery charge - 250 nC
Tj = 150°C
IRRM Reverse recovery current 6.4 A
(see Figure 16)
1. Pulse width limited by safe operating area.
2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5%

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Electrical characteristics STP40NF10

2.1 Electrical characteristics (curves)

Figure 2. Safe operating area for TO-220 Figure 3. Thermal impedance for TO-220

Figure 4. Output characteristics Figure 5. Transfer characteristics

Figure 6. Transconductance Figure 7. Static drain-source on resistance

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STP40NF10 Electrical characteristics

Figure 8. Gate charge vs. gate-source voltage Figure 9. Capacitance variations

Figure 10. Normalized gate threshold voltage Figure 11. Normalized on resistance vs.
vs. temperature temperature

Figure 12. Source-drain diode forward Figure 13. Normalized breakdown voltage
characteristics vs. Tj

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Test circuit STP40NF10

3 Test circuit

Figure 14. Switching times test circuit for Figure 15. Gate charge test circuit
resistive load
VDD

12V 47kΩ
1kΩ
100nF
RL 2200 3.3
μF μF
VDD IG=CONST
VD Vi=20V=VGMAX 100Ω D.U.T.
VGS 2200
RG D.U.T. μF 2.7kΩ VG

PW
47kΩ

PW 1kΩ
AM01468v1 AM01469v1

Figure 16. Test circuit for inductive load Figure 17. Unclamped Inductive load test
switching and diode recovery times circuit

L
A A A
D
FAST L=100μH VD
G D.U.T. DIODE 2200 3.3
μF μF VDD
S B 3.3 1000
B B μF μF
25 Ω VDD ID
D

RG S
Vi D.U.T.

Pw
AM01470v1 AM01471v1

Figure 18. Unclamped inductive waveform Figure 19. Switching time waveform
V(BR)DSS ton toff
tr tdoff tf
VD tdon

90% 90%
IDM
10%
ID 10% VDS
0

VDD VDD 90%

VGS

AM01472v1 0 10% AM01473v1

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STP40NF10 Package mechanical data

4 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com. ECOPACK
is an ST trademark.

Doc ID 11096 Rev 5 9/12

Package mechanical data STP40NF10

TO-220 type A mechanical data

mm
Dim
Min Typ Max
A 4.40 4.60
b 0.61 0.88
b1 1.14 1.70
c 0.48 0.70
D 15.25 15.75
D1 1.27
E 10 10.40
e 2.40 2.70
e1 4.95 5.15
F 1.23 1.32
H1 6.20 6.60
J1 2.40 2.72
L 13 14
L1 3.50 3.93
L20 16.40
L30 28.90
∅P 3.75 3.85
Q 2.65 2.95

0015988_Rev_S

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STP40NF10 Revision history

5 Revision history

Table 8. Document revision history

Date Revision Changes

16-Dec-2004 1 First version.

17-Aug-2006 2 The document has been reformatted.
31-Jan-2007 3 Typo mistake on Table 2.
19-Sep-2007 4 Added DPAK.
10-Nov-2010 5 Removed DPAK.

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 STP40NF10

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