LMC6482

Datasheet

16 V CMOS dual rail-to-rail input and output, operational amplifiers

Features
• Low input offset voltage: 2 mV max.
• Rail-to-rail input and output
• Excellent CMRR : 98 dB @ 16 V
• Low current consumption: 900 µA max.
MiniSO8 SO8
• Gain bandwidth product: 2.7 MHz
• Low supply voltage: 2.7 - 16 V
• Unity gain stable
• Low input bias current: 50 pA max.
• High ESD tolerance: 4 kV HBM
• Extended temp. range: -40 °C to +125 °C

Applications
• Data acquisition systems
• Battery-powered instrumentation
• Instrumentation amplifier
• Active filtering
• DAC buffer
• High-impedance sensor interface
• Current sensing (high and low side)
Maturity status link

LMC6482 Description
The LMC6482 offer rail-to-rail input and output functionality allowing this product to
be used on full range input and output without limitation.
This rail to rail capability combined with excellent accuracy makes this device ideal
for systems such as data acquisition, that require wide input signal range.
This is particularly useful for a low-voltage supply such as 2.7 V that the LMC6482 is
able to operate with.
Thus, the LMC6482 has the great advantage of offering a large span of supply
voltages, ranging from 2.7 V to 16 V. It can be used in multiple applications with a
unique reference.
Low input bias current performance makes the LMC6482 perfect when used for
signal conditioning in sensor interface applications. In addition, low- side and high-
side current measurements can be easily made thanks to rail-to-rail functionality.

DS12573 - Rev 2 - September 2018 www.st.com

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 LMC6482
Pin configuration

1 Pin configuration

Figure 1. Pin connection (top view)

OUT1 VCC+

IN1- OUT2

IN1+ IN2-

VCC- IN2+

DS12573 - Rev 2 page 2/25

 LMC6482
Absolute maximum ratings and operating conditions

2 Absolute maximum ratings and operating conditions

Table 1. Absolute maximum ratings

Symbol Parameter Value Unit

VCC Supply voltage (1) 18 V

Vid Differential input voltage (2) ±VCC mV

Vin Input voltage (VCC-) - 0.2 to (VCC+) + 0.2 V

Iin Input current (3) 10 mA

Tstg Storage temperature -65 to 150 °C

MiniSO8 190
Rthja Thermal resistance junction to ambient (4)(5) °C/W
SO-8 125
Tj Maximum junction temperature 150 °C

HBM: Human body model (6) 4000

ESD MM: machine model (7) 100 V

CDM: charged device model (8) 1500

Latch-up immunity 200 mA

1. All voltage values, except the differential voltage are with respect to the network ground terminal.
2. Differential voltages are the non-inverting input terminal with respect to the inverting input terminal. See for the precautions
to follow when using LMC6482 with a high differential input voltage.
3. Input current must be limited by a resistor in series with the inputs.
4. Rth are typical values.
5. Short-circuits can cause excessive heating and destructive dissipation.
6. According to JEDEC standard JESD22-A114F.
7. According to JEDEC standard JESD22-A115A.
8. According to ANSI/ESD STM5.3.1.

Table 2. Operating conditions

Symbol Parameter Value Unit

VCC Supply voltage 2.7 to 16

V
Vicm Common mode input voltage range (VCC-) - 0.1 to (VCC+) + 0.1

Toper Operating free air temperature range -40 to +125 °C

DS12573 - Rev 2 page 3/25

 LMC6482
Electrical characteristics

3 Electrical characteristics

VCC+ = +4 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25 ° C, and RL > 10 kΩ connected to VCC/2 (unless otherwise
specified).

Table 3. Electrical characteristics

Symbol Parameter Conditions Min. Typ. Max. Unit

Vicm = VCC/2 2
Vio Input offset voltage mV
Tmin < Top < Tmax 2.5

ΔVio/ΔT Input offset voltage drift (1) 5 µV/°C

nV
ΔVio Long term input offset voltage drift (2) T = 25 °C 1
montℎ
Vout = VCC/2 1 50
Iib Input bias current (1)
Tmin < Top < Tmax 200
pA
Vout = VCC/2 1 50
Iio Input offset current (1)
Tmin < Top < Tmax 200

RIN Input resistance 1 TΩ

CIN Input capacitance 12.5 pF

Vicm = -0.1 to 4.1 V, Vout = VCC/2 65 85

CMRR Common mode rejection ratio 20 log (ΔVic/ΔVio)
Tmin < Top < Tmax 60

RL = 2 kΩ, Vout= 0.3 to 3.7 V 85 136

dB
Tmin < Top < Tmax 80
Avd Large signal voltage gain
RL = 10 kΩ, Vout = 0.2 to 3.8 V 85 140

Tmin < Top < Tmax 80

RL=2 kΩ to VCC/2 28 50

High level output voltage Tmin < Top < Tmax 60

VOH mV
(voltage drop from VCC+) RL = 10 kΩ tο VCC/2 6 15

Tmin < Top < Tmax 20

RL = 2 kΩ tο VCC/2 23 50

Tmin < Top < Tmax 60

VOL Low level output voltage mV
RL = 10 kΩ tο VCC/2 5 15

Tmin < Top < Tmax 20

Vout = VCC 25 37
Isink
Tmin < Top < Tmax 15
Iout mA
Vout = 0 V 35 45
Isource
Tmin < Top < Tmax 20

No load, Vout = VCC/2 570 800

ICC Supply current per amplifier µA
Tmin < Top < Tmax 900

GBP Gain bandwidth product RL = 10 kΩ, CL = 100 pF 1.9 2.7 MHz

DS12573 - Rev 2 page 4/25

 LMC6482
Electrical characteristics

Symbol Parameter Conditions Min. Typ. Max. Unit

ɸm Phase margin RL = 10 kΩ, CL = 100 pF 50 Degrees

Gm Gain margin RL = 10 kΩ, CL = 100 pF 15 dB

Av = 1, Vout = 3 VPP, 10 % to 90% 0.6 0.85

SRn Negative slew rate
Tmin < Top < Tmax 0.5
V/µs
Av = 1, Vout = 3 VPP, 10 % to 90% 1.0 1.4
SRp Positive slew rate
Tmin < Top < Tmax 0.9

f = 1 kHz 22 nV
en Equivalent input noise voltage
f = 10 kHz 19 Hz

f = 1 kHz, Av = 1, RL = 10 kΩ,
THD+N Total harmonic distortion + noise 0.001 %
BW = 22 kHz, Vin = 0.8 VPP

1. Maximum values are guaranteed by design.

2. Typical value is based on the Vio drift observed after 1000h at 125 °C extrapolated to 25 °C using the Arrhenius law and
assuming an activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration (see Section
5.6 Long term input offset voltage drift).

VCC+ = +10 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25 ° C, and RL > 10 kΩ connected to VCC/2 (unless
otherwise specified).

Table 4. Electrical characteristics

Symbol Parameter Conditions Min. Typ. Max. Unit

Vicm = VCC/2 2
Vio Input offset voltage mV
Tmin < Top < Tmax 2.5

ΔVio/ΔT Input offset voltage drift (1) 5 µV/°C

nV
ΔVio Longterm input offset voltage drift (2) T = 25 °C 25
montℎ
Vout = VCC/2 1 50
Iib Input bias current (1)
Tmin < Top < Tmax 200
pA
Vout = VCC/2 1 50
Iio Input offset current (1)
Tmin < Top < Tmax 200

RIN Input resistance 1 TΩ

CIN Input capacitance 12.5 pF

Vicm = -0.1 to 10.1 V, Vout = VCC/2 72 92

CMRR Common mode rejectionratio 20 log (ΔVic/ΔVio)
Tmin < Top < Tmax 67

RL = 2 kΩ, Vout= 0.3 to 9.7 V 90 140

dB
Tmin < Top < Tmax 85
Avd Large signal voltage gain
RL = 10 kΩ, Vout = 0.2 to 9.8 V 90

Tmin < Top < Tmax 85

DS12573 - Rev 2 page 5/25

 LMC6482
Electrical characteristics

Symbol Parameter Conditions Min. Typ. Max. Unit

RL=2 kΩ to VCC/2 45 70

High level output voltage Tmin < Top < Tmax 80

VOH mV
(voltage drop from VCC+) RL = 10 kΩ tο VCC/2 10 30

Tmin < Top < Tmax 40

RL = 2 kΩ tο VCC/2 42 70

Tmin < Top < Tmax 80

VOL Low level output voltage mV
RL = 10 kΩ tο VCC/2 9 30

Tmin < Top < Tmax 40

Vout = VCC 30 39
Isink
Tmin < Top < Tmax 15
Iout mA
Vout = 0 V 50 69
Isource
Tmin < Top < Tmax 40

No load, Vout = VCC/2 630 850

ICC Supply current per amplifier µA
Tmin < Top < Tmax 1000

GBP Gain bandwidth product RL = 10 kΩ, CL = 100 pF 1.9 2.7 MHz

ɸm Phase margin RL = 10 kΩ, CL = 100 pF 53 Degrees

Gm Gain margin RL = 10 kΩ, CL = 100 pF 15 dB

Av = 1, Vout = 8 VPP, 10 % to 90% 0.8 1

SRn Negative slew rate
Tmin < Top < Tmax 0.7
V/µs
Av = 1, Vout = 8 VPP, 10 % to 90% 1.0 1.3
SRp Positive slew rate
Tmin < Top < Tmax 0.9

f = 1 kHz 22 nV
en Equivalent input noise voltage
f = 10 kHz 19 Hz

f = 1 kHz, Av = 1, RL = 10 kΩ,
THD+N Total harmonic distortion + noise 0.0003 %
BW = 22 kHz, Vin = 5 VPP

1. Maximum values are guaranteed by design.

2. Typical value is based on the Vio drift observed after 1000h at 125 °C extrapolated to 25 °C using the Arrhenius law and
assuming an activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration (see Section
5.6 Long term input offset voltage drift).

DS12573 - Rev 2 page 6/25

 LMC6482
Electrical characteristics

VCC+ = +16 V with VCC- = 0 V, Vicm = VCC/2, Tamb = 25 ° C, and RL > 10 kΩ connected to VCC/2 (unless
otherwise specified).

Table 5. Electrical characteristics

Symbol Parameter Conditions Min. Typ. Max. Unit

Vicm = VCC/2 2
Vio Input offset voltage mV
Tmin < Top < Tmax 2.5

ΔVio/ΔT Input offset voltage drift (1) 5 µV/°C

nV
ΔVio Longterm input offset voltage drift (2) T = 25 °C 500
montℎ
Vout = VCC/2 1 50
Iib Input bias current (1)
Tmin < Top < Tmax 200
pA
Vout = VCC/2 1 50
Iio Input offset current (1)
Tmin < Top < Tmax 200

RIN Input resistance 1 TΩ

CIN Input capacitance 12.5 pF

Common mode rejection ratio Vicm = -0.1 to 16.1 V, Vout = VCC/2 75 98

CMRR
20 log (ΔVic/ΔVio) Tmin < Top < Tmax 70

Supply voltage rejection ratio Vcc = 4 to 16 V 100 131

SVRR
20 log (ΔVcc/ΔVio) Tmin < Top < Tmax 90
dB
RL = 2 kΩ, Vout= 0.3 to 15.7 V 90 146

Tmin < Top < Tmax 85

Avd Large signal voltage gain
RL = 10 kΩ, Vout = 0.2 to 15.8 V 90 149

Tmin < Top < Tmax 85

RL = 2 kΩ to V/2 70 130

High level output voltage Tmin < Top < Tmax 150
VOH mV
(voltage drop from VCC+) RL = 10 kΩ 16 40

Tmin < Top < Tmax 50

RL = 2 kΩ 70 130

Tmin < Top < Tmax 150

VOL Low level output voltage mV
RL = 10 kΩ 15 40

Tmin < Top < Tmax 50

Vout = VCC 30 40
Isink
Tmin < Top < Tmax 15
Iout mA
Vout = 0 V 50 68
Isource
Tmin < Top < Tmax 45

No load, Vout = VCC/2 660 900

ICC Supply current per amplifier µA
Tmin < Top < Tmax 1000

GBP Gain bandwidth product RL = 10 kΩ, CL = 100 pF 1.9 2.7 MHz

DS12573 - Rev 2 page 7/25

 LMC6482
Electrical characteristics

Symbol Parameter Conditions Min. Typ. Max. Unit

ɸm Phase margin RL = 10 kΩ, CL = 100 pF 55 Degrees

Gm Gain margin RL = 10 kΩ, CL = 100 pF 15 dB

Av = 1, Vout = 10 VPP, 10 % to 90% 0.7 0.95

SRn Negative slew rate
Tmin < Top < Tmax 0.6
V/µs
Av = 1, Vout = 10 VPP, 10 % to 90% 1 1.4
SRp Positive slew rate
Tmin < Top < Tmax 0.9

f = 1 kHz 22 nV
en Equivalent input noise voltage
f = 10 kHz 19 Hz

f = 1 kHz, Av = 1, RL = 10 kΩ,
THD+N Total harmonic distortion + noise 0.0002 %
BW = 22 kHz, Vin = 10 VPP

1. Maximum values are guaranteed by design.

2. Typical value is based on the Vio drift observed after 1000h at 125 °C extrapolated to 25 °C using the Arrhenius law and
assuming an activation energy of 0.7 eV. The operational amplifier is aged in follower mode configuration (see Section
5.6 Long term input offset voltage drift).

DS12573 - Rev 2 page 8/25

 LMC6482
Electrical characteristic curves

4 Electrical characteristic curves

Figure 2. Supply current vs. supply voltage Figure 3. Input offset voltage distribution at VCC = 16 V

800 30
Vcc=16V
Vicm=Vcc/2 Vicm=8V
25
T=25°C
600
20
Supply Current (µA)

Population (%)
T=-40°C
400 15
T=25°C

T=125°C 10

200
5

0 0
0 2 4 6 8 10 12 14 16 -2.0 -1.6 -1.2 -0.8 -0.4 0.0 0.4 0.8 1.2 1.6 2.0

Supply Voltage (V) Input offset voltage (mV)

Figure 4. Input offset voltage distribution at VCC = 4 V Figure 5. Channel separation

140
30
Vcc=4V
Vicm=2V 0
25
T=25°C
Channel separation (dB)

0
20
Population (%)

80
15
60
10 Vcc=16V
40 Vicm=8V
Gain=1
5 Vin=2Vpp
20 T=25ºC

0
-2.0 -1.6 -1.2 -0.8 -0.4 0.0 0.4 0.8 1.2 1.6 2.0
0
10 100 1k 10k 100k 1M
Input offset voltage (mV)
Frequency (Hz)

DS12573 - Rev 2 page 9/25

 LMC6482
Electrical characteristic curves

Figure 6. Output current vs. output voltage at VCC = 2.7 V Figure 7. Output current vs. output voltage at VCC = 16 V

30 100
Sink Sink
Vid=-1V 75 Vid=-1V
20
50
10

Output Current (mA)

Output Current (mA)

25
T=-40°C T=-40°C
0 T=25°C 0 T=25°C
T=125°C T=125°C
-25
-10
-50
-20
-75
Source Source
Vcc=2.7V Vid=1V Vcc=16V Vid=1V
-30 -100
0.0 0.5 1.0 1.5 2.0 2.5 0 2 4 6 8 10 12 14 16
Output Voltage (V) Output Voltage (V)

Figure 9. Output high voltage (drop from VCC+) vs. supply

Figure 8. Output low voltage vs. supply voltage
voltage
30
Vid=-0.1V 30
25 Rl=10kΩ to Vcc/2 T=-40°C Vid=0.1V
25 Rl=10kΩ to Vcc/2 T=-40°C
Output voltage (from Vcc+) (mV)

T=25°C
20
Output voltage (mV)

T=25°C
20
T=125°C
15 T=125°C
15
10
10

5
5

0
4 6 8 10 12 14 16 0
4 6 8 10 12 14 16
Supply Voltage (V)
Supply Voltage (V)

Figure 10. Output voltage vs. input voltage close to the

Figure 11. Slew rate vs. supply voltage
rail at VCC = 16 V
16.00 2.0

15.95 1.5

15.90 1.0

15.85 0.5
Slew rate (V/µs)
Output voltage (V)

Vicm=Vcc/2
15.80 0.0 Vload=Vcc/2
T=125°C T=25°C T=-40°C Rl=10kΩ
0.15 -0.5 Cl=100pF

0.10 -1.0
Vcc=16V
0.05 Follower configuration -1.5

0.00 -2.0
0.00

0.05

0.10

0.15

15.80

15.85

15.90

15.95

16.00

4 6 8 10 12 14 16
Supply Voltage (V)
Input voltage (V)

DS12573 - Rev 2 page 10/25

 LMC6482
Electrical characteristic curves

Figure 12. Negative slew rate at VCC = 16 V Figure 13. Positive slew rate at VCC = 16 V

6 6
Vcc=16V
4 Vicm=Vcc/2 4
Rl=10kΩ
Cl=100pF
2 2 T=125°C

Signal Amplitude (V)

Signal Amplitude (V)

T=-40°C
0 0
T=25°C
T=25°C
-2 -2
T=125°C T=-40°C
Vcc=16V
-4 -4 Vicm=Vcc/2
Rl=10kΩ
Cl=100pF
-6 -6
-2 0 2 4 6 8 10 12 14 16 18 -2 0 2 4 6 8 10 12 14 16 18
Time (µs) Time (µs)

Figure 15. Recovery behavior after a negative step on the

Figure 14. Response to a small input voltage step
input
0.10
10 0.20
Vcc=16V
Vicm=8V Gain=101
Rl=10kΩ 8 Rl=10kΩ
0.05 0.16
Cl=100pF Vin Cl=100pF
T=25°C T=25°C
Signal Amplitude (V)

6 0.12
Output Voltage (V)

Vcc=±8V

Input voltage (V)

0.00
4 0.08
Vcc=±1.35V
2 0.04
-0.05
0 0.00

-0.10 -2 -0.04
0 5 10 15 -10 0 10 20 30 40
Time (µs) Time (µs)

Figure 16. Recovery behavior after a positive step on the

Figure 17. Bode diagram at VCC = 2.7 V
input
60 0
2 0.04
Phase
50 -30
0 0.00 40 -60
Gain
-2 -0.04 30 -90
Output Voltage (V)

Phase(°)
Gain (dB)
Input voltage (V)

Vcc=±1.35V T=-40°C
20 -120
-4 -0.08
10 -150
Vcc=±8V Vcc=2.7V
-6 -0.12
0 Vicm=1.35V T=25°C -180
Gain=101 Rl=10kΩ
Vin Rl=10kΩ
-8 -0.16 -10 Cl=100pF -210
Cl=100pF Gain=101 T=125°C
T=25°C -20 -240
-10 -0.20 1k 10k 100k 1M 10M
-10 0 10 20 30 40
Frequency (Hz)
Time (µs)

DS12573 - Rev 2 page 11/25

 LMC6482
Electrical characteristic curves

Figure 19. Power supply rejection ratio (PSRR) vs.

Figure 18. Bode diagram at VCC = 16 V
frequency
60 0
120
Phase
50 -30
100
40 -60
PSRR+
Gain
30 -90 80

Phase(°)
Gain (dB)

T=-40°C

PSRR (dB)
20 -120
60
Vcc=16V
10 -150
Vcc=16V Vicm=8V
Vicm=8V T=25°C 40 Gain=1
0 -180
Rl=10kΩ Rl=10kΩ
-10 Cl=100pF -210
Cl=100pF
20 Vosc=200mVPP
Gain=101 T=125°C PSRR-
-20 -240 T=25°C
1k 10k 100k 1M 10M 0
Frequency (Hz) 10 100 1k 10k 100k 1M
Frequency (Hz)

Figure 21. Output impedance vs. frequency in closed loop

Figure 20. Output overshoot vs. capacitive load
configuration
200
10000
175 Vicm=Vcc/2
Rl=10kΩ Vcc=16V
Vin=100mVpp 1000 Vicm=8V
150 Vcc=16V
Gain=1 Gain=1
T=25°C Vosc=30mVRMS
Output impedance ( W )

125
T=25°C
Overshoot (%)

100
100

75 Vcc=2.7V
10
50
1
25

0
10 100 1000 0.1
Cload (pF) 1k 10k 100k 1M 10M
Frequency (Hz)

Figure 22. THD + N vs. frequency Figure 23. THD + N vs. output voltage

1 1
Vcc=16V
Vicm=8V
0.1 Gain=1
0.1
Vin=10Vpp Rl=2kΩ
BW=80kHz
T=25°C Rl=10kΩ
THD + N (%)

THD + N (%)

0.01 0.01

Vcc=16V Rl=100kΩ
Rl=2kΩ
Rl=10kΩ Vicm=8V
1E-3 Rl=100kΩ
1E-3 Gain=1
f=1kHz
BW=22kHz
T=25°C
1E-4 1E-4
100 1000 10000 0.01 0.1 1 10
Frequency (Hz) Output Voltage (Vpp)

DS12573 - Rev 2 page 12/25

 LMC6482
Electrical characteristic curves

Figure 24. Noise vs. frequency Figure 25. 0.1 to 10 Hz noise

140 6
Vcc=16V
Equivalent Input Noise Voltage (nV/VHz)

120 Vcc=16V 4 Vicm=8V

Vicm=Vcc/2 T=25°C
100 T=25°C

Input voltage noise (µV)

2
80
0
60
-2
40
-4
20

0 -6
10 100 1k 10k 0 2 4 6 8 10
Frequency (Hz) Time (s)

DS12573 - Rev 2 page 13/25

 LMC6482
Application information

5 Application information

5.1 Operating voltages

The LMC6482 device can operate from 2.7 to 16 V. The parameters are fully specified for 4 V, 10 V, and 16 V
power supplies. However, the parameters are very stable in the full VCC range. Additionally, the main
specifications are guaranteed in extended temperature ranges from -40 to 125 °C.

5.2 Input pin voltage ranges

The LMC6482 device have internal ESD diode protection on the inputs. These diodes are connected between the
input and each supply rail to protect the input MOSFETs from electrical discharge.
If the input pin voltage exceeds the power supply by 0.5 V, the ESD diodes become conductive and excessive
current can flow through them. Without limitation this over current can damage the device.
In this case, it is important to limit the current to 10 mA, by adding resistance on the input pin, as described in
figure below.

Figure 26. Input current limitation

16 V

R - +
Vout
Vin + -

5.3 Rail-to-rail input

The LMC6482 device have a rail-to-rail input, and the input common mode range is extended from (VCC-) - 0.1 V
to (VCC+) + 0.1 V.

5.4 Rail-to-rail output

The operational amplifier output levels can go close to the rails: to a maximum of 40 mV above and below the rail
when connected to a 10 kΩ resistive load to VCC/2.

5.5 Input offset voltage drift over temperature

The maximum input voltage drift variation over temperature is defined as the offset variation related to the offset
value measured at 25 °C. The operational amplifier is one of the main circuits of the signal conditioning chain, and
the amplifier input offset is a major contributor to the chain accuracy. The signal chain accuracy at 25 °C can be
compensated during production at application level. The maximum input voltage drift over temperature enables
the system designer to anticipate the effect of temperature variations.
The maximum input voltage drift over temperature is computed using Equation 1.
ΔVio Vio T − Vio 25°C
= max (1)
ΔT T − 25°C

where T = -40 °C and 125 °C.

DS12573 - Rev 2 page 14/25

 LMC6482
Long term input offset voltage drift

The LMC6482 datasheet maximum values are guaranteed by measurements on a representative sample size
ensuring a Cpk (process capability index) greater than 1.3.

5.6 Long term input offset voltage drift

To evaluate product reliability, two types of stress acceleration are used:
Voltage acceleration, by changing the applied voltage
Temperature acceleration, by changing the die temperature (below the maximum junction temperature allowed by
the technology) with the ambient temperature.
The voltage acceleration has been defined based on JEDEC results, and is defined using
Equation 2

AFV = ϵβ.VS − VU (2)

where:
AFV is the voltage acceleration factor
β is the voltage acceleration constant in 1/V, constant technology parameter (β = 1)
VS is the stress voltage used for the accelerated test
VU is the voltage used for the application
The temperature acceleration is driven by the Arrhenius model, and is defined in
Equation 3
Ea 1 1
AFT = e k . TU − TS (3)

Where:
AFT is the temperature acceleration factor
Ea is the activation energy of the technology based on the failure rate k is the Boltzmann constant (8.6173 x 10-5
eV.K-1)
TU is the temperature of the die when VU is used (K)
TS is the temperature of the die under temperature stress (K)
The final acceleration factor, AF, is the multiplication of the voltage acceleration factor and the temperature
acceleration factor (Equation 4)
AF = AFT × AFV (4)

AF is calculated using the temperature and voltage defined in the mission profile of the product. The AF value can
then be used in to calculate the number of months of use equivalent to 1000 hours of reliable stress duration.
Montℎs = AF × 1000 ℎ × 12 montℎs/ 24 ℎ × 365.25 days (5)

To evaluate the op amp reliability, a follower stress condition is used where VCC is defined as a function of the
maximum operating voltage and the absolute maximum rating (as recommended by JEDEC rules).
The Vio drift (in µV) of the product after 1000 h of stress is tracked with parameters at different measurement
conditions (see equation 6)
VCC = max VPP witℎ Vicm = VCC /2 (6)

The long term drift parameter (ΔVio), estimating the reliability performance of the product, is obtained using the
ratio of the Vio (input offset voltage value) drift over the square root of the calculated number of months (Equation
7)
Vio drift
ΔVio = (7)
montℎs

Where Vio drift is the measured drift value in the specified test conditions after 1000 h stress duration.

DS12573 - Rev 2 page 15/25

 LMC6482
High values of input differential voltage

5.7 High values of input differential voltage

In a closed loop configuration, which represents the typical use of an op amp, the input differential voltage is low
(close to Vio). However, some specific conditions can lead to higher input differential values, such as:
operation in an output saturation state
operation at speeds higher than the device bandwidth, with output voltage dynamics limited by slew rate.
use of the amplifier in a comparator configuration, hence in open loop
Use of the LMC6482 in comparator configuration, especially combined with high temperature and long duration
can create a permanent drift of Vio.

5.8 Capacitive load

Driving large capacitive loads can cause stability problems. Increasing the load capacitance produces gain
peaking in the frequency response, with overshoot and ringing in the step response. It is usually considered that
with a gain peaking higher than 2.3 dB an op amp might become unstable.
Generally, the unity gain configuration is the worst case for stability and the ability to drive large capacitive loads.
Figure below "Stability criteria with a serial resistor at different supply voltage" shows the serial resistor that must
be added to the output, to make a system stable. The Figure 28. Test configuration for Riso shows the test
configuration using an isolation resistor, Riso.

Figure 27. Stability criteria with a serial resistor at different supply voltage

1000
Vcc=16V

Stable
Vcc=2.7V
Riso ( W )

100
Unstable

Vicm=Vcc/2
Rl=10kΩ
Gain=1
T=25°C
10
100p 1n 10n 100n
Cload (F)

Figure 28. Test configuration for Riso

V CC+

- Riso
VOUT
VIN +
Cload 10 kΩ
V CC-

5.9 PCB layout recommendations

Particular attention must be paid to the layout of the PCB, tracks connected to the amplifier, load, and power
supply. The power and ground traces are critical as they must provide adequate energy and grounding for all
circuits. The best practice is to use short and wide PCB traces to minimize voltage drops and parasitic
inductance.

DS12573 - Rev 2 page 16/25

 LMC6482
Optimized application recommendation

In addition, to minimize parasitic impedance over the entire surface, a multi-via technique that connects the
bottom and top layer ground planes together in many locations is often used.
The copper traces that connect the output pins to the load and supply pins should be as wide as possible to
minimize trace resistance.

5.10 Optimized application recommendation

It is recommended to place a 22 nF capacitor as close as possible to the supply pin. A good decoupling will help
to reduce electromagnetic interference impact.

DS12573 - Rev 2 page 17/25

 LMC6482
Package information

6 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK®
packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions
and product status are available at: www.st.com. ECOPACK® is an ST trademark.

6.1 MiniSO8 package information

Figure 29. MiniSO8 package outline

Table 6. MiniSO8 mechanical data

Dim. Millimeters Inches

Min. Typ. Max. Min. Typ. Max.

A 1.1 0.043
A1 0 0.15 0 0.006
A2 0.75 0.85 0.95 0.03 0.033 0.037
b 0.22 0.4 0.009 0.016
c 0.08 0.23 0.003 0.009
D 2.8 3 3.2 0.11 0.118 0.126
E 4.65 4.9 5.15 0.183 0.193 0.203
E1 2.8 3 3.1 0.11 0.118 0.122
e 0.65 0.026
L 0.4 0.6 0.8 0.016 0.024 0.031
L1 0.95 0.037
L2 0.25 0.01
k 0° 8° 0° 8°
ccc 0.1 0.004

DS12573 - Rev 2 page 18/25

 LMC6482
SO8 package information

6.2 SO8 package information

Figure 30. SO8 package outline

Table 7. SO-8 mechanical data

Millimeters Inches
Dim.
Min. Typ. Max. Min. Typ. Max.

A 1.75 0.069
A1 0.1 0.25 0.004 0.01
A2 1.25 0.049
b 0.28 0.48 0.011 0.019
c 0.17 0.23 0.007 0.01
D 4.8 4.9 5 0.189 0.193 0.197
E 5.8 6 6.2 0.228 0.236 0.244
E1 3.8 3.9 4 0.15 0.154 0.157
e 1.27 0.05
h 0.25 0.5 0.01 0.02
L 0.4 1.27 0.016 0.05
L1 1.04 0.04
k 0 8° 1° 8°
ccc 0.1 0.004

DS12573 - Rev 2 page 19/25

 LMC6482
Ordering information

7 Ordering information

Table 8. Order code

Order code Temperature range Package Packing

LMC6482IDT SO8
-40° to +125 °C Tape and reel
LMC6482IST MiniSO8

DS12573 - Rev 2 page 20/25

 LMC6482

Revision history

Table 9. Document revision history

Date Revision Changes

24-Jul-2018 1 Initial release.

12-Sep-2018 2 Updated the temperature range value in Table 8. Order code.

DS12573 - Rev 2 page 21/25

 LMC6482
Contents

Contents
1 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2 Absolute maximum ratings and operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4 Electrical characteristic curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
5.1 Operating voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2 Input pin voltage ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.3 Rail-to-rail input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.4 Rail-to-rail output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.5 Input offset voltage drift over temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.6 Long term input offset voltage drift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.7 High values of input differential voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.8 Capacitive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.9 PCB layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.10 Optimized application recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

6.1 MiniSO8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.2 SO8 package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

DS12573 - Rev 2 page 22/25

 LMC6482
List of tables

List of tables
Table 1. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Table 2. Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Table 3. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 4. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 5. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 6. MiniSO8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 7. SO-8 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 8. Order code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 9. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

DS12573 - Rev 2 page 23/25

 LMC6482
List of figures

List of figures
Figure 1. Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 2. Supply current vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 3. Input offset voltage distribution at VCC = 16 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4. Input offset voltage distribution at VCC = 4 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 5. Channel separation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 6. Output current vs. output voltage at VCC = 2.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 7. Output current vs. output voltage at VCC = 16 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 8. Output low voltage vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 9. Output high voltage (drop from VCC+) vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 10. Output voltage vs. input voltage close to the rail at VCC = 16 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 11. Slew rate vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 12. Negative slew rate at VCC = 16 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 13. Positive slew rate at VCC = 16 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 14. Response to a small input voltage step . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 15. Recovery behavior after a negative step on the input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 16. Recovery behavior after a positive step on the input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 17. Bode diagram at VCC = 2.7 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 18. Bode diagram at VCC = 16 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 19. Power supply rejection ratio (PSRR) vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 20. Output overshoot vs. capacitive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 21. Output impedance vs. frequency in closed loop configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 22. THD + N vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 23. THD + N vs. output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 24. Noise vs. frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 25. 0.1 to 10 Hz noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 26. Input current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 27. Stability criteria with a serial resistor at different supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 28. Test configuration for Riso . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 29. MiniSO8 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 30. SO8 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

DS12573 - Rev 2 page 24/25

 LMC6482

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST
products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST
products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2018 STMicroelectronics – All rights reserved

DS12573 - Rev 2 page 25/25