MICROCONTROLLERS
Module-2
Dr. Mini K. Namboothiripad
Electrical
Agnel Charities FCRIT Vashi
Indirect Memory Access Instructions
• INDF0 → Access memory at address in FSR0 (no change).
• POSTINC0 → Access memory at FSR0, then increment FSR0.
• POSTDEC0 → Access memory at FSR0, then decrement FSR0.
• PREINC0 → Increment FSR0 first, then access memory.
• PLUSW0 → Access memory at (FSR0 + WREG).
Example with FSR0 and INDF0
LFSR 0, 0x40 ; Load FSR0 with address 0x40
MOVF INDF0, W ; Move [0x40] into WREG via FSR0
Steps Occurred:
1. FSR0 = 0x40
2. Instruction fetches value from memory location 0x40 (via INDF0).
3. That value is sent to WREG.
Example
LFSR 0, 0x40 ; Load FSR0 with address 0x40
MOVF POSTINC0, W ; Move [0x40] into WREG, then increment FSR0 → now
FSR0 = 0x41
Steps Occurred:
1. FSR0 = 0x40
2. Instruction fetches value from memory location 0x40 (via INDF0).
3. That value is sent to WREG.
4. After the operation, FSR0 is automatically incremented to 0x41.
Bit test instructions in PIC18
• BTFSC FileReg, b
• Bit Test File, Skip if Clear
• Tests bit b in file register FileReg
• If the bit = 0 → the next instruction is skipped.
• If the bit = 1 → execution continues normally.
• Example:
• BTFSC 0x20, 0 ; test bit 0 of 0x20
• GOTO odd ; executed only if 0x20’s bit 0 = 1;
If 0x20’s bit 0 = 0, this GOTO is skipped
Bit test instructions in PIC18
• BTFSS FileReg, b
• Bit Test File, Skip if Set
• Tests bit b in file register FileReg
• If the bit = 1 → the next instruction is skipped.
• If the bit = 0 → execution continues normally.
• Example:
• BTFSS 0x20, 0 ; test bit 0 of 0x20
• GOTO NEXT ; executed only if 0x20’s bit 0 = 0;
If 0x20’s bit 0 = 1, this GOTO is skipped
Application
Check a num is even/odd:
BTFSS NUM, 0 ; test LSB if 0➔ even. Else odd
GOTO EVEN ; if bit0 = 0 → EVEN; So execute this ; otherwise skip this
GOTO ODD and go to odd
Examples
• Write a program to add 7F9Ah to BC48H and storing the result in RAM memory
location starting at 40h
• Write a program to subtract 7F9Ah from BC48H and storing the result in RAM
memory location starting at 40h
• Write the steps that the SUB instruction will go through for the following: 23h-12h
Example
Assume WREG=F0h. Perform the following operations. Indicate the result and the
register where it is stored
1. ANDLW 45h
2. IORLW 90h
3. XORLW 76h
Example
Find the content of WREG after the following instructions
1. MOVLW 65h; ANDLW 76h
2. MOVLW 70h ; IORLW 6Bh
3. MOVLW 6Ah; XORLW 6Eh
Data Transfer Instructions
• MOVLW k
• MOVWF FileREg ; Copy from WREG to FileREg
• MOVF FileReg, d ;
• If d=0; Copy from FileReg to WREG
• If d=1; FileREg to itself; Useful for updating flags
• MOVFF FileReg1 FileReg2 ; Copy from Reg1 to Reg2
• MOVLB k ; To select Bank register
• Other Related:
• CLRF f
• CLRW
• SETF f
Arithmetic
• ADDLW k: k+WREG.=WREG
• ADDWF f, d: WREG +f = f/WREG
• ADDWFC f, d: WREG +f +C = f/WREG
• SUBLW k: k-WREG =WREG
• SUBWF f, d: f-WREG =f/WREG
• SUBWFB f, d: f-WREG-C!=f/WREG
• SUBFWB f, d: WREG-f-C! =f/WREG
• MULLW k: Multiplies WREG by k➔ storing the 16-bit result in the PRODH and PRODL registers.
• INCF f,d ; f + 1 → f/WREG
• INCFSZ f,d f + 1, skip next instruction if 0
• DECF f,d f – 1 → f/WREG
• DECFSZ f,d f – 1, skip next instruction if 0
Logical Instructions
• ANDWF f,d ; WREG AND f → WREG/f
• ANDLW k ; WREG AND literal → WREG
• IORWF f,d ; WREG OR f→ WREG/f
• IORLW k ; WREG OR literal → WREG
• XORWF f,d ; WREG XOR f → WREG/f
• XORLW k ; WREG XOR literal → WREG
• COMF f,d ; Bitwise complement
• NEGF f,d ; 2’s Complement
Rotate Instructions
• Rotating the bits of the FileRegister
• RRNCF FileReg,d
• RLNCF FileReg,d
• Rotation through the carry
• RRCF FileReg,d
• RLCF FileReg,d
• SWAPF FileReg, d
• Lower 4-bits put into higher 4-bits
• Higher 4-bits put into Lower 4-bits
Branch Instructions
• Conditional➔ Instruction Jump Condition
BC Branch if carry flag C=1
BNC Branch if carry flag C=0
• Unconditional BZ Branch if Zero
• GOTO BNZ Branch if Not Zero
• BRA
BN Branch if Negative
BNN Branch if Not Negative
BOV Branch if OV=1
BNOV Branch if OV=0
Compare Instructions
• CPFSGT
• CPFSEQ
• CPFSLT
