Experiment 8: Design Verilog program for implementing various
types of Flip-Flops such as SR, JK and D.
Objective: To understand and implement fundamental sequential logic elements
(Flip-Flops) using Verilog HDL.
Design Approach (Flip-Flops - FFs):
Flip-flops are memory elements that store a single bit of information. They
are edge-triggered (usually on positive or negative clock edge).
SR Flip-Flop: Set-Reset. Can have an indeterminate state (SR=11). Often
implemented with NOR or NAND gates. In behavioral Verilog, you handle
the if (S && R) condition.
JK Flip-Flop: Overcomes the indeterminate state of SR. If JK=11, it toggles.
D Flip-Flop: Data Flip-Flop. Output takes the value of the D input at the
active clock edge. Most widely used FF.
Modeling Styles:
Exclusively Behavioral modeling using always @(posedge clk or negedge clk
or posedge reset) blocks is the standard and most appropriate way to
describe sequential logic (flip-flops) in Verilog.
Simulation Package Preferred:
ModelSim: Essential for simulating sequential logic and observing state
changes over time with clock signals.
Steps:
1. Design Each Flip-Flop: Create separate Verilog modules for SR, JK, and D
flip-flops.
o Include inputs for clock (clk) and an optional asynchronous reset
(reset).
o Use an always block sensitive to the clock edge and/or reset.
o D Flip-Flop Example (positive edge-triggered, synchronous reset):
Verilog
module D_FF (output reg Q, input D, clk, rst_n); // rst_n is active low reset
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin // Asynchronous active-low reset
Q <= 1'b0;
end else begin
Q <= D; // Update Q with D on positive clock edge
end
end
endmodule
o JK Flip-Flop Example (positive edge-triggered, synchronous reset,
handling toggle):
Verilog
module JK_FF (output reg Q, input J, K, clk, rst_n);
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
Q <= 1'b0;
end else begin
case ({J, K})
2'b00: Q <= Q; // Hold
2'b01: Q <= 1'b0; // Reset
2'b10: Q <= 1'b1; // Set
2'b11: Q <= ~Q; // Toggle
endcase
end
end
endmodule
2. Create Testbenches: Develop a testbench for each FF, providing a clock
signal, reset pulses, and varying inputs (S/R, J/K, D) to test all operating
conditions.
3. Simulate in ModelSim: Compile, simulate, and meticulously analyze the
waveforms to ensure that the Q output changes correctly on the active
clock edge according to the FF's characteristic table.
